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31. 发明申请

US20130322762A1 System and Method to Perform Feature Detection and to Determine a Feature Score 有权
标题翻译：执行特征检测并确定特征得分的系统和方法
公开(公告)号：US20130322762A1
公开(公告)日：2013-12-05
申请号：US13602677
申请日：2012-09-04
申请人： Mao Zeng , Erich James Plondke , Lucian Codrescu
发明人： Mao Zeng , Erich James Plondke , Lucian Codrescu
IPC分类号： G06K9/68 , G06K9/46
CPC分类号： G06K9/4638
摘要： A system and method of processing an image is disclosed. A particular method of determining whether a particular pixel of an image is a feature includes receiving data corresponding to a plurality of pixels (from the image) surrounding the particular pixel. The method further includes determining a set of comparison results, each corresponding to one of the plurality of pixels and indicating a result of comparing an attribute value corresponding to one of the plurality of pixels to a comparison value (based on a particular attribute value of the particular pixel and a threshold value). The method further includes performing a processor-executable instruction that, when executed by a processor, causes the processor to identify a subset of the set of comparison results that indicate the particular pixel is the feature. The identified subset may be a consecutive order of pixels of the plurality of pixels.
摘要翻译：公开了一种处理图像的系统和方法。确定图像的特定像素是否是特征的特定方法包括接收与围绕特定像素的多个像素（来自图像）相对应的数据。所述方法还包括确定一组比较结果，每一个对应于所述多个像素之一并且指示将与所述多个像素中的一个相对应的属性值与比较值（基于所述多个像素的特定属性值）进行比较的结果特定像素和阈值）。所述方法还包括执行处理器可执行指令，所述指令在由处理器执行时使所述处理器识别所述特定像素是所述特征的所述一组比较结果的子集。所识别的子集可以是多个像素的像素的连续顺序。

32. 发明申请

US20120297256A1 Large Ram Cache 审中-公开
标题翻译：大Ram缓存
公开(公告)号：US20120297256A1
公开(公告)日：2012-11-22
申请号：US13112132
申请日：2011-05-20
申请人： Erich James Plondke , Lucian Codrescu , William C. Anderson
发明人： Erich James Plondke , Lucian Codrescu , William C. Anderson
IPC分类号： G06F12/00 , G06F11/16 , G06F12/08
CPC分类号： G06F12/0893 , G06F11/1064 , G06F12/0646 , Y02D10/13
摘要： Systems and method for configuring a page-based memory device without pre-existing dedicated metadata. The method includes reading metadata from a metadata portion of a page of the memory device, and determining a characteristic of the page based on the metadata. The memory device may be configured as a cache. The metadata may include address tags, such that determining the characteristic may include determining if desired information is present in the page, and reading the desired information if it is determined to be present in the page. The metadata may also include error-correcting code (ECC), such that determining the characteristic may include detecting errors present in data stored in the page. The metadata may further include directory information, memory coherency information, or dirty/valid/lock information.
摘要翻译：用于配置基于页面的存储设备而不具有预先存在的专用元数据的系统和方法。该方法包括从存储设备的页面的元数据部分读取元数据，以及基于元数据确定页面的特性。存储器件可以被配置为高速缓存。元数据可以包括地址标签，使得确定特征可以包括确定页面中是否存在所需信息，并且如果确定存在于页面中则读取所需信息。元数据还可以包括纠错码（ECC），使得确定特性可以包括检测存在于页面中的数据中存在的错误。元数据还可以包括目录信息，存储器一致性信息或脏/有效/锁定信息。

33. 发明申请

US20110125987A1 Dedicated Arithmetic Decoding Instruction 审中-公开
标题翻译：专用算术解码指令
公开(公告)号：US20110125987A1
公开(公告)日：2011-05-26
申请号：US12622998
申请日：2009-11-20
申请人： Erich James Plondke , Lucian Codrescu , Ajay Anant Ingle , Mao Zeng , Christopher Edward Koob , Charles Joseph Tabony
发明人： Erich James Plondke , Lucian Codrescu , Ajay Anant Ingle , Mao Zeng , Christopher Edward Koob , Charles Joseph Tabony
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： H03M7/4006 , G06F9/30018 , G06F9/3895 , H04N19/13 , H04N19/436 , H04N19/44 , H04N19/61
摘要： A dedicated arithmetic decoding instruction is disclosed. In a particular embodiment, an apparatus includes a memory and a processor coupled to the memory. The processor is configured to execute general purpose instructions and to execute a dedicated arithmetic decoding instruction retrieved from the memory.
摘要翻译：公开了专用算术解码指令。在特定实施例中，装置包括存储器和耦合到存储器的处理器。处理器被配置为执行通用指令并且执行从存储器检索的专用算术解码指令。

34. 发明申请

US20100242041A1 Real Time Multithreaded Scheduler and Scheduling Method 有权
标题翻译：实时多线程调度程序和调度方法
公开(公告)号：US20100242041A1
公开(公告)日：2010-09-23
申请号：US12405271
申请日：2009-03-17
申请人： Erich James Plondke , Lucian Codrescu
发明人： Erich James Plondke , Lucian Codrescu
IPC分类号： G06F9/46
CPC分类号： G06F9/3851 , G06F9/4812 , G06F9/4881
摘要： In a particular embodiment, a method is disclosed that includes receiving an interrupt at a first thread, the first thread including a lowest priority thread of a plurality of executing threads at a processor at a first time. The method also includes identifying a second thread, the second thread including a lowest priority thread of a plurality of executing threads at a processor at a second time. The method further includes directing a subsequent interrupt to the second thread.
摘要翻译：在特定实施例中，公开了一种包括在第一线程处接收中断的方法，所述第一线程在第一时间包括处理器处的多个执行线程的最低优先级线程。所述方法还包括识别第二线程，所述第二线程在第二时间包括处理器处的多个执行线程的最低优先级线程。该方法还包括将后续中断引导到第二线程。

35. 发明申请

US20090228688A1 Dual Function Adder for Computing a Hardware Prefetch Address and an Arithmetic Operation Value 失效
标题翻译：用于计算硬件预取地址和算术运算值的双功能加法器
公开(公告)号：US20090228688A1
公开(公告)日：2009-09-10
申请号：US12041694
申请日：2008-03-04
申请人： Ajay Anant Ingle , Erich James Plondke , Lucian Codrescu
发明人： Ajay Anant Ingle , Erich James Plondke , Lucian Codrescu
IPC分类号： G06F9/30
CPC分类号： G06F9/383 , G06F9/3001
摘要： A system including a dual function adder is described. In one embodiment, the system includes an adder. The adder is configured for a first instruction to determine an address for a hardware prefetch if the first instruction is a hardware prefetch instruction. The adder is further configures for the first instruction to determine a value from an arithmetic operation if the first instruction is an arithmetic operation instruction.
摘要翻译：描述了包括双功能加法器的系统。在一个实施例中，该系统包括加法器。如果第一指令是硬件预取指令，则加法器被配置用于第一指令以确定用于硬件预取的地址。如果第一指令是算术运算指令，则加法器进一步配置用于从算术运算确定值的第一指令。

36. 发明授权

US09823928B2 FIFO load instruction 有权
公开(公告)号：US09823928B2
公开(公告)日：2017-11-21
申请号：US13249284
申请日：2011-09-30
申请人： Mao Zeng , Lucian Codrescu , Erich James Plondke , Ajay Anant Ingle
发明人： Mao Zeng , Lucian Codrescu , Erich James Plondke , Ajay Anant Ingle
IPC分类号： G06F9/30
CPC分类号： G06F9/3004 , G06F9/30032 , G06F9/30043
摘要： An instruction identifies a register and a memory location. Upon execution of the instruction by a processor, an item is loaded from the memory location and a shift and insert operation is performed to shift data in the register and to insert the item into the register.

37. 发明授权

US09361109B2 System and method to evaluate a data value as an instruction 有权
标题翻译：将数据值作为指令进行评估的系统和方法
公开(公告)号：US09361109B2
公开(公告)日：2016-06-07
申请号：US12785551
申请日：2010-05-24
申请人： Lucian Codrescu , Erich James Plondke , Suresh Venkumahanti
发明人： Lucian Codrescu , Erich James Plondke , Suresh Venkumahanti
IPC分类号： G06F9/30 , G06F9/32 , G06F9/26
CPC分类号： G06F9/322 , G06F9/26 , G06F9/328
摘要： A system and method to evaluate a data value as an instruction is disclosed. For example, an apparatus configured to execute program code includes an execute unit configured to execute a first instruction associated with a location of a second instruction. The first instruction is identified by a program counter. The apparatus also includes a decode unit configured to receive the second instruction from the location and to decode the second instruction to generate a decoded second instruction without changing the program counter to point to the second instruction.
摘要翻译：公开了一种用于评估数据值作为指令的系统和方法。例如，被配置为执行程序代码的装置包括执行单元，被配置为执行与第二指令的位置相关联的第一指令。第一条指令由程序计数器识别。所述装置还包括：解码单元，被配置为从所述位置接收所述第二指令，并且解码所述第二指令以生成解码的第二指令，而不改变所述程序计数器以指向所述第二指令。

38. 发明授权

US08656145B2 Methods and systems for allocating interrupts in a multithreaded processor 有权
标题翻译：用于在多线程处理器中分配中断的方法和系统
公开(公告)号：US08656145B2
公开(公告)日：2014-02-18
申请号：US12233688
申请日：2008-09-19
申请人： Erich James Plondke , Lucian Codrescu
发明人： Erich James Plondke , Lucian Codrescu
IPC分类号： G06F9/48
CPC分类号： G06F9/4818
摘要： A multithreaded processor capable of allocating interrupts is described. In one embodiment, the multithreaded processor includes an interrupt module and threads for executing tasks. The interrupt module can identify a priority for each thread based on a task priority for tasks being executed by the threads and assign an interrupt to a thread based at least on its priority.
摘要翻译：描述了能够分配中断的多线程处理器。在一个实施例中，多线程处理器包括用于执行任务的中断模块和线程。中断模块可以基于线程执行的任务的任务优先级来识别每个线程的优先级，并且至少基于其优先级为线程分配中断。

39. 发明授权

US08631056B2 Processor and method of determining a normalization count 失效
标题翻译：处理器和确定归一化计数的方法
公开(公告)号：US08631056B2
公开(公告)日：2014-01-14
申请号：US11971230
申请日：2008-01-09
申请人： Shankar Krithivasan , Erich James Plondke , Lucian Codrescu , Mao Zeng
发明人： Shankar Krithivasan , Erich James Plondke , Lucian Codrescu , Mao Zeng
IPC分类号： G06F7/00
CPC分类号： G06F7/74 , G06F7/49936
摘要： In a particular embodiment, a method is disclosed that includes receiving an operand to be normalized at a normalization logic circuit, where the operand includes a plurality of bits. The method further includes generating a zero output when a value of the operand is equal to zero and, when the value is not equal to zero, generating an output value representing a number that is one less than a count of leading bits of the operand.
摘要翻译：在特定实施例中，公开了一种方法，其包括接收在归一化逻辑电路中归一化的操作数，其中操作数包括多个位。该方法还包括当操作数的值等于零时产生零输出，并且当该值不等于零时，生成表示小于该操作数的前导位的计数的数字的输出值。

40. 发明申请

US20130212357A1 Floating Point Constant Generation Instruction 审中-公开
标题翻译：浮点常数生成指令
公开(公告)号：US20130212357A1
公开(公告)日：2013-08-15
申请号：US13369693
申请日：2012-02-09
申请人： Erich James Plondke , Lucian Codrescu , Charles Joseph Tabony , Swaminathan Balasubramanian
发明人： Erich James Plondke , Lucian Codrescu , Charles Joseph Tabony , Swaminathan Balasubramanian
IPC分类号： G06F9/30 , G06F9/302
CPC分类号： G06F9/30014 , G06F9/30025 , G06F9/30167
摘要： Systems and methods for generating a floating point constant value from an instruction are disclosed. A first field of the instruction is decoded as a sign bit of the floating point constant value. A second field of the instruction is decoded to correspond to an exponent value of the floating point constant value. A third field of the instruction is decoded to correspond to the significand of the floating point constant value. The first field, the second field, and the third field are combined to form the floating point constant value. The exponent value may include a bias, and a bias constant may be added to the exponent value to compensate for the bias. The third field may comprise the most significant bits of the significand. Optionally, the second field and the third field may be shifted by first and second shift values respectively before they are combined to form the floating point constant value.
摘要翻译：公开了从指令生成浮点常数值的系统和方法。指令的第一个字段被解码为浮点常数值的符号位。指令的第二个字段被解码以对应于浮点常数值的指数值。指令的第三个字段被解码以对应于浮点常数值的有效位数。第一个字段，第二个字段和第三个字段组合起来形成浮点常量值。指数值可以包括偏置，并且可以将偏置常数加到指数值以补偿偏差。第三个字段可以包括有效位的最高有效位。可选地，第二场和第三场可以在组合之前分别移位第一和第二移位值以形成浮点常数值。

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