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    • 33. 发明授权
      US06181014B2 Integrated circuit memory devices having highly integrated SOI memory cells therein 有权
    • Integrated circuit memory devices having highly integrated SOI memory cells therein
    • 在其中具有高度集成的SOI存储器单元的集成电路存储器件
    • US06181014B2
    • 2001-01-30
    • US09271519
    • 1999-03-18
    • Kyu-Charn Park , Duck-Hyung Lee
    • Kyu-Charn Park , Duck-Hyung Lee
    • H01L2348
    • H01L27/10858 , H01L27/10885 , H01L27/1203 , H01L2924/0002 , Y10S257/907 , Y10S257/908 , H01L2924/00
    • Integrated circuit memory devices having highly integrated SOI memory cells therein include an SOI substrate having a semiconductor active layer therein. A first trench isolation region is also provided. The first trench isolation region extends into and partitions the semiconductor active layer into first and second active regions. These first and second active regions are preferably electrically isolated from each other by the first trench isolation region. First and second access transistors are provided in the first and second active regions, respectively, and a first electrically insulating layer is provided on the SOI substrate. A first bit line is also provided at a first level. The first bit line is electrically connected to a first source/drain region of the first access transistor by a first bit line contact. This first bit line contact extends through the first electrically insulating layer and contacts the first source/drain region of the first access transistor. A second electrically insulating layer is also provided on the first bit line, opposite said first electrically insulating layer and a second bit line is provided on the second electrically insulating layer at a second level above the first level. The second bit line is electrically connected to a first source/drain region of the second access transistor by a second bit line contact which extends through the first and second electrically insulating layers and contacts the first source/drain region of the second access transistor. Higher integration densities can be achieved by dividing the active layer into electrically isolated active regions and then forming bit lines at different levels which are electrically connected to access transistors within these isolated active regions.
    • 其中具有高度集成的SOI存储单元的集成电路存储器件包括其中具有半导体有源层的SOI衬底。 还提供了第一沟槽隔离区域。 第一沟槽隔离区延伸到半导体活性层并将其分隔成第一和第二有源区。 这些第一和第二有源区优选地通过第一沟槽隔离区彼此电隔离。 第一和第二存取晶体管分别设置在第一和第二有源区中，并且第一电绝缘层设置在SOI衬底上。 在第一级还提供第一位线。 第一位线通过第一位线接触电连接到第一存取晶体管的第一源极/漏极区域。 该第一位线接触件延伸穿过第一电绝缘层并接触第一存取晶体管的第一源极/漏极区域。 在第一位线上还设有第二电绝缘层，与第一电绝缘层相对，并且第二位线在第二电绝缘层上设置在高于第一电平的第二电平上。 第二位线通过延伸穿过第一和第二电绝缘层并接触第二存取晶体管的第一源/漏区的第二位线接触电连接到第二存取晶体管的第一源/漏区。 可以通过将有源层分为电隔离的有源区，然后形成与这些隔离的有源区内的存取晶体管电连接的不同电平的位线来实现更高的积分密度。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 34. 发明授权
      US06171942B2 Methods of forming electrically conductive lines in integrated circuit memories using self-aligned silicide blocking layers 有权
    • Methods of forming electrically conductive lines in integrated circuit memories using self-aligned silicide blocking layers
    • 在使用自对准硅化物阻挡层的集成电路存储器中形成导电线的方法
    • US06171942B2
    • 2001-01-09
    • US09283226
    • 1999-04-01
    • Duck-Hyung Lee , Jong-Woo Park
    • Duck-Hyung Lee , Jong-Woo Park
    • H01L2170
    • H01L27/10888 , H01L21/76897 , H01L27/10894
    • Conductive lines are formed in integrated circuit memories using a Silicide blocking layer that is self-aligned. The Silicide blocking layer is self-aligned by etching an electrically insulating layer that is formed between a electrically conductive lines on a substrate in an integrated circuit memory. The etching removes the electrically insulating layer from the outer surfaces of the electrically conductive lines, but leaves a portion of the electrically insulating layer on the substrate between the electrically conductive lines. The portion of the electrically insulating layer remaining on the substrate may prevent the formation of a Silicide film on the substrate during a heating step used to form contacts on the outer surfaces of the electrically conductive lines. The self-aligned Silicide blocking layer may allow a reduction in the number of steps in the fabrication of the contacts and reduce the need to align a mask to the substrate to form the Silicide blocking layer.
    • 使用自对准的硅化物阻挡层在集成电路存储器中形成导电线。 通过蚀刻形成在集成电路存储器中的基板上的导电线之间的电绝缘层，自对准硅化物阻挡层。 该蚀刻从电导线的外表面去除电绝缘层，但是在导电线之间留下基板上的电绝缘层的一部分。 保留在基板上的电绝缘层的部分可以防止在用于在导电线的外表面上形成接触的加热步骤中在基板上形成硅化硅膜。 自对准的硅化物阻挡层可以允许减少接触的制造中的步骤数量，并且减少将掩模对准衬底以形成硅化物阻挡层的需要。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
    • 35. 发明授权
      US6015748A Methods of fabricating integrated circuit memory devices including silicide blocking layers on memory cell transistor source and drain regions 有权
    • Methods of fabricating integrated circuit memory devices including silicide blocking layers on memory cell transistor source and drain regions
    • 在存储单元晶体管源极和漏极区域上制造包括硅化物阻挡层的集成电路存储器件的方法
    • US6015748A
    • 2000-01-18
    • US304355
    • 1999-05-04
    • Hong-Ki Kim , Duck-Hyung Lee , Chang-Sik Choi
    • Hong-Ki Kim , Duck-Hyung Lee , Chang-Sik Choi
    • H01L27/108 , H01L21/8239 , H01L27/105 , H01L21/3205
    • H01L27/105 , H01L27/1052
    • Integrated circuit memory devices are fabricated by fabricating an array of memory cell field effect transistors and peripheral circuit field effect transistors that are spaced-apart from the memory cell transistors, in an integrated circuit substrate. The memory cell transistors include spaced-apart memory cell transistor source and drain regions and a memory cell gate therebetween. The peripheral circuit transistors include spaced-apart peripheral circuit transistor source and drain regions and a peripheral circuit gate therebetween. A silicide blocking layer is formed on the memory cell transistor source and drain regions. The integrated circuit substrate is silicided to thereby form a silicide layer on the memory cell transistor gates, on the peripheral circuit source and drain regions and on the peripheral circuit gates, such that the memory cell transistor source and drain regions are free of the silicide layer thereon. Accordingly, low contact resistance silicide regions may be selectively provided in memory cells without degrading the leakage characteristics thereof.
    • 集成电路存储器件通过在集成电路衬底中制造与存储单元晶体管间隔开的存储单元场效应晶体管阵列和外围电路场效应晶体管来制造。 存储单元晶体管包括间隔开的存储单元晶体管源极和漏极区以及它们之间的存储单元栅极。 外围电路晶体管包括间隔开的外围电路晶体管源极和漏极区域以及其间的外围电路栅极。 在存储单元晶体管源极和漏极区域上形成硅化物阻挡层。 集成电路基板被硅化，从而在外围电路源极和漏极区域以及外围电路栅极上的存储单元晶体管栅极上形成硅化物层，使得存储单元晶体管源极和漏极区域不含硅化物层 上。 因此，可以在存储单元中选择性地提供低接触电阻硅化物区域，而不会降低其泄漏特性。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 40. 发明授权
      US08154097B2 Image sensor and method of manufacturing the same 有权
    • Image sensor and method of manufacturing the same
    • 图像传感器及其制造方法
    • US08154097B2
    • 2012-04-10
    • US12266856
    • 2008-11-07
    • Hong-Ki Kim , Duck-Hyung Lee , Hyun-Pil Noh
    • Hong-Ki Kim , Duck-Hyung Lee , Hyun-Pil Noh
    • H01L31/09
    • H01L27/14632 , H01L27/14636 , H01L27/14685
    • An image sensor and a method of manufacturing the same are provided. The image sensor includes a substrate having a sensor array area and a peripheral circuit area a first insulating film structure formed on the peripheral circuit area and including a plurality of first multi-layer wiring lines and a second insulating film structure formed on the sensor array area and including a plurality of second multi-layer wiring lines. The uppermost-layer wiring line of the plurality of first multi-layer wiring lines is higher than that of the uppermost-layer wiring line of the plurality of second multi-layer wiring lines. The first insulating film structure includes an isotropic etch-stop layer, and the second insulating film structure does not include the isotropic etch-stop layer.
    • 提供了图像传感器及其制造方法。 图像传感器包括具有传感器阵列区域的基板和形成在外围电路区域上的第一绝缘膜结构的外围电路区域，并且包括多个第一多层布线和形成在传感器阵列区域上的第二绝缘膜结构 并且包括多个第二多层布线。 多个第一多层布线的最上层布线比多个第二多层布线的最上层布线高。 第一绝缘膜结构包括各向同性蚀刻停止层，第二绝缘膜结构不包括各向同性蚀刻停止层。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Espacenet 法律信息 同族专利 专利引用
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