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31. 发明授权

US5831457A Input buffer circuit immune to common mode power supply fluctuations 失效
标题翻译：输入缓冲电路免受共模电源波动
公开(公告)号：US5831457A
公开(公告)日：1998-11-03
申请号：US477283
申请日：1995-06-07
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： H03K5/08 , H03B1/00 , H03K17/16 , H03K19/003
CPC分类号： H03K17/161 , H03K19/00361
摘要： The present invention provides an input buffer circuit for reducing false transitions within a circuit. The input buffer circuit includes an input pad for receiving an input voltage, an input buffer having an input and a circuit for modifying a voltage entering the input buffer to track changes in a power supply voltage relative to a voltage at the input pad. The circuit is connected in series between the input pad and the input the input buffer.
摘要翻译：本发明提供一种用于减少电路内的错误转换的输入缓冲器电路。输入缓冲电路包括用于接收输入电压的输入焊盘，具有输入的输入缓冲器和用于修改进入输入缓冲器的电压的电路，以跟踪相对于输入焊盘处的电压的电源电压的变化。该电路串联连接在输入焊盘和输入缓冲器之间。

32. 发明授权

US5801563A Output driver circuitry having a single slew rate resistor 失效
标题翻译：具有单个压摆率电阻器的输出驱动器电路
公开(公告)号：US5801563A
公开(公告)日：1998-09-01
申请号：US588988
申请日：1996-01-19
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： H03K5/1252 , H03K19/00 , H03K19/0175 , H03K5/12 , H03K17/687
CPC分类号： H03K19/0013
摘要： An output driver circuit an integrated circuit memory device prevents crowbar currents from occurring. The output driver uses just one resistive element having multiple taps so that the amount of silicon area used for slew rate control is minimized. The signals which control the output driver devices are carefully balanced for no skew and cross at a voltage level of Vcc/2 so that there is no crowbar current generated during tri-stating of the output driver output signal.
摘要翻译：输出驱动器电路集成电路存储器件防止发生撬棒电流。输出驱动器仅使用具有多个抽头的一个电阻元件，使得用于转换速率控制的硅面积的量被最小化。控制输出驱动器器件的信号在Vcc / 2的电压电平下不会出现偏斜和交叉，因此在输出驱动器输出信号三态期间不产生紧急电流。

33. 发明授权

US5764592A External write pulse control method and structure 失效
标题翻译：外部写脉冲控制方法和结构
公开(公告)号：US5764592A
公开(公告)日：1998-06-09
申请号：US771642
申请日：1996-12-21
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G01R31/28 , G01R31/3185 , G11C7/22 , G11C11/401 , G11C11/407 , G11C11/413 , G11C29/02 , G11C29/50 , G11C7/00
CPC分类号： G11C29/028 , G11C29/02 , G11C29/50 , G11C29/50012 , G11C7/22
摘要： A method and control circuit structure for externally controlling the width of a write pulse of a synchronous integrated circuit memory device is disclosed. The method and control circuit provide for a test mode in which the width of the write pulse of the synchronous integrated circuit memory device may be externally controlled to be entered. After entering the test mode, the start of a write pulse of the synchronous integrated circuit memory device is triggered by a transition of a clock signal from a first logic state to a second logic state. The termination of the write pulse is accomplished by selective manipulation of an external control signal external to the synchronous integrated circuit memory device.
摘要翻译：公开了一种外部控制同步集成电路存储器件写入脉冲的宽度的方法和控制电路结构。该方法和控制电路提供了一种测试模式，其中同步集成电路存储器件的写入脉冲的宽度可以被外部控制输入。在进入测试模式之后，通过从第一逻辑状态到第二逻辑状态的时钟信号的转变来触发同步集成电路存储器件的写入脉冲的开始。通过选择性地操纵同步集成电路存储器件外部的外部控制信号来实现写入脉冲的终止。

34. 再颁专利

USRE41337E1 Synchronous test mode initialization 有权
标题翻译：同步测试模式初始化
公开(公告)号：USRE41337E1
公开(公告)日：2010-05-18
申请号：US09596027
申请日：2000-06-15
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： H03K5/13
CPC分类号： G01R31/31726 , G01R31/31701 , G06F11/2284 , G11C29/46 , G11C2029/0407
摘要： The entire data path of a synchronous integrated circuit device is initialized in a test mode upon power-up of the synchronous integrated circuit device. Upon power-up of the integrated circuit device in the test mode, a clock signal (either an external clock signal or an associated internal clock signal) is internally clocked. As the clock signal goes to a low logic state upon power-up of the device, a master latch (flip-flop) flip-flop element of the integrated circuit device is loaded with data and is allowed to conduct; a slave latch (flip-flop) flip-flop element of the integrated circuit device does not conduct. As the clock signal goes to a high logic state, the data in the master latch is latched. Also upon the high logic state of the clock, the slave latch element is loaded with data and is allowed to conduct.
摘要翻译：同步集成电路器件的整个数据通道在同步集成电路器件上电时以测试模式被初始化。在测试模式下，集成电路器件上电时，时钟信号（外部时钟信号或相关的内部时钟信号）都在内部时钟。随着器件上电时时钟信号进入低逻辑状态，集成电路器件的主锁存器（触发器）触发器元件被加载数据并被允许导通; 集成电路器件的从锁存器（触发器）触发器元件不导通。当时钟信号变为高逻辑状态时，主锁存器中的数据被锁存。此外，在时钟的高逻辑状态下，从锁存元件被加载数据并被允许进行。

35. 发明授权

US07368947B2 Voltage translating control structure 有权
标题翻译：电压转换控制结构
公开(公告)号：US07368947B2
公开(公告)日：2008-05-06
申请号：US11012533
申请日：2004-12-15
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K3/356113 , H03K17/693
摘要： A voltage translating control structure for switching logic is described. A battery drain problem is corrected by this structure. The voltage translating feature allows reliable switching between power supply and battery even if the power supply voltage has significantly decreased. Operation is adaptable to include all DC power systems. Logic circuitry that also allows voltage translation is presented.
摘要翻译：描述了用于开关逻辑的电压转换控制结构。通过这种结构来纠正电池排出问题。电压转换功能允许电源和电池之间的可靠切换，即使电源电压显着降低。操作适应于包括所有直流电源系统。还提供了允许电压转换的逻辑电路。

36. 发明授权

US07208987B2 Reset initialization 有权
标题翻译：重置初始化
公开(公告)号：US07208987B2
公开(公告)日：2007-04-24
申请号：US10999751
申请日：2004-11-30
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： H03L7/00
CPC分类号： H03K17/223 , G06F1/24 , H03K3/356008
摘要： A reset initialization structure and method is described. A power on reset pulse is utilized to force the state of system reset during intervals of Vcc which otherwise would result in indeterminate reset states. Operation is adaptable to include all DC power systems. The reset initialization structure provides operational protection during power up and power down conditions.
摘要翻译：描述了复位初始化结构和方法。上电复位脉冲用于在Vcc的间隔期间迫使系统复位状态，否则将导致不确定的复位状态。操作适应于包括所有直流电源系统。复位初始化结构在上电和掉电条件下提供操作保护。

37. 发明授权

US6059450A Edge transition detection circuitry for use with test mode operation of an integrated circuit memory device 失效
标题翻译：用于与集成电路存储器件的测试模式操作一起使用的边沿转换检测电路
公开(公告)号：US6059450A
公开(公告)日：2000-05-09
申请号：US771643
申请日：1996-12-21
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G11C7/10 , G11C8/18 , G11C29/46 , H03K5/1534 , G11C7/00
CPC分类号： G11C7/1045 , G11C29/46 , G11C8/18 , H03K5/1534
摘要： An integrated circuit structure and method provides for an integrated circuit device to respond to an edge transition detection (ETD) pulse in one of two ways. First, in response to the ETD pulse, the integrated circuit device exits a test mode at least temporarily every cycle of the integrated circuit device. Second, a node of the integrated circuit device is re-initialized every cycle if it is not forced by a super voltage indicative of test mode entry. Both of these responses prevent accidental entry of the integrated circuit device into the test mode. If the integrated circuit device is supposed to be in the test mode, it stays in the test mode. If, however, the integrated circuit device is not intended to be in the test mode, the ETD pulse forces the integrated circuit device out of the test mode. Subsequent entry into the test mode of the device is permitted if conditions for entry into the test mode have otherwise been met.
摘要翻译：集成电路结构和方法提供集成电路器件以两种方式之一响应边沿跃迁检测（ETD）脉冲。首先，响应于ETD脉冲，集成电路器件至少临时地在集成电路器件的每个周期暂时退出测试模式。第二，如果集成电路设备的节点不被强制指示测试模式进入的超级电压强制，则每个周期都重新初始化集成电路设备的节点。这两个响应都防止集成电路设备意外进入测试模式。如果集成电路设备应该处于测试模式，它将保持在测试模式。然而，如果集成电路器件不是处于测试模式，则ETD脉冲迫使集成电路器件脱离测试模式。如果以其他方式满足进入测试模式的条件，则允许进入设备的测试模式。

38. 发明授权

US5946264A Method and structure for enhancing the access time of integrated circuit memory devices 有权
标题翻译：提高集成电路存储器件存取时间的方法和结构
公开(公告)号：US5946264A
公开(公告)日：1999-08-31
申请号：US183231
申请日：1998-10-30
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G11C7/10 , G11C11/419 , G11C7/00
CPC分类号： G11C7/1078 , G11C11/419
摘要： A memory structure features a write driver circuit that is controlled to assist equilibrate devices recover one or more bitlines attached to a memory cell following the completion of a write operation of the memory cell. After the write operation, a write bus true and a write bus complement generated by the write driver are coupled to bitlines and equilibration devices by passgates controlled by a control signal.
摘要翻译：存储器结构具有写入驱动器电路，其被控制以帮助平衡器件在存储器单元的写入操作完成之后恢复连接到存储器单元的一个或多个位线。在写入操作之后，由写入驱动器产生的写总线真和写总线补码通过由控制信号控制的传送通路耦合到位线和平衡器件。

39. 发明授权

US5708789A Structure to utilize a partially functional cache memory by invalidation of faulty cache memory locations 失效
标题翻译：通过使故障高速缓冲存储器位置无效来利用部分功能的高速缓冲存储器的结构
公开(公告)号：US5708789A
公开(公告)日：1998-01-13
申请号：US717139
申请日：1996-09-20
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G06F12/08 , G06F12/16 , G11C29/00
CPC分类号： G11C29/88 , G06F12/0888
摘要： According to the present invention, when faulty data bits in a cache memory are not repairable through conventional repair means such as row/column redundancy, the faulty bits are made inaccessible to the microprocessor by rendering invalid an appropriate line of data in the cache memory containing the faulty data. The present invention employs address detection circuitry which detects when a faulty data address stored in the tag RAM is presented during a microprocessor memory cycle and forces the valid bit for that faulty data to a predetermined logic level. When the valid bit associated with the faulty data is set to the predetermined logic level, the tag RAM generates a signal indicative of a "miss" condition. The "miss condition" is communicated to the microprocessor which must access the requested data from main memory, thus effectively bypassing the faulty data. The address detection circuitry of the invalidation circuitry may be expanded to handle any number of faulty data. In this way, a primary or secondary cache memory having faulty data may be utilized.
摘要翻译：根据本发明，当通过诸如行/列冗余的常规修复装置不能修复高速缓冲存储器中的有缺陷的数据位时，通过在高速缓冲存储器中使适当的数据行无效地使微处理器无法访问故障位，故障数据。本发明采用地址检测电路，其检测在微处理器存储周期期间何时呈现存储在标签RAM中的故障数据地址，并将该错误数据的有效位强制到预定逻辑电平。当与故障数据相关联的有效位设置为预定逻辑电平时，标签RAM产生指示“未命中”状态的信号。 “未命中状态”被传送到微处理器，微处理器必须从主存储器访问所请求的数据，从而有效地绕过故障数据。无效电路的地址检测电路可以被扩展以处理任何数量的故障数据。以这种方式，可以利用具有错误数据的主要或次要高速缓冲存储器。

40. 发明授权

US5701275A Pipelined chip enable control circuitry and methodology 失效
标题翻译：流水线芯片使能控制电路和方法
公开(公告)号：US5701275A
公开(公告)日：1997-12-23
申请号：US588730
申请日：1996-01-19
申请人： David Charles McClure
发明人： David Charles McClure
IPC分类号： G11C11/413 , G11C7/10 , G11C11/409 , G11C11/41 , G11C8/00 , G11C7/00
CPC分类号： G11C7/106 , G11C7/1039 , G11C7/1051
摘要： According to the present invention, the data access time of a chip select condition of a synchronized memory integrated circuit device is pipelined so that it approximates the normal access time of data for the device. The response time to the chip enable signal during a deselect condition is immediate and thus is not pipelined. The access time of data due to a chip select condition is pipelined and matched with the normal access time of data propagation so that any access time pushout previously incurred when transitioning the device output signal from a high impedance (disabled) to a low impedance (enabled) state is eliminated. The circuitry of the present invention tri-states the output pin of the synchronized memory device on the initial rising edge of an external clock signal supplied to the device upon a deselect condition. Upon the first cycle of the select condition, when the external clock signal initially rises, an Output Disable Internal signal remains a high logic state. Next, on the second rising edge of the external clock signal, an Output Enable Internal signal is clocked high and the Output Disable Internal signal is clocked low, thereby overcoming an weak latch on the Output Disable Internal signal to change the output pins of the device from a high impedance to a low impedance state indicative of a select condition.
摘要翻译：根据本发明，同步存储器集成电路器件的芯片选择状态的数据访问时间被流水线化，使其近似于器件的数据的正常访问时间。在取消选择条件下对芯片使能信号的响应时间是立即的，因此不是流水线的。由于芯片选择条件导致的数据访问时间被流水线化，并与数据传播的正常访问时间相匹配，以便将设备输出信号从高阻抗（禁用）转换为低阻抗（已启用）时，先前发生的任何访问时间）状态被消除。本发明的电路在取消选择条件下，在提供给该设备的外部时钟信号的初始上升沿三态化同步的存储器件的输出引脚。在选择条件的第一个周期时，当外部时钟信号最初上升时，输出禁止内部信号保持高逻辑状态。接下来，在外部时钟信号的第二个上升沿，输出使能内部信号为高电平，输出禁止内部信号为低电平，从而克服了输出禁止内部信号的弱锁存器，以改变器件的输出引脚从高阻抗到指示选择条件的低阻抗状态。

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