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31. 发明申请

US20090044086A1 Error correction in a set associative storage device 有权
标题翻译：集合关联存储设备中的纠错
公开(公告)号：US20090044086A1
公开(公告)日：2009-02-12
申请号：US12222085
申请日：2008-08-01
申请人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
发明人： Simon John Craske , Andrew Christopher Rose , Paul Stanley Hughes , Antony John Penton , Richard York , Simon Andrew Ford , Stuart David Biles , Alex James Waugh
IPC分类号： G06F11/30
CPC分类号： G06F11/1064
摘要： A data processing apparatus is provided comprising processing circuitry for performing data processing operations, a set associative storage device for storing data values for access by the processing circuitry when performing data processing operations, error detection circuitry for performing, for each access to the storage device, an error detection operation on the data value accessed, and maintenance circuitry associated with the storage device for performing one or more maintenance operations. The processing circuitry is arranged to issue an error detection maintenance request to the maintenance circuitry specifying at least one specific physical location within the storage device, and the maintenance circuitry is responsive to the error detection maintenance request to perform at least one dummy access to the at least one specific physical location within the storage device and to provide the processing circuitry with error status information derived from the error detection operation performed by the error detection circuitry in respect of said at least one dummy access.
摘要翻译：提供了一种数据处理装置，包括用于执行数据处理操作的处理电路，用于在执行数据处理操作时存储由处理电路进行访问的数据值的组合关联存储装置，用于对存储装置的每次访问执行的错误检测电路，对所访问的数据值的错误检测操作，以及与存储设备相关联的用于执行一个或多个维护操作的维护电路。处理电路被布置为向维护电路发出指示存储设备内的至少一个特定物理位置的错误检测维护请求，并且维护电路响应于错误检测维护请求，以对至少一个虚拟访问在所述存储设备内的至少一个特定的物理位置，并且为所述处理电路提供由所述错误检测电路针对所述至少一个虚拟访问执行的错误检测操作导出的错误状态信息。

32. 发明授权

US07447883B2 Allocation of branch target cache resources in dependence upon program instructions within an instruction queue 失效
标题翻译：根据指令队列中的程序指令分配分支目标缓存资源
公开(公告)号：US07447883B2
公开(公告)日：2008-11-04
申请号：US11501920
申请日：2006-08-10
申请人： Vladimir Vasekin , Stuart David Biles , Andrew Christopher Rose , Wilco Dijkstra
发明人： Vladimir Vasekin , Stuart David Biles , Andrew Christopher Rose , Wilco Dijkstra
IPC分类号： G06F9/32
CPC分类号： G06F12/0875 , G06F9/30058 , G06F9/30181 , G06F9/3806 , G06F12/0862 , G06F2212/6028 , Y02D10/13
摘要： A data processing system includes an instruction fetching circuit 2, an instruction queue 4 and further processing circuits 6. A branch target cache, which maybe a branch target address cache 8, a branch target instruction cache 10 or both, is used to store branch target addresses or blocks of instructions starting at the branch target respectively. A control circuit 12 is responsive to the contents of the instruction queue 4 when a branch instruction is encountered to determine whether or not storage resources within the branch target cache 8, 10 should be allocated to that branch instruction. Storage resources within the branch target cache 8, 10 will be allocated when the number of program instructions within the instruction queue is below a threshold number and/or the estimated execution time of the program instructions is below a threshold time.
摘要翻译：数据处理系统包括指令提取电路2，指令队列4和其他处理电路6。分支目标高速缓存（分支目标地址高速缓存8，分支目标指令高速缓存10或两者）分别用于存储从分支目标开始的分支目标地址或指令块。当遇到分支指令时，控制电路12响应于指令队列4的内容，以确定分支目标高速缓存8,10中的存储资源是否应被分配给该分支指令。当指令队列内的程序指令数量低于阈值数量和/或程序指令的估计执行时间低于阈值时间时，将分配分支目标缓存器8,10内的存储资源。

33. 发明授权

US07406585B2 Data processing system having an external instruction set and an internal instruction set 失效
标题翻译：数据处理系统具有外部指令集和内部指令集
公开(公告)号：US07406585B2
公开(公告)日：2008-07-29
申请号：US10609538
申请日：2003-07-01
申请人： Andrew Christopher Rose , Krisztian Flautner
发明人： Andrew Christopher Rose , Krisztian Flautner
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/3808 , G06F9/3836 , G06F9/3844 , G06F9/3861
摘要： There is provided a system havingan execution core operable to execute internal instructions.A translation buffer is operable to store a plurality of internal instruction blocks of one or more internal instructions where the internal instruction blocks are a dynamic translation of respective external instruction blocks of one or more external instructions.A remapper is responsive to an execution request for an external instruction that is within one of said external instruction blocks to identify a corresponding internal instruction block stored within said translation buffer. Thus one or more internal instructions from said corresponding internal instruction block can be supplied to execution core.
摘要翻译：提供了一种具有可执行内部指令的执行核心的系统。翻译缓冲器可操作以存储一个或多个内部指令的多个内部指令块，其中内部指令块是一个或多个外部指令的相应外部指令块的动态转换。再映射器响应于在所述外部指令块之一内的外部指令的执行请求，以识别存储在所述转换缓冲器内的对应的内部指令块。因此，可以将来自所述对应的内部指令块的一个或多个内部指令提供给执行核心。

34. 发明授权

US07360061B2 Program instruction decompression and compression techniques 有权
标题翻译：程序指令解压缩和压缩技术
公开(公告)号：US07360061B2
公开(公告)日：2008-04-15
申请号：US11004227
申请日：2004-12-06
申请人： Vladimir Vasekin , Andrew Christopher Rose
发明人： Vladimir Vasekin , Andrew Christopher Rose
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30178 , G06F9/3853 , G06F9/3885
摘要： A data processing system including an instruction cache 8 and an instruction decompression circuit 10 between the instruction cache 8 and a compressed instruction data memory 12. The instruction decompression circuit decompresses compressed instruction data CID recovered from the compressed instruction data memory and forms program instructions which are supplied to the instruction cache. The program instructions are compressed in blocks of program instructions with an associated mask value where the bit values within the mask indicate whether corresponding bit slices within the blocks of program instructions are to be represented by a default bit value or a separately specified by bit slice specifier values. This technique is particularly well suited to VLIW processors.
摘要翻译：数据处理系统，包括在指令高速缓存8和压缩指令数据存储器12之间的指令高速缓存8和指令解压缩电路10。指令解压缩电路解压缩从压缩指令数据存储器恢复的压缩指令数据CID，并形成提供给指令高速缓存的程序指令。程序指令以具有关联掩码值的程序指令块压缩，其中掩码内的位值指示程序指令块内的相应位片是否由缺省位值表示，或由位片指定符单独指定价值观。这种技术特别适用于VLIW处理器。

35. 发明授权

US07219215B2 Data processing apparatus and method for moving data elements between specified registers and a continuous block of memory 有权
标题翻译：用于在指定的寄存器和连续的存储器块之间移动数据元素的数据处理装置和方法
公开(公告)号：US07219215B2
公开(公告)日：2007-05-15
申请号：US10889367
申请日：2004-07-13
申请人： Simon Andrew Ford , Dominic Hugo Symes , Andrew Christopher Rose , David Raymond Lutz , Christopher Neal Hinds
发明人： Simon Andrew Ford , Dominic Hugo Symes , Andrew Christopher Rose , David Raymond Lutz , Christopher Neal Hinds
IPC分类号： G06F9/40
CPC分类号： G06F9/30167 , G06F9/30025 , G06F9/30036 , G06F9/3004 , G06F9/30145
摘要： A data processing apparatus and method are provided for moving data between registers and memory. The data processing apparatus comprises a register data store having a plurality of registers operable to store data elements. A processor is operable to perform in parallel a data processing operation on multiple data elements accessed in at least one of the registers. Access logic is operable in response to a single access instruction to move a plurality of data elements between specified registers and a continuous block of memory in which data elements are stored as an array of structures having a structure format, the structure format having a plurality of components. The single access instruction identifies the number of components in the structure format, and the access logic is further operable to rearrange the plurality of data elements as they are moved such that each specified register stores data elements of one component whilst in memory the data elements are stored as the array of structures.
摘要翻译：提供了一种用于在寄存器和存储器之间移动数据的数据处理装置和方法。数据处理装置包括具有可操作以存储数据元素的多个寄存器的寄存器数据存储器。处理器可操作以对在至少一个寄存器中访问的多个数据元素并行地执行数据处理操作。访问逻辑可操作以响应于单个访问指令来移动指定寄存器之间的多个数据元素和其中数据元素被存储为具有结构格式的结构的阵列的连续存储块，所述结构格式具有多个组件。单个访问指令标识结构格式的组件的数量，并且访问逻辑还可用于在移动多个数据元素时重新排列多个数据元素，使得每个指定的寄存器存储一个组件的数据元素，而在存储器中数据元素是存储为结构数组。

36. 发明授权

US07131118B2 Write-through caching a JAVA® local variable within a register of a register bank 有权
标题翻译：直写缓存在注册库的寄存器中的JAVA（R）局部变量
公开(公告)号：US07131118B2
公开(公告)日：2006-10-31
申请号：US10201956
申请日：2002-07-25
申请人： Andrew Christopher Rose
发明人： Andrew Christopher Rose
IPC分类号： G06F9/44 , G06F9/30 , G06F21/00 , G06F12/00
CPC分类号： G06F8/4441
摘要： In a data processing apparatus 2 having a first mode of operation in which JAVA® bytecodes 46, 48 specify the processing operations and a second mode of operation in which other instructions specify the processing operations. In order to speed operation, the JAVA® Local Variable 0, or another such variable, is stored within a register of a register bank 14 to be available for rapid access. This storage is in a write-through manner such that reads of the value will be directly serviced from the register R4 and writes to the data value will be made in both the register R4 and back in the original memory location for that data value as determined by the JAVA® Virtual Machine.
摘要翻译：在具有JAVA（R）字节码46,48指定处理操作的第一操作模式的数据处理设备2和其他指令指定处理操作的第二操作模式。为了加速操作，JAVA（局部变量0）或另一个这样的变量被存储在寄存器组14的寄存器内以便可用于快速访问。该存储器是以直写方式进行的，使得该值的读取将从寄存器R 4直接服务，并且写入数据值将在寄存器R 4中和在该数据值的原始存储器位置中进行由JAVA虚拟机确定。

37. 发明授权

US07089539B2 Program instruction interpretation 有权
标题翻译：程序说明解释
公开(公告)号：US07089539B2
公开(公告)日：2006-08-08
申请号：US10081215
申请日：2002-02-25
申请人： Christopher Bentley Dornan , Andrew Christopher Rose
发明人： Christopher Bentley Dornan , Andrew Christopher Rose
IPC分类号： G06F9/45 , G06F9/30
CPC分类号： G06F9/45504
摘要： Program instructions in the form of Java bytecodes may be subject to fixed mappings to processing operations or programmable mappings to processing operations. A system is provided with a fixed mapping hardware interpreter, a programmable mapping hardware interpreter and a software interpreter. The fixed mapping hardware interpreter is able to provide high speed interpretation of the common and simple bytecodes. The programmable mapping hardware interpreter is able to provide high speed interpretation of the simple and performance critical programmable bytecodes with the remaining bytecodes and more complicated bytecodes being handled by the software interpreter.
摘要翻译：以Java字节码形式的程序指令可能会对处理操作或可编程映射进行固定映射以进行处理操作。系统提供有固定映射硬件解释器，可编程映射硬件解释器和软件解释器。固定映射硬件解释器能够提供常用和简单字节码的高速解释。可编程映射硬件解释器能够提供简单和性能关键的可编程字节码的高速解释，其余的字节码和更复杂的字节码由软件解释器处理。

38. 发明授权

US06172530B2 Decoder for generating N output signals from two or more precharged input signals 失效
标题翻译：用于从两个或多个预充电输入信号产生N个输出信号的解码器
公开(公告)号：US06172530B2
公开(公告)日：2001-01-09
申请号：US09335696
申请日：1999-06-18
申请人： David Michael Bull , Andrew Christopher Rose
发明人： David Michael Bull , Andrew Christopher Rose
IPC分类号： G11C800
CPC分类号： G11C8/00
摘要： A decoder is provided for generating N output signals, the decoder comprising a precharged gate structure arranged to receive two or more input signals and to generate N intermediate signals. In a precharge phase, the precharged gate structure is arranged to output the N intermediate signals at a first logic value, and in an evaluate phase the precharged gate structure is arranged to maintain a first intermediate signal at the first logic value, and to cause all other intermediate signals to transition to a second logic value. Further, self-timed logic is provided for receiving the N intermediate signals, and for generating the N output signals, the self-timed logic being arranged, during the precharge phase, to generate the N output signals at the second logic value, and during the evaluate phase to cause a first output signal corresponding to the first intermediate signal to transition to the first logic value. The self-timed logic is further arranged to generate each output signal from the corresponding intermediate signal as qualified to predetermined other intermediate signal, such that the transition of the first output signal to the first logic value is delayed by a first predetermined time after the predetermined other intermediate signal has transitioned to the second logic value.
摘要翻译：提供了用于产生N个输出信号的解码器，该解码器包括预充电栅极结构，其被布置为接收两个或更多个输入信号并产生N个中间信号。在预充电阶段，预充电栅极结构被布置为以第一逻辑值输出N个中间信号，并且在评估阶段中，预充电栅结构被布置成将第一中间信号保持在第一逻辑值，并且使所有其他中间信号转换到第二逻辑值。此外，提供自定时逻辑用于接收N个中间信号，并且为了产生N个输出信号，在预充电阶段期间，自定时逻辑被布置为以第二逻辑值生成N个输出信号，并且在所述评估阶段使得对应于所述第一中间信号的第一输出信号转变到所述第一逻辑值。自定时逻辑还被布置为从对应的中间信号产生符合预定的其他中间信号的每个输出信号，使得第一输出信号到第一逻辑值的转变在预定的第一预定时间后延迟第一预定时间其他中间信号已经转换到第二逻辑值。

39. 发明授权

US08923278B2 Peer-to-peer, internet protocol telephone system with system-wide configuration data 有权
标题翻译：具有全系统配置数据的点对点互联网协议电话系统
公开(公告)号：US08923278B2
公开(公告)日：2014-12-30
申请号：US12987865
申请日：2011-01-10
申请人： Jen T'ai Chitty , Christopher Rose
发明人： Jen T'ai Chitty , Christopher Rose
IPC分类号： H04L12/66
CPC分类号： H04L65/1059 , H04L12/66 , H04L65/1053 , H04M7/0063
摘要： Various embodiments of the invention provide a Peer-to-Peer (P2P, Internet Protocol (IP) telephone system. The telephone system includes a plurality of terminals coupled together via an IP network. The terminals cooperate with one another to provide telephony features without a dedicated central controller such as a PBX and/or a KSU controller. The terminals further cooperate with one another to maintain system-wide configuration data for the telephone system.
摘要翻译：本发明的各种实施例提供了一种对等（P2P，因特网协议（IP））电话系统，电话系统包括通过IP网络耦合在一起的多个终端，终端彼此协作以提供电话功能，而没有专用中央控制器如PBX和/或KSU控制器，终端进一步互相配合，以维护电话系统的系统范围配置数据。

40. 发明授权

US08347067B2 Instruction pre-decoding of multiple instruction sets 有权
公开(公告)号：US08347067B2
公开(公告)日：2013-01-01
申请号：US12010312
申请日：2008-01-23
申请人： Peter Richard Greenhalgh , Andrew Christopher Rose , Simon John Craske
发明人： Peter Richard Greenhalgh , Andrew Christopher Rose , Simon John Craske
IPC分类号： G06F9/30
CPC分类号： G06F9/30174 , G06F9/30145 , G06F9/30167 , G06F9/3802 , G06F9/3814 , G06F9/382 , G06F9/3853 , G06F9/3865
摘要： A data processing apparatus is provided with pre-decoding circuitry 10 serving to generate pre-decoded instructions which are stored within an instruction cache 20. The pre-decoded instructions from the instruction cache 20 are read by decoding circuitry 45, 50, 46 and used to form control signals for controlling processing operations corresponding to the pre-decoded instructions. The program instructions originally fetched can belong to respective ones of a plurality of instruction sets. Instructions from one instruction set are pre-decoded by the pre-decoding circuitry 10 into pre-decoded instructions having a shared format to represent shared functionality with corresponding instructions taken from another of the instruction sets. In this way, a shared portion of the decoding circuitry can generate control signals with respect to the shared functionality of instructions from both of these different instruction sets.

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