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31. 发明授权

US07602633B2 Non-volatile memory device, method of manufacturing the same, and method of operating the same 有权
标题翻译：非易失性存储器件，其制造方法及其操作方法
公开(公告)号：US07602633B2
公开(公告)日：2009-10-13
申请号：US11946737
申请日：2007-11-28
申请人： Byung-Yong Choi , Choong-Ho Lee , Kyu-Charn Park
发明人： Byung-Yong Choi , Choong-Ho Lee , Kyu-Charn Park
IPC分类号： G11C11/00
CPC分类号： H01L29/685
摘要： A non-volatile memory device includes a substrate, resistance patterns, a gate dielectric layer, a gate electrode pattern, a first impurity region and a second impurity region. The substrate has recesses. The recesses are filled with the resistance patterns. The resistance patterns include a material having a resistance that is variable in accordance with a voltage applied thereto. The gate dielectric layer is formed on the substrate. The gate electrode pattern is formed on the gate dielectric layer. The first and second impurity regions are formed in the substrate. The first impurity region and the second impurity region contact side surfaces of the resistance patterns. Further, the resistance patterns, the first impurity region and the second impurity region define a channel region. Thus, the non-volatile memory device may store data using a variable resistance of the resistance patterns so that the non-volatile memory device may have excellent operational characteristics.
摘要翻译：非易失性存储器件包括衬底，电阻图案，栅极介电层，栅极电极图案，第一杂质区域和第二杂质区域。基板有凹槽。凹槽中填充有电阻图案。电阻图案包括具有根据施加到其上的电压而可变的电阻的材料。栅极电介质层形成在基板上。栅极电极图案形成在栅极介电层上。在衬底中形成第一和第二杂质区。电阻图案的第一杂质区和第二杂质区接触侧表面。此外，电阻图案，第一杂质区域和第二杂质区域限定沟道区域。因此，非易失性存储器件可以使用电阻图案的可变电阻来存储数据，使得非易失性存储器件可以具有优异的操作特性。

32. 发明申请

US20090237324A1 Dual display module and display apparatus having the same 失效
标题翻译：双显示模块和具有该显示模块的显示装置
公开(公告)号：US20090237324A1
公开(公告)日：2009-09-24
申请号：US12382556
申请日：2009-03-18
申请人： Yoon-Chan Oh , Chan-Kyoung Moon , Kyoung-Soo Lee , Min-Hyeng Lee , Seon-Hee Kim , Gun-Mo Kim , Choong-Ho Lee , Byung-Hee Kim , Kuen-Dong Ha
发明人： Yoon-Chan Oh , Chan-Kyoung Moon , Kyoung-Soo Lee , Min-Hyeng Lee , Seon-Hee Kim , Gun-Mo Kim , Choong-Ho Lee , Byung-Hee Kim , Kuen-Dong Ha
IPC分类号： G09G5/00 , G09G3/30
CPC分类号： G06F1/1601 , G02F2001/133317 , G02F2001/133342 , G06F1/1616 , G06F1/1637 , G06F1/1647 , G09G2300/023 , H01L25/048 , H01L27/3267 , H01L27/3281 , H01L2924/0002 , H01L2924/00
摘要： A dual display module having a first display panel and a second display panel, the dual display module including a bezel arranged between the first display panel and the second display panel, and having a penetration area between the first display panel and the second display panel; and a supporting member arranged between the bezel and the second display panel and supporting the second display panel, the supporting member having at least one protrusion unit that protrudes through the penetration area to face the first display panel.
摘要翻译：一种具有第一显示面板和第二显示面板的双显示模块，所述双显示模块包括布置在所述第一显示面板和所述第二显示面板之间的边框，并且在所述第一显示面板和所述第二显示面板之间具有穿透区域; 以及布置在所述边框和所述第二显示面板之间并支撑所述第二显示面板的支撑构件，所述支撑构件具有突出穿过所述穿透区域以面对所述第一显示面板的至少一个突出单元。

33. 发明授权

US07586149B2 Circuit device including vertical transistors connected to buried bitlines and method of manufacturing the same 有权
标题翻译：电路装置包括连接到埋地位线的垂直晶体管及其制造方法
公开(公告)号：US07586149B2
公开(公告)日：2009-09-08
申请号：US11541756
申请日：2006-10-02
申请人： Jae-man Yoon , Dong-gun Park , Kang-yoon Lee , Choong-ho Lee , Bong-soo Kim , Seong-goo Kim , Hyeoung-won Seo , Seung-bae Park
发明人： Jae-man Yoon , Dong-gun Park , Kang-yoon Lee , Choong-ho Lee , Bong-soo Kim , Seong-goo Kim , Hyeoung-won Seo , Seung-bae Park
IPC分类号： H01L23/528 , H01L27/108
CPC分类号： H01L29/66666 , H01L21/823885 , H01L27/10876 , H01L27/10885 , H01L27/10894 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device. The circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region, bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction, channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another, gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars, and buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region.
摘要翻译：一种包括连接到掩埋位线的垂直晶体管的电路器件和制造该电路器件的方法。该电路装置包括半导体衬底，该半导体衬底包括外围电路区域和在外围电路区域的两侧的左侧和右侧电池区域，布置在半导体衬底上的底部有源区域在列方向上彼此间隔开并从所述外围电路区域与所述左侧单元区域和右侧单元区域交替地排列成行方向，所述通道柱从所述底部有源区域沿垂直方向突出并且被配置为在所述行方向上彼此对准并且彼此间隔开，栅电极设置有栅介电层并且被附接到环绕通道柱的侧表面，以及沿底部有源区延伸的掩埋位线，底部有源区包括底部源极/漏极区。

34. 发明申请

US20090189217A1 Semiconductor Memory Devices Including a Vertical Channel Transistor 有权
标题翻译：包括垂直通道晶体管的半导体存储器件
公开(公告)号：US20090189217A1
公开(公告)日：2009-07-30
申请号：US12418879
申请日：2009-04-06
申请人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
发明人： Jae-man Yoon , Dong-gun Park , Choong-ho Lee , Moon-suk Yi , Chul Lee
IPC分类号： H01L29/78
CPC分类号： H01L27/10885 , H01L27/0207 , H01L27/10814 , H01L27/10876 , H01L29/66666
摘要： Semiconductor memory devices include a semiconductor substrate and a plurality of semiconductor material pillars in a spaced relationship on the semiconductor substrate. Respective surrounding gate electrodes surround ones of the pillars. A first source/drain region is in the semiconductor substrate between adjacent ones of the pillars and a second source/drain region is in an upper portion of at least one of the adjacent pillars. A buried bit line is in the first source/drain region and electrically coupled to the first source/drain region and a storage node electrode is on the upper portion of the at least one of the adjacent pillars and electrically contacting with the second source/drain region.
摘要翻译：半导体存储器件包括在半导体衬底上具有间隔关系的半导体衬底和多个半导体材料柱。相邻的围绕电极围绕其中的一个柱。第一源极/漏极区域在相邻的柱之间的半导体衬底中，并且第二源极/漏极区域位于至少一个相邻支柱的上部。掩埋位线在第一源极/漏极区域中并且电耦合到第一源极/漏极区域，并且存储节点电极在相邻柱的至少一个的上部上并且与第二源极/漏极地区。

35. 发明授权

US07528022B2 Method of forming fin field effect transistor using damascene process 有权
标题翻译：使用镶嵌工艺形成翅片场效应晶体管的方法
公开(公告)号：US07528022B2
公开(公告)日：2009-05-05
申请号：US11112818
申请日：2005-04-21
申请人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
发明人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7851 , H01L21/26586 , H01L29/66818
摘要： A method of forming a fin transistor using a damascene process is provided. A filling mold insulation pattern is recessed to expose an upper portion of a fin, and a mold layer is formed. The mold layer is patterned to form a groove crossing the fin and exposing a part of the upper portion of the fin. A gate electrode is formed to fill the groove with a gate insulation layer interposed between the fin and the gate electrode, and the mold layer is removed. Impurities are implanted through both sidewalls and a top surface of the upper portion of the fin disposed at opposite sides of a gate electrode to form a source/drain region.
摘要翻译：提供了一种使用镶嵌工艺形成鳍式晶体管的方法。填充模具绝缘图案凹入以暴露翅片的上部，并且形成模具层。图案化模具层以形成与散热片交叉的凹槽并暴露翅片上部的一部分。形成栅电极，用插入翅片和栅电极之间的栅极绝缘层填充凹槽，并且去除模层。通过设置在栅极电极的相对侧的翅片的上侧部分的两个侧壁和顶部表面注入杂质以形成源极/漏极区域。

36. 发明授权

US07465985B2 Non-volatile memory device and methods of forming the same 有权
标题翻译：非易失性存储器件及其形成方法
公开(公告)号：US07465985B2
公开(公告)日：2008-12-16
申请号：US11580086
申请日：2006-10-13
申请人： Byung-Yong Choi , Choong-Ho Lee , Dong-Gun Park
发明人： Byung-Yong Choi , Choong-Ho Lee , Dong-Gun Park
IPC分类号： H01L21/334
CPC分类号： H01L27/115 , H01L27/11519 , H01L27/11526 , H01L27/11529
摘要： A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.
摘要翻译：提供了一种非易失性存储器件及其形成方法。非易失性存储器件可以包括依次层叠在半导体衬底的预定或给定区域上的单元隔离图案和半导体图案，半导体图案上的单元栅极线和半导体衬底的一侧的顶表面上的半导体图案电池隔离图案，单元栅极线和半导体衬底之间的多层陷阱绝缘层，以及单元栅极线和半导体图案，在单元栅极线的两侧的半导体衬底中的第一杂质扩散层和位于单元栅极线两侧的半导体图案中的第二杂质扩散层。

37. 发明授权

US07384850B2 Methods of forming complementary metal oxide semiconductor (CMOS) transistors having three-dimensional channel regions therein 有权
标题翻译：形成其中具有三维沟道区的互补金属氧化物半导体（CMOS）晶体管的方法
公开(公告)号：US07384850B2
公开(公告)日：2008-06-10
申请号：US11087988
申请日：2005-03-23
申请人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
发明人： Young-Joon Ahn , Dong-Gun Park , Choong-Ho Lee , Hee-Soo Kang
IPC分类号： H01L21/8234
CPC分类号： H01L29/78696 , H01L21/823807 , H01L21/823828 , H01L21/84 , H01L27/1203 , H01L29/66787 , H01L29/78645
摘要： An integrated circuit device containing complementary metal oxide semiconductor transistors includes a semiconductor substrate and an NMOS transistor having a first fin-shaped active region that extends in the semiconductor substrate. The first fin-shaped active region has a first channel region therein with a first height. A PMOS transistor is also provided. The PMOS transistor has a second fin-shaped active region that extends in the semiconductor substrate. This second fin-shaped active region has a second channel region therein with a second height unequal to the first height.
摘要翻译：包含互补金属氧化物半导体晶体管的集成电路器件包括半导体衬底和具有在半导体衬底中延伸的第一鳍状有源区的NMOS晶体管。第一鳍形有源区域在其中具有第一高度的第一通道区域。还提供PMOS晶体管。 PMOS晶体管具有在半导体衬底中延伸的第二鳍状有源区。该第二鳍形有源区域具有其中具有不等于第一高度的第二高度的第二沟道区域。

38. 发明申请

US20080130349A1 NON-VOLATILE MEMORY DEVICE, METHOD OF MANUFACTURING THE SAME, AND METHOD OF OPERATING THE SAME 有权
标题翻译：非易失性存储器件，其制造方法及其操作方法
公开(公告)号：US20080130349A1
公开(公告)日：2008-06-05
申请号：US11946737
申请日：2007-11-28
申请人： Byung Yong CHOI , Choong-Ho LEE , Kyu-Charn PARK
发明人： Byung Yong CHOI , Choong-Ho LEE , Kyu-Charn PARK
IPC分类号： G11C11/00 , H01L45/00
CPC分类号： H01L29/685
摘要： A non-volatile memory device includes a substrate, resistance patterns, a gate dielectric layer, a gate electrode pattern, a first impurity region and a second impurity region. The substrate has recesses. The recesses are filled with the resistance patterns. The resistance patterns include a material having a resistance that is variable in accordance with a voltage applied thereto. The gate dielectric layer is formed on the substrate. The gate electrode pattern is formed on the gate dielectric layer. The first and second impurity regions are formed in the substrate. The first impurity region and the second impurity region contact side surfaces of the resistance patterns. Further, the resistance patterns, the first impurity region and the second impurity region define a channel region. Thus, the non-volatile memory device may store data using a variable resistance of the resistance patterns so that the non-volatile memory device may have excellent operational characteristics.
摘要翻译：非易失性存储器件包括衬底，电阻图案，栅极介电层，栅极电极图案，第一杂质区域和第二杂质区域。基板有凹槽。凹槽中填充有电阻图案。电阻图案包括具有根据施加到其上的电压而可变的电阻的材料。栅极电介质层形成在基板上。栅极电极图案形成在栅极介电层上。在衬底中形成第一和第二杂质区。电阻图案的第一杂质区和第二杂质区接触侧表面。此外，电阻图案，第一杂质区域和第二杂质区域限定沟道区域。因此，非易失性存储器件可以使用电阻图案的可变电阻来存储数据，使得非易失性存储器件可以具有优异的操作特性。

39. 发明申请

US20070190725A1 Methods of Manufacturing Semiconductor devices Having Buried Bit Lines 审中-公开
标题翻译：制造埋置位线的半导体器件的方法
公开(公告)号：US20070190725A1
公开(公告)日：2007-08-16
申请号：US11740525
申请日：2007-04-26
申请人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
发明人： Tae-yong Kim , Choong-ho Lee , Chul Lee , Eun-suk Cho , Suk-kang Sung , Hye-jin Cho
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11568
摘要： A semiconductor device includes a semiconductor substrate having a first conductivity type and having an upper portion, a pair of bit lines extending in a first direction and doped with an impurity of a second conductivity type opposite to the first conductivity type and spaced from one another in the upper portion of the semiconductor substrate, a first line formed between the pair of bit lines having a plurality of alternating recessed device isolation regions and channel regions, with each of the channel regions contacting each bit line of the at least one pair of bit lines, and word lines formed at right angles to the first lines and covering the channel regions.
摘要翻译：半导体器件包括具有第一导电类型并具有上部的半导体衬底，一对位线沿着第一方向延伸并且掺杂有与第一导电类型相反并且彼此间隔开的第二导电类型的杂质所述半导体衬底的上部，形成在所述一对位线之间的第一线，所述第一线具有多个交替的凹陷器件隔离区域和沟道区域，其中每个沟道区域与所述至少一对位线的每个位线接触以及与第一线成直角形成并覆盖沟道区的字线。

40. 发明申请

US20070114612A1 Method of fabricating semiconductor devices having MCFET/finFET and related device 审中-公开
标题翻译：制造具有MCFET / finFET及相关器件的半导体器件的方法
公开(公告)号：US20070114612A1
公开(公告)日：2007-05-24
申请号：US11443816
申请日：2006-05-31
申请人： Young-Joon Ahn , Choong-Ho Lee , Hee-Soo Kang
发明人： Young-Joon Ahn , Choong-Ho Lee , Hee-Soo Kang
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/1104 , H01L27/11 , H01L29/7851
摘要： In a method of fabricating a semiconductor device having both a MCFET and a finFET on a common substrate, a first hard mask pattern and a second hard mask pattern are formed on a substrate, the second hard mask pattern having a width in a horizontal direction that is less than that of the first hard mask pattern, and the second hard mask pattern being spaced apart from the first hard mask pattern. The substrate is partially removed using the first and second hard mask patterns as etch masks, and forming a preliminary multi-fin structure below the first hard mask pattern and a single fin structure below the second hard mask pattern. A concave portion is formed in the preliminary multi-fin structure to form a multi-fin structure.
摘要翻译：在制造在共用衬底上具有MCFET和finFET的半导体器件的方法中，在衬底上形成第一硬掩模图案和第二硬掩模图案，第二硬掩模图案在水平方向上具有宽度，即小于第一硬掩模图案的厚度，并且第二硬掩模图案与第一硬掩模图案间隔开。使用第一和第二硬掩模图案作为蚀刻掩模部分地去除衬底，以及在第一硬掩模图案下方形成初步的多鳍结构，以及在第二硬掩模图案下面形成单个鳍结构。在预备的多翅片结构中形成凹部以形成多翅片结构。

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