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31. 发明授权

US06239017B1 Dual damascene CMP process with BPSG reflowed contact hole 有权
标题翻译：双镶嵌CMP工艺与BPSG回流接触孔
公开(公告)号：US06239017B1
公开(公告)日：2001-05-29
申请号：US09156357
申请日：1998-09-18
申请人： Chine-Gie Lou , Hsueh-Chung Chen
发明人： Chine-Gie Lou , Hsueh-Chung Chen
IPC分类号： H01L214763
CPC分类号： H01L21/76828 , H01L21/31612 , H01L21/31625 , H01L21/76804 , H01L21/76807 , H01L2221/1036
摘要： An improved and new process for fabricating a planarized dual damascene contact hole and trench structure, wherein the contact holes have tapered sidewalls, has been developed. The dual damascene contact hole and trench are formed in a three layer insulator structure, in which the middle layer is a doped silicon oxide having a lower reflow temperature than the undoped silicon oxide layers forming the top and bottom layers. The contact holes are etched through the doped silicon oxide layer and the bottom undoped silicon oxide layer. The trenches are etched through the top undoped silicon oxide layer. After etching tapered sidewalls are formed at the contact holes by reflow of the doped silicon oxide through which the holes are etched.
摘要翻译：已经开发了一种用于制造平面化双镶嵌接触孔和沟槽结构的改进和新工艺，其中接触孔具有锥形侧壁。双镶嵌接触孔和沟槽形成为三层绝缘体结构，其中中间层是具有比形成顶层和底层的未掺杂氧化硅层低的回流温度的掺杂氧化硅。通过掺杂氧化硅层和底部未掺杂的氧化硅层蚀刻接触孔。通过顶部未掺杂的氧化硅层蚀刻沟槽。蚀刻之后，通过掺杂氧化硅的回流在接触孔处形成锥形侧壁，通过该掺杂氧化硅蚀刻孔。

32. 发明授权

US06218285B1 Method for forming inter-metal dielectric layers in metallization process 有权
标题翻译：在金属化工艺中形成金属间介电层的方法
公开(公告)号：US06218285B1
公开(公告)日：2001-04-17
申请号：US09387506
申请日：1999-09-01
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L214763
CPC分类号： H01L21/31053 , H01L21/76819
摘要： The method for forming inter-metal dielectric layers in a metallization process mainly includes the following steps. At first, a semiconductor substrate having interconnection structures formed thereon is provided. A liner layer is formed to cover the interconnection structures and the substrate, and a first dielectric layer is formed on the liner layer. A planarization stop layer is formed on the first dielectric layer and a second dielectric layer is formed on the planarization stop layer, wherein the second dielectric layer has a higher removal rate than the planarization stop layer in a planarization process. Finally, the substrate is planarized by removing portions of the second dielectric layer until portions of the planarization stop layer is presented.
摘要翻译：在金属化处理中形成金属间介电层的方法主要包括以下步骤。首先，提供其上形成有互连结构的半导体衬底。形成衬里层以覆盖互连结构和衬底，并且在衬垫层上形成第一介电层。在第一电介质层上形成平坦化阻挡层，在平坦化终止层上形成第二电介质层，其中在平坦化工艺中第二电介质层具有比平坦化终止层更高的去除率。最后，通过去除第二电介质层的部分直到呈现平坦化停止层的部分来平坦化基板。

33. 发明授权

US06184159B2 Interlayer dielectric planarization process 失效
标题翻译：层间电介质平面化处理
公开(公告)号：US06184159B2
公开(公告)日：2001-02-06
申请号：US09096901
申请日：1998-06-12
申请人： Chine-Gie Lou , Horng-Ming Lee
发明人： Chine-Gie Lou , Horng-Ming Lee
IPC分类号： H01L214763
CPC分类号： H01L21/02129 , H01L21/02271 , H01L21/02304 , H01L21/02362 , H01L21/31053 , H01L21/31612 , H01L21/31625 , H01L21/3185 , H01L21/76819
摘要： A method of forming a planar interlayer dielectric layer over underlying structures is disclosed. First, a liner oxide layer is formed over the underlying structures. Then, a BPSG layer is formed over the liner oxide layer. The BPSG layer is polished and a cap oxide layer is formed over the BPSG layer. Finally, a nitride layer is formed over the cap oxide layer.
摘要翻译：公开了一种在下面的结构上形成平面层间介质层的方法。首先，在下面的结构上形成衬里氧化物层。然后，在衬垫氧化物层上形成BPSG层。抛光BPSG层，并在BPSG层上形成帽氧化物层。最后，在盖氧化物层上形成氮化物层。

34. 发明授权

US06184130B2 Silicide glue layer for W-CVD plug application 失效
公开(公告)号：US06184130B2
公开(公告)日：2001-02-06
申请号：US08965313
申请日：1997-11-06
申请人： Tzu-Kun Ku , Hsueh-Chung Chen , Chine-Gie Lou
发明人： Tzu-Kun Ku , Hsueh-Chung Chen , Chine-Gie Lou
IPC分类号： H01L2144
CPC分类号： H01L21/76876 , H01L21/76843 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： A new method of tungsten plug metallization using a silicide glue layer is described. Semiconductor device structures are provided in and on a semiconductor substrate. An insulating layer is provided covering the semiconductor device structures wherein a contact opening is made through the insulating layer to one of the semiconductor device structures. A silicide layer is deposited conformally over the surface of the insulating layer and within the contact opening as a combined ohmic contact and glue layer. In a first embodiment, a tungsten layer is deposited overlying the silicide layer. The tungsten layer not within the contact opening is removed to complete the formation of the tungsten plug metallization. In a second embodiment, the silicide layer not within the contact opening is selectively removed and a tungsten layer is selectively deposited overlying the silicide layer within the contact opening to complete formation of the tungsten plug metallization in the fabrication of an integrated circuit.

35. 发明授权

US6159793A Structure and fabricating method of stacked capacitor 有权
标题翻译：堆叠电容器的结构和制造方法
公开(公告)号：US6159793A
公开(公告)日：2000-12-12
申请号：US299956
申请日：1999-04-26
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L21/02 , H01L21/316 , H01L21/8242
CPC分类号： H01L28/84 , H01L21/31604 , H01L27/10852 , H01L28/91 , Y10S438/964
摘要： A structure and method of fabricating a stacked capacitor which forms a hemispherical grain (HSG) polysilicon on the surface of a crown shaped amorphous silicon layer. By selective tungsten deposition, the HSG polysilicon and the amorphous silicon layer are displaced with a rough tungsten layer. A material with a high dielectric constant and a metal layer are formed in sequence as a dielectric layer and an upper electrode of the capacitor, so as to form a crown metal-insulator-metal (MIM) capacitor.
摘要翻译：制造在冠状非晶硅层的表面上形成半球状晶粒（HSG）多晶硅的叠层电容器的结构和方法。通过选择性钨沉积，HSG多晶硅和非晶硅层用粗钨层移位。依次形成具有高介电常数和金属层的材料作为电容器的电介质层和上电极，以形成金属 - 绝缘体 - 金属（MIM）电容器。

36. 发明授权

US6107139A Method for making a mushroom shaped DRAM capacitor 失效
标题翻译：制造蘑菇状DRAM电容器的方法
公开(公告)号：US6107139A
公开(公告)日：2000-08-22
申请号：US118170
申请日：1998-07-17
申请人： Yeur-Luen Tu , Chine-Gie Lou
发明人： Yeur-Luen Tu , Chine-Gie Lou
IPC分类号： H01L21/02 , H01L21/8242 , H01L21/44 , H01L27/108
CPC分类号： H01L28/82 , H01L27/10852 , H01L28/87 , H01L28/91
摘要： A method of forming a capacitor for a DRAM memory cell is disclosed. The method comprises the steps of forming a crown shaped capacitor being partially filled with oxide. Next, nitride spacers and polysilicon spacers are formed on the sides of crown capacitor. The remaining oxide is removed and then the oxide spacers are removed to leave a mushroom shaped bottom storage node. A dielectric is deposited and a top conductive node is deposited to complete the capacitor.
摘要翻译：公开了一种形成用于DRAM存储单元的电容器的方法。该方法包括形成部分填充有氧化物的冠状电容器的步骤。接下来，在冠电容器的侧面上形成氮化物间隔物和多晶硅间隔物。除去剩余的氧化物，然后除去氧化物间隔物以留下蘑菇状底部储存节点。沉积电介质并沉积顶部导电节点以完成电容器。

37. 发明授权

US6090664A Method for making a stacked DRAM capacitor 失效
标题翻译：堆叠DRAM电容器的制造方法
公开(公告)号：US6090664A
公开(公告)日：2000-07-18
申请号：US121021
申请日：1998-07-22
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L21/02 , H01L21/314 , H01L21/8242
CPC分类号： H01L28/87 , H01L21/3143 , H01L27/10852 , H01L28/84
摘要： A method of forming a capacitor for a stacked DRAM memory cell. A contact hole is formed in a dielectric stack of an interlayer dielectric, a first nitride layer, a high temperature oxide (HTO) layer, and a second nitride layer. An in-situ doped amorphous silicon segment is formed in and over the contact hole. The second nitride layer is removed and then a hemispherical grain (HSG) polysilicon layer is formed over the amorphous silicon segment. The HTO layer is removed and a capacitor dielectric layer is formed over the HSG polysilicon layer. Finally, a top conductive layer is formed over the capacitor dielectric layer.
摘要翻译：一种形成堆叠DRAM存储单元的电容器的方法。在层间电介质，第一氮化物层，高温氧化物（HTO）层和第二氮化物层的电介质叠层中形成接触孔。在接触孔中和上方形成原位掺杂的非晶硅部分。去除第二氮化物层，然后在非晶硅部分上形成半球形晶粒（HSG）多晶硅层。去除HTO层，并在HSG多晶硅层上形成电容器介质层。最后，在电容器电介质层上形成顶部导电层。

38. 发明授权

US5759906A Planarization method for intermetal dielectrics between multilevel interconnections on integrated circuits 失效
标题翻译：集成电路多层互连之间的金属间电介质的平面化方法
公开(公告)号：US5759906A
公开(公告)日：1998-06-02
申请号：US827813
申请日：1997-04-11
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L21/3105 , H01L21/316 , H01L21/768 , H01L23/522 , H01L21/28
CPC分类号： H01L21/76819 , H01L21/31053
摘要： An improved method for making a planar intermetal dielectric layer (IMD) for multilevel electrical interconnections on ULSI circuits is achieved. The method involves forming metal lines on which is deposited a conformal PECVD oxide. A multilayer of spin-on glass, composed of at least four layers, is deposited and baked at elevated temperatures and long times after each layer to minimize the poisoned via problem on product with minimum feature sizes greater than 0.35 um. A multilayer of a low dielectric constant polymer can also be used to reduce the RC time delay on product having minimum feature sizes less than 0.35 um. After depositing a SiO.sub.2 on the SOG, or depositing a Fluorine-doped Silicon Glass (FSG) on the low k polymer, the layer is partially chemical/mechanically polished to provide the desired more global planar IMD. This eliminates the necessity of polishing back the SOG or polymer, which is difficult to achieve with the current technologies. Via holes are then etched in the IMD, and a FSG insulating layer is deposited and etched back to form sidewall spacers in the via holes to prevent outgassing from the SOG or low k polymer, and the next level of metal interconnections are formed. The method can be repeated to achieve a multilevel of planar metal interconnections for ULSI circuits.
摘要翻译：实现了一种用于在ULSI电路上制作用于多电平电互连的平面金属间介电层（IMD）的改进方法。该方法包括形成在其上沉积保形PECVD氧化物的金属线。由至少四层组成的多层旋涂玻璃在升高的温度下沉积并在每层之后长时间烘烤，以最小化最小特征尺寸大于0.35μm的产品上的中毒通孔问题。还可以使用低介电常数聚合物的多层以减少具有小于0.35μm的最小特征尺寸的产品上的RC时间延迟。在SOG上沉积SiO2或在低k聚合物上沉积氟掺杂硅玻璃（FSG）后，该层被部分化学/机械抛光以提供所需的更全局的平面IMD。这消除了使用当前技术难以实现的SOG或聚合物的抛光的必要性。然后在IMD中蚀刻通孔，并且将FSG绝缘层沉积并回蚀以在通孔中形成侧壁间隔物，以防止SOG或低k聚合物的脱气，并形成下一级的金属互连。可以重复该方法以实现用于ULSI电路的多层平面金属互连。

39. 发明授权

US06468858B1 Method of forming a metal insulator metal capacitor structure 有权
标题翻译：金属绝缘体金属电容器结构的形成方法
公开(公告)号：US06468858B1
公开(公告)日：2002-10-22
申请号：US09814974
申请日：2001-03-23
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/288 , H01L21/3212 , H01L27/10855 , H01L28/55 , H01L28/90
摘要： A process for forming a metal—insulator—metal (MIM), capacitor structure, in which platinum is employed for both the capacitor top plate and storage node structures, while a high dielectric constant layer, such as BaTiO3 is used for the capacitor dielectric layer, has been developed. Prior to formation of the MIM capacitor structure, an underlying, platinum storage node plug structure is formed in a narrow diameter opening, allowing communication between the MIM capacitor structure, and regions of an underlying transfer gate transistor, to be realized. A thin ruthenium shape is used as a seed layer to allow an electroless plating procedure to be employed for attainment of the platinum storage node plug structure.
摘要翻译：用于电容器顶板和存储节点结构中使用铂的金属 - 绝缘体 - 金属（MIM）电容器结构的方法，而诸如BaTiO 3的高介电常数层用于电容器介电层，已经开发。在形成MIM电容器结构之前，在窄的开口处形成一个下层铂存储节点插头结构，从而实现MIM电容器结构与底层传输栅极晶体管的区域之间的通信。使用薄的钌形状作为种子层，以允许采用无电镀方法来获得铂储存节点插塞结构。

40. 发明授权

US06399482B1 Method and structure for a conductive and a dielectric layer 有权
标题翻译：导电和介电层的方法和结构
公开(公告)号：US06399482B1
公开(公告)日：2002-06-04
申请号：US09430749
申请日：1999-10-29
申请人： Chine-Gie Lou
发明人： Chine-Gie Lou
IPC分类号： H01L214763
CPC分类号： H01L21/76801 , H01L21/76834 , H01L21/76885
摘要： A structure and method for conductive layer and inter-metal dielectric layer is disclosed. Firstly, a conductive layer and an anti-reflection coating layer are formed on a substrate. A photolithography and an etching is then carried out to form conductive structure. Dielectric spacers are then formed on the sidewalls of the conductive structure. An organic dielectric layer is coated on the semiconductor substrate and etched back with the anti-reflection coating layer as stopping layer. The anti-reflection coating layer is then removed. An inorganic dielectric layer and a dielectric cap layer are deposited on the conductive structure and the organic dielectric layer. The structure fabricated comprises a conductive layer formed on a substrate; dielectric spacers formed on the sidewalls of the conductive layer; an organic dielectric layer formed to fill the regions among the conductive layer; an inorganic dielectric layer formed on the conductive layer and the organic dielectric layer; a planarized cap layer formed on the inorganic dielectric layer.
摘要翻译：公开了导电层和金属间介电层的结构和方法。首先，在基板上形成导电层和防反射涂层。然后进行光刻和蚀刻以形成导电结构。然后在导电结构的侧壁上形成电介质间隔物。将有机电介质层涂覆在半导体衬底上并用抗反射涂层作为阻挡层进行回蚀。然后除去防反射涂层。无机介电层和电介质盖层沉积在导电结构和有机电介质层上。制造的结构包括形成在基板上的导电层; 形成在导电层的侧壁上的电介质间隔物; 形成为填充导电层中的区域的有机介电层; 形成在所述导电层和所述有机介电层上的无机介电层; 形成在无机介电层上的平坦化的盖层。

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