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31. 发明授权

US09747109B2 Flexible instruction execution in a processor pipeline 有权
公开(公告)号：US09747109B2
公开(公告)日：2017-08-29
申请号：US14514596
申请日：2014-10-15
申请人： Cavium, Inc.
发明人： David Albert Carlson
IPC分类号： G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/3855
摘要： Executing instructions in a processor includes analyzing operations to be performed by instructions, including: determining a latency associated with a first operation to be performed by a first instruction, determining a second operation to be performed by a second instruction, where a result of the second operation depends on a result of the first operation, and assigning a value to the second instruction corresponding to the determined latency associated with the first operation. One or more instructions are selected to be issued together in the same clock cycle of the processor from among instructions whose operations have been analyzed, the selected instructions occurring consecutively according to a program order. A start of execution of the second instruction is delayed by a particular number of clock cycles after the clock cycle in which the second instruction is issued according to the value assigned to the second instruction.

32. 发明授权

US09740807B2 Method to measure edge-rate timing penalty of digital integrated circuits 有权
公开(公告)号：US09740807B2
公开(公告)日：2017-08-22
申请号：US14609164
申请日：2015-01-29
申请人： Cavium, Inc.
发明人： Nitin Mohan , Vasudevan Kandadi
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： Methods for evaluating timing delays in unbalanced digital circuit elements and for correcting timing delays computed by static-timing models are described. Unbalanced circuit elements have large edge-rates at their input and small edge-rates at their output. Unbalanced circuit elements may be analyzed using a modified loaded ring oscillator. A statistical model and a fixed-corner model may be used to calculate timing delays associated with the unbalanced circuit elements and a timing delay error between the two models. The timing delay error may then be used to correct timing delays computed by static-timing models for similar unbalanced circuit elements within a more complex digital circuit.

33. 发明申请

US20170206171A1 Collapsed Address Translation With Multiple Page Sizes 审中-公开
公开(公告)号：US20170206171A1
公开(公告)日：2017-07-20
申请号：US15475718
申请日：2017-03-31
申请人： Cavium, Inc.
发明人： Shubhendu S. Mukherjee , Bryan W. Chin , Wilson P. Snyder, II , Michael Bertone , Richard E. Kessler , Christopher Mikulis
IPC分类号： G06F12/1036 , G06F9/50 , G06F12/1009
CPC分类号： G06F12/1036 , G06F9/5077 , G06F12/1009 , G06F12/1027 , G06F2212/651
摘要： A computer system that supports virtualization may maintain multiple address spaces. Each guest operating system employs guest virtual addresses (GVAs), which are translated to guest physical addresses (GPAs). A hypervisor, which manages one or more guest operating systems, translates GPAs to root physical addresses (RPAs). A merged translation lookaside buffer (MTLB) caches translations between the multiple addressing domains, enabling faster address translation and memory access. The MTLB can be logically addressable as multiple different caches, and can be reconfigured to allot different spaces to each logical cache. Further, a collapsed TLB provides an additional cache storing collapsed translations derived from the MTLB.

34. 发明授权

US09703722B2 Method and system for compressing data for a translation look aside buffer (TLB) 有权
公开(公告)号：US09703722B2
公开(公告)日：2017-07-11
申请号：US14940679
申请日：2015-11-13
申请人： Cavium, Inc.
发明人： Anna Kujtkowski , Wilson P. Snyder, II
IPC分类号： G06F12/10 , G06F12/1027 , H04L12/743 , G06F12/1009
CPC分类号： G06F12/1027 , G06F12/1009 , G06F2212/1016 , G06F2212/401 , G06F2212/68 , H04L45/7457
摘要： An embodiment of the present disclosure includes a method for compressing data for a translation look aside buffer (TLB). The method includes: receiving an identifier at a content addressable memory (CAM), the identifier having a first bit length; compressing the identifier based on a location within the CAM the identifier is stored, the compressed identifier having a second bit length, the second bit length being smaller than the first bit length; and mapping at least the compressed identifier to a physical address in a buffer.

35. 发明授权

US09690590B2 Flexible instruction execution in a processor pipeline 有权
公开(公告)号：US09690590B2
公开(公告)日：2017-06-27
申请号：US14514708
申请日：2014-10-15
申请人： Cavium, Inc.
发明人： David Albert Carlson
IPC分类号： G06F9/30 , G06F9/40 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/3826 , G06F9/3867
摘要： Executing instructions in a processor includes: selecting or more instructions to be issued together in the same clock cycle of the processor from among a plurality of instructions, the selected one or more instructions occurring consecutively according to a program order; and executing instructions that have been issued, through multiple execution stages of a pipeline of the processor. The executing includes: determining a delay assigned to a first instruction, and sending a result of a first operation performed by the first instruction in a first execution stage to a second execution stage, where the number of execution stages between the first execution stage and the second execution stage is based on the determined delay.

36. 发明授权

US09680742B2 Packet output processing 有权
公开(公告)号：US09680742B2
公开(公告)日：2017-06-13
申请号：US14193895
申请日：2014-02-28
申请人： Cavium, Inc.
发明人： Joseph B. Tompkins , Brian Robert Folsom , Wilson P. Snyder, II , Richard E. Kessler , Edwin Langevin , Andrew J. Jones , Ethan F. Robbins , Krupa Sagar O. S. Mylavarapu , Mahesh Dorai , Nagaraj G. Shirali , Ranjith Kumar V. Hallur
IPC分类号： H04L12/28 , H04L12/56 , H04L12/741 , H04L12/721 , H04L12/911 , H04L29/06 , H04L12/863 , H04L12/801 , H04L12/823
CPC分类号： H04L45/74 , H04L45/566 , H04L47/32 , H04L47/34 , H04L47/50 , H04L47/6225 , H04L47/821 , H04L69/22
摘要： A circuit operates to manage transmittal of packets in a network packet processor. The circuit includes a packet descriptor manager (PDM), a packet scheduling engine (PSE), and a packet engines and buffering module (PEB). The PDM generates a metapacket and a descriptor from a command signal, where the command signal identifies a packet to be transmitted by the circuit. The PSE determines an order in which to transmit the packet among a number of packets, where the PSE determines the order based on information indicated in the metapacket. Once the packet is scheduled for transmission, the PEB performs processing operations on the packet to produce a processed packet based on instructions indicated in the descriptor. The PEB then causes the processed packet to be transmitted toward the destination.

37. 发明授权

US09673753B1 Voltage-controlled oscillator with improved tuning curve linearization 有权
公开(公告)号：US09673753B1
公开(公告)日：2017-06-06
申请号：US15000840
申请日：2016-01-19
申请人： Cavium, Inc.
发明人： Omer O. Yildirim , JingDong Deng , Scott E. Meninger
IPC分类号： H03B5/08 , H03B5/12
CPC分类号： H03B5/1212 , H03B5/1243 , H03B5/1246 , H03B5/1265 , H03B5/1293
摘要： In an embodiment, a voltage-controlled oscillator circuit includes a gain element and an LC resonator coupled with the gain element, the LC resonator including an inductor section and a capacitor section. The capacitor section has at least two branches connected in parallel and a voltage control input for tuning the LC resonator. Any of the at least two branches is selected from the group of DC-coupled and AC-coupled. Characteristics of the two branches and bias voltages of the AC-coupled branches are selected to provide a tuning curve of the voltage-controlled oscillator circuit that is approximately linear.

38. 发明申请

US20170097895A1 INPUT OUTPUT VALUE PREDICTION WITH PHYSICAL OR VIRTUAL ADDRESSING FOR VIRTUAL ENVIRONMENT 有权
公开(公告)号：US20170097895A1
公开(公告)日：2017-04-06
申请号：US14874460
申请日：2015-10-04
申请人： Cavium, Inc.
发明人： Wilson Parkhurst Snyder, II , Michael Sean Bertone
IPC分类号： G06F12/10
CPC分类号： G06F12/10 , G06F9/3004 , G06F2212/654
摘要： Method and system embodying the method for input/output value determination at a processor core, comprising generating an I/O instruction comprising at least a physical or a virtual address; comparing the address with a relevant database of I/O devices addresses. When the comparing is successful determining the I/O device or a state on the I/O device to receive the I/O instruction in accordance with the address; setting a value of a first register to a value identifying the determined I/O device or the state on the I/O device; predicting a value to be set in a second register in accordance with the address; and setting a value of a third register. Providing I/O instruction other than a request I/O instruction to the I/O device or the state on the I/O device, which sets a register to a value according to the I/O instruction and reports the value to the processor core.

39. 发明授权

US09614762B2 Work migration in a processor 有权
公开(公告)号：US09614762B2
公开(公告)日：2017-04-04
申请号：US14230698
申请日：2014-03-31
申请人： Cavium, Inc.
发明人： Rajan Goyal , Gregg A. Bouchard
IPC分类号： G06F15/16 , H04L12/741 , G06F13/16 , G06F12/0802 , G06F12/02 , G06F12/04 , G06F12/06 , G06F12/00 , G06F3/06 , G06F11/20 , G06F12/126 , G06N5/02 , H04L12/26 , H04L12/747 , H04L12/851 , H04L12/801 , G06F9/50 , H04L29/08 , G06F9/46 , G11C7/10 , G06F12/0868 , H04L29/06
CPC分类号： H04L63/06 , G06F3/0629 , G06F3/0647 , G06F9/46 , G06F9/5016 , G06F9/5027 , G06F11/203 , G06F12/00 , G06F12/0207 , G06F12/04 , G06F12/06 , G06F12/0623 , G06F12/0802 , G06F12/0868 , G06F12/126 , G06F13/16 , G06F13/1642 , G06N5/02 , G06N5/027 , G11C7/1075 , H04L43/18 , H04L45/742 , H04L45/745 , H04L47/2441 , H04L47/39 , H04L63/0227 , H04L63/0263 , H04L63/10 , H04L67/10 , H04L69/02 , H04L69/22 , Y02B70/30 , Y02B70/32 , Y02D10/14 , Y02D10/22
摘要： A packet processor provides for rule matching of packets in a network architecture. The packet processor includes a lookup cluster complex having a number of lookup engines and respective on-chip memory units. The on-chip memory stores rules for matching against packet data. Each of the lookup engines receives a key request associated with a packet and determines a subset of the rules to match against the packet data. A work product may be migrated between lookup engines to complete the rule matching process. As a result of the rule matching, the lookup engine returns a response message indicating whether a match is found.

40. 发明授权

US09590797B1 Edge rate control calibration 有权
标题翻译：边缘率控制校准
公开(公告)号：US09590797B1
公开(公告)日：2017-03-07
申请号：US15143282
申请日：2016-04-29
申请人： Cavium, Inc.
发明人： Jonathan K. Brown , Ethan Crain
IPC分类号： H03D3/24 , H04L7/00 , H04L7/033
CPC分类号： H04L7/0025 , H03K3/0315 , H03K5/135 , H04L7/0337
摘要： In an example embodiment, a circuit includes an oscillator providing a set of clock phase signals. A main edge rate controller (ERC) coupled to the oscillator is configured to adjust an edge rate of each clock phase signal of the set of clock phase signals. An interpolator coupled to the main ERC is configured to interpolate the adjusted set of clock phase signals to provide at least one desired phase output signal. An edge rate controller calibrator comprises a ring oscillator including at least three ERCs connected in a loop, a counter configured to count a number of cycles of the ring oscillator over a given period, and a finite state machine (FSM) configured to compare the counter count to a given value corresponding to an operating frequency of the circuit and to adjust operation of the circuit based on the comparison.
摘要翻译：在示例实施例中，电路包括提供一组时钟相位信号的振荡器。耦合到振荡器的主边沿速率控制器（ERC）被配置为调整该组时钟相位信号的每个时钟相位信号的边沿速率。耦合到主ERC的内插器被配置为内插经调整的时钟相位信号组，以提供至少一个期望的相位输出信号。边缘速率控制器校准器包括环形振荡器，其包括以循环连接的至少三个ERC，配置成在给定周期内对环形振荡器的周期数进行计数的计数器和被配置为比较计数器的有限状态机（FSM）计数到与电路的工作频率相对应的给定值，并且基于该比较来调整电路的操作。

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