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31. 发明授权

US07877581B2 Networked processor for a pipeline architecture 有权
标题翻译：用于管道架构的网络处理器
公开(公告)号：US07877581B2
公开(公告)日：2011-01-25
申请号：US10726470
申请日：2003-12-02
申请人： Shridhar Mukund , Mahesh Gopalan , Neeraj Kashalkar
发明人： Shridhar Mukund , Mahesh Gopalan , Neeraj Kashalkar
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30025 , G06F9/30007 , G06F9/3001 , G06F9/30032
摘要： A networking application processor is provided. The processor includes an input socket configured to receive data packets. The processor includes a memory for holding instructions and circuitry configured to access data structures associated with the processing stages. The circuitry configured to access data structures enables a single cycle access to an operand from a memory location. An arithmetic logic unit (ALU) is provided. Circuitry for aligning operands to be processed by the ALU is included. The circuitry for aligning the operands causes the operand to be aligned by a lowest significant bit, wherein the circuitry for aligning the operand supplies an extension to the operand to allow the ALU to process different size operands.
摘要翻译：提供了网络应用处理器。处理器包括被配置为接收数据分组的输入套接字。处理器包括用于保存指令的存储器和被配置为访问与处理级相关联的数据结构的电路。被配置为访问数据结构的电路使得能够从存储器单元访问单个操作数。提供了算术逻辑单元（ALU）。包括用于对准由ALU处理的操作数的电路。用于对准操作数的电路使操作数与最低有效位对齐，其中对准操作数的电路向操作数提供扩展以允许ALU处理不同大小的操作数。

32. 发明授权

US07859730B2 Printer with scanner function, and its control method and control program product 有权
标题翻译：带扫描仪功能的打印机及其控制方法和控制程序产品
公开(公告)号：US07859730B2
公开(公告)日：2010-12-28
申请号：US10830784
申请日：2004-04-22
申请人： Kazumi Yamada
发明人： Kazumi Yamada
IPC分类号： G03F3/08
CPC分类号： H04N1/00538 , H04N1/58 , H04N1/6019
摘要： When text is taken in with a scanner, the reflection of the light from a sheet of paper, etc. causes a tinge on the sheet of paper. The tinge around each letter is printed as minute dots, and the outlines of printed letters are blurred and the clearness or distinctness of the letters are decreased.When printing text taken in through a scanner unit 30, by reducing (or reducing to zero) the ratios of occurrence of small dots in a gradient range “n” or “m” of the data for printing (CMYK signals) generated from image data (RGB signals), or converting such ratios of occurrence of small dots into the ratios of occurrence of large dots based on the weight ratio, the blur of each letter that may be caused by the small dots can be reduced, and the clearness and distinctness of each letter can be improved.
摘要翻译：当用扫描仪拍摄文本时，来自一张纸等的光的反射在纸张上产生色调。每个字母周围的色调打印为微小点，打印字母的轮廓模糊，字母的清晰度或明显性降低。当通过扫描器单元30拍摄的文本通过在图像数据生成的打印数据（CMYK信号）的梯度范围“n”或“m”中减小（或减少到零）小点的出现比率（RGB信号），或者根据重量比将小点的出现比例转换成大点的出现比例，可以减少由小点引起的每个字母的模糊，并且清晰度和清晰度的每个字母可以改进。

33. 发明授权

US07855577B1 Using a single buffer for multiple I/O standards 有权
标题翻译：使用单个缓冲区用于多个I / O标准
公开(公告)号：US07855577B1
公开(公告)日：2010-12-21
申请号：US12269149
申请日：2008-11-12
申请人： Chai Yee Teng , Ket Chiew Sia
发明人： Chai Yee Teng , Ket Chiew Sia
IPC分类号： H03K19/094 , H03K19/0175
CPC分类号： H03K19/018514 , H03K19/017509 , H03K19/017581 , H03K19/018585
摘要： A buffer circuit for using one buffer for multiple differential I/O standards is disclosed. The buffer circuit includes a differential input buffer. The first input of the differential input buffer may receive an input and the second input is coupled to a switch. The switch may be a one-time-programmable switch. The switch has a coupling to transmit a signal to the second input of the differential input buffer. The switch may be programmed to selectively transmit different signals to the differential input buffer. The first input terminal of the switch may receive an inverted version of the input signal and the second input terminal of the switch may receive a reference voltage. The buffer may transmit an LVDS signal or an SSTL signal or an HSTL signal. Using one differential buffer for multiple I/O standards may reduce the overall die size and may save space on the die.
摘要翻译：公开了一种用于使用一个缓冲器用于多个差分I / O标准的缓冲电路。缓冲电路包括差分输入缓冲器。差分输入缓冲器的第一输入可以接收输入，第二输入耦合到开关。开关可以是一次性可编程开关。开关具有将信号传输到差分输入缓冲器的第二输入的耦合。该开关可被编程为选择性地向差分输入缓冲器发送不同的信号。开关的第一输入端子可以接收输入信号的反相形式，并且开关的第二输入端子可以接收参考电压。缓冲器可以发送LVDS信号或SSTL信号或HSTL信号。对于多个I / O标准使用一个差分缓冲器可能会降低整体管芯尺寸，并且可以节省管芯上的空间。

34. 发明授权

US07849430B2 Reverse donut model 有权
标题翻译：反向甜甜圈型号
公开(公告)号：US07849430B2
公开(公告)日：2010-12-07
申请号：US12054317
申请日：2008-03-24
申请人： Richard W. Smith , Hang Kwan , Manzurul Khan
发明人： Richard W. Smith , Hang Kwan , Manzurul Khan
IPC分类号： G06F17/50 , G06F9/45
CPC分类号： G06F17/5031 , G06F2217/84
摘要： A pruning algorithm for generating a reverse donut model (RDM) for running timing analysis for a block in an IC includes logic to reduce a hierarchical model of the IC to a single level flat model. A block from a plurality of blocks that make up the IC is identified from the single level flat model of the IC. The pruning algorithm is further used to initialize a timer and to define timing constraints associated with each of a plurality of input and output pins associated with the identified block. A RDM for the identified block is generated by identifying and including connectivity information associated with a plurality of input and output pins in an outer boundary of the identified block and at least one layer of interface connection between each of the plurality of input and output pins in the outer layer of the identified block and one or more circuit elements external to the identified block in the IC interfacing with each of the plurality of input and output pins in the identified block. The generated RDM acts as a blackbox for the identified block and is used in place of the identified block for running the timing analysis.
摘要翻译：用于生成用于对IC中的块运行时序分析的反向环形模型（RDM）的修剪算法包括将IC的分级模型减小到单个级别平面模型的逻辑。从IC的单级平面型号识别来自构成IC的多个块的块。修剪算法还用于初始化定时器并且定义与与所识别的块相关联的多个输入和输出引脚中的每一个相关联的定时约束。通过识别并包括与所识别的块的外边界中的多个输入和输出引脚相关联的连通性信息以及多个输入和输出引脚中的每一个之间的至少一层接口连接来生成用于所识别的块的RDM 所识别的块的外层和IC中所识别的块外部的一个或多个电路元件与所识别的块中的多个输入和输出引脚中的每一个接口连接。生成的RDM用作识别块的黑盒，并用于代替用于运行时序分析的标识块。

35. 发明授权

US07849203B2 Command and control of arbitrary resources in a peer-to-peer network 有权
标题翻译：命令和控制对等网络中的任意资源
公开(公告)号：US07849203B2
公开(公告)日：2010-12-07
申请号：US10845508
申请日：2004-05-12
申请人： Howard Berkey , Greg Corson , John Paul Bates
发明人： Howard Berkey , Greg Corson , John Paul Bates
IPC分类号： G06F15/16
CPC分类号： H04L67/104 , H04L29/08846 , H04L67/1068 , H04L67/28 , H04L67/2876
摘要： Provided is a method and apparatus for virtualizing access to resources in a distributed peer-to-peer (P2P) network. Specifically, a resource locally managed by a peer in the P2P network can be published such that other peers can identify the peer managing the resource. Any peer requesting access to the resource of another peer establishes communication to the peer managing the resource. After establishing communication, a proxy of the peer managing the resource can establish a proxy interface. The proxy interface operating on the peer requesting access, permits the peer requesting access to generate command and control data to control the resource. Thus, the peer requesting access believes that it manages the local resource, while in reality, the peer requesting access only has virtualized access to the resource.
摘要翻译：提供了一种用于虚拟化分布式对等（P2P）网络中的资源的访问的方法和装置。具体来说，可以发布由P2P网络中的对等体本地管理的资源，使得其他对等体可以识别管理资源的对等体。请求访问另一个对等体的资源的任何对等体建立与管理资源的对等体的通信。建立通信后，管理资源的对等体的代理可以建立代理接口。在对等体上操作的代理接口请求访问，允许对等体请求访问生成命令和控制数据以控制资源。因此，对等体请求访问认为它管理本地资源，而实际上，对等请求访问仅具有对资源的虚拟访问。

36. 发明授权

US07841820B2 Universal modular wafer transport system 有权
标题翻译：通用模块化晶圆输送系统
公开(公告)号：US07841820B2
公开(公告)日：2010-11-30
申请号：US11938236
申请日：2007-11-09
申请人： Anthony C. Bonora , Richard H. Gould , Roger G. Hine , Michael Krolak , Jerry A. Speasl
发明人： Anthony C. Bonora , Richard H. Gould , Roger G. Hine , Michael Krolak , Jerry A. Speasl
IPC分类号： B65G54/02
CPC分类号： H01L21/67778 , H01L21/67766 , H01L21/67775 , H01L21/68707 , Y10S414/139
摘要： The present invention is a wafer transfer system that transports individual wafers between chambers within an isolated environment. In one embodiment, a wafer is transported by a wafer shuttle that travel within a transport enclosure. The interior of the transport enclosure is isolated from the atmospheric conditions of the surrounding wafer fabrication facility. Thus, an individual wafer may be transported throughout the wafer fabrication facility without having to maintain a clean room environment for the entire facility. The wafer shuttle may be propelled by various technologies, such as, but not limited to, magnetic levitation or air bearings. The wafer shuttle may also transport more than one wafer simultaneously. The interior of the transport enclosure may also be under vacuum, gas-filled, or subject to filtered air.
摘要翻译：本发明是一种晶片传送系统，其在隔离环境中的室之间输送各个晶片。在一个实施例中，晶片由在运输箱内行进的晶片梭运送。运输箱的内部与周围的晶片制造设备的大气条件隔离。因此，单个晶片可以在整个晶片制造设备中运输，而不必为整个设备保持洁净室环境。晶片梭可以通过各种技术来推动，例如但不限于磁悬浮或空气轴承。晶片梭可能同时传送多于一个晶片。运输箱的内部也可以在真空下，充满气体，或经过过滤的空气。

37. 发明授权

US07836219B1 System and method for authentication of embedded RAID on a host RAID card 有权
标题翻译：用于主机RAID卡上嵌入式RAID认证的系统和方法
公开(公告)号：US07836219B1
公开(公告)日：2010-11-16
申请号：US11054785
申请日：2005-02-09
申请人： Fadi A. Mahmoud , Ganapathy S. Sridaran
发明人： Fadi A. Mahmoud , Ganapathy S. Sridaran
IPC分类号： G06F3/00 , G06F9/445
CPC分类号： G06F21/123
摘要： An invention is provided for authenticating software associated with an embedded device on a motherboard. An embodiment includes executing an option ROM BIOS for the embedded device. If a bit pattern read from a first memory located on the host card does not match a predetermined bit pattern, the option ROM BIOS is terminated. In another embodiment, a first memory address is provided to the address lines of a memory device located on the host card and a first set of data is output from the memory device, followed by a second memory address to output a second set of data. The second memory address is equal to the first memory address plus the maximum addressable size of the memory device. The first set of data is compared to the second data, and the option ROM BIOS is terminated if the first and second sets of data do not match.
摘要翻译：提供了一种用于认证与主板上的嵌入式设备相关联的软件的发明。实施例包括为嵌入式设备执行选项ROM BIOS。如果从位于主机卡上的第一存储器读取的位模式与预定位模式不匹配，则选项ROM BIOS终止。在另一个实施例中，第一存储器地址被提供给位于主机卡上的存储器设备的地址线，并且第一组数据从存储器件输出，随后是第二存储器地址以输出第二组数据。第二个存储器地址等于第一个存储器地址加上存储器件的最大寻址大小。将第一组数据与第二数据进行比较，如果第一组数据和第二组数据不匹配，则选项ROM BIOS将被终止。

38. 发明授权

US07830191B2 Vernier delay circuit 有权
标题翻译：游标延迟电路
公开(公告)号：US07830191B2
公开(公告)日：2010-11-09
申请号：US12396219
申请日：2009-03-02
申请人： Shoji Kojima , Masakatsu Suda
发明人： Shoji Kojima , Masakatsu Suda
IPC分类号： H03H11/26
CPC分类号： H03K5/131 , H03K2005/00052 , H03K2005/00065 , H03L7/0805 , H03L7/0995
摘要： A ring oscillator oscillates at a frequency determined by an input bias signal. A bias signal adjusting unit produces a bias signal for the ring oscillator using feedback so that the oscillation frequency of the ring oscillator matches a predetermined reference frequency. An individual bias circuit includes a plurality of bias circuits provided for a total of N second variable delay elements, respectively. The bias circuits are configured such that the bias signals can be individually adjusted.
摘要翻译：环形振荡器以由输入偏置信号确定的频率振荡。偏置信号调整单元使用反馈产生环形振荡器的偏置信号，使得环形振荡器的振荡频率与预定的参考频率匹配。单独的偏置电路包括分别为总共N个第二可变延迟元件提供的多个偏置电路。偏置电路被配置成使得可以单独地调整偏置信号。

39. 发明授权

US07822935B2 Methods for data-smuggling 有权
标题翻译：数据走私方法
公开(公告)号：US07822935B2
公开(公告)日：2010-10-26
申请号：US11772211
申请日：2007-06-30
申请人： Amir Mosek
发明人： Amir Mosek
IPC分类号： G06F12/00
CPC分类号： G06F12/1441
摘要： The present invention discloses methods for an application, running on a host system, to access a restricted area of a storage device, the method including the steps of: providing a file system for running on the host system; restricting access, by the file system, to the restricted area; sending an indication, from the application to the storage device, that data being sent by the application to the storage device via the file system is intended for the restricted area; detecting the indication in the storage device; and making the data, residing in the restricted area, available for reading by the application upon receiving an application request. Preferably, the method further includes the step of: releasing wasted areas, of the storage device, for use by the file system. Preferably, the method further includes the step of: copying non-restricted data from a non-restricted area into the restricted area.
摘要翻译：本发明公开了一种在主机系统上运行以访问存储设备的受限区域的应用的方法，所述方法包括以下步骤：提供用于在所述主机系统上运行的文件系统; 限制文件系统访问限制区域; 从所述应用向所述存储设备发送由所述应用经由所述文件系统发送到所述存储设备的数据指示所述受限区域; 检测存储设备中的指示; 并且在接收到应用请求时，驻留在限制区域中的数据可供应用读取。优选地，该方法还包括以下步骤：释放存储装置的浪费区域供文件系统使用。优选地，该方法还包括以下步骤：将非受限制的数据从非限制区域复制到限制区域中。

40. 发明授权

US07814263B2 Erase history-based flash writing method 有权
标题翻译：擦除基于历史的闪存写入方式
公开(公告)号：US07814263B2
公开(公告)日：2010-10-12
申请号：US11727986
申请日：2007-03-29
申请人： Ori Stern , Amir Mosek
发明人： Ori Stern , Amir Mosek
IPC分类号： G06F12/00
CPC分类号： G11C16/102
摘要： A method for writing into a flash memory device includes calculating a physical block for writing data thereto, checking whether the calculated physical block has been erased since a last power-up of the device and if it has been erased writing the data, or, if it has not been erased performing a refresh operation thereby obtaining a newly erased block since a last power-up that the data can be written to. The newly erased block may be the calculated block or another block of the flash memory.
摘要翻译：一种用于写入闪速存储装置的方法包括：计算用于向其写入数据的物理块，检查所述计算的物理块是否已经从设备的最后上电并且已被擦除写入数据而被擦除，或者如果由于可以写入数据的最后一次上电，所以没有擦除执行刷新操作从而获得新擦除的块。新擦除的块可以是计算的块或闪存的另一块。

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