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31. 发明申请

US20080228950A1 MEMORY POWER DOWN MODE EXIT METHOD AND SYSTEM 审中-公开
标题翻译：存储器掉电模式退出方法和系统
公开(公告)号：US20080228950A1
公开(公告)日：2008-09-18
申请号：US11686067
申请日：2007-03-14
申请人： Margaret Clark Freebern , Farrukh Aquil , Wolfgang Hokenmaier
发明人： Margaret Clark Freebern , Farrukh Aquil , Wolfgang Hokenmaier
IPC分类号： G06F3/00
CPC分类号： G11C7/1045 , G11C5/143 , G11C11/4074 , G11C2207/2227
摘要： A memory includes a circuit having a set terminal for receiving an input signal indicating a request to exit a power-down mode. The circuit is configured to provide an output signal to enable exiting the power-down mode in response to the input signal before the input signal is latched.
摘要翻译：存储器包括具有用于接收指示退出掉电模式的请求的输入信号的设置终端的电路。电路被配置为提供输出信号，以便在输入信号被锁存之前响应于输入信号而退出掉电模式。

32. 发明授权

US07415387B2 Die and wafer failure classification system and method 失效
标题翻译：模具和晶圆故障分类系统及方法
公开(公告)号：US07415387B2
公开(公告)日：2008-08-19
申请号：US11612541
申请日：2006-12-19
申请人： Kevin L. Fields , Timothy J. A. Bynum
发明人： Kevin L. Fields , Timothy J. A. Bynum
IPC分类号： G06F11/30
CPC分类号： G01R31/2894 , G01R31/31718
摘要： A system and method for classifying failures of semiconductor integrated circuit dies using a unique input vector created from die level characterization data to classify wafer (process related) and die level (defect related) patterns. The failure classification may then be used to assign the appropriate yield loss by die. The classification results produced by the plurality of classifiers are examined with a preference towards assigning a wafer level failure classification to failure data for a die when any of the plurality of failure classification results indicates a presence of a wafer level failure.
摘要翻译：一种用于使用由晶粒级表征数据创建的唯一输入向量来分类半导体集成电路管芯的故障的系统和方法，以对晶片（与工艺相关）和管芯级（缺陷相关）模式进行分类。然后，故障分类可用于通过模具分配适当的产量损失。当多个故障分类结果中的任何一个指示晶片级故障的存在时，对多个分类器产生的分类结果进行检查，优选将晶片级故障分类分配给芯片的故障数据。

33. 发明申请

US20080192543A1 Method and Apparatus for Selecting Redundant Memory Cells 审中-公开
标题翻译：选择冗余存储单元的方法和设备
公开(公告)号：US20080192543A1
公开(公告)日：2008-08-14
申请号：US11673771
申请日：2007-02-12
申请人： Jungwon Kim , Jiho Kim , Changduk Kim
发明人： Jungwon Kim , Jiho Kim , Changduk Kim
IPC分类号： G11C16/06
CPC分类号： G11C29/24 , G11C29/808 , G11C29/812
摘要： In a semiconductor memory which comprises a main memory array, redundant memory cells, and a plurality of repair fuse boxes, a method of selecting redundant memory cells in relation to repair fuse boxes, comprising testing redundant memory cells to determine whether they are valid or defective, and making a selection of redundant memory cells which allocates valid redundant memory cells to respective repair fuse boxes but which does not allocate defective redundant memory cells to any repair fuse boxes.
摘要翻译：在包括主存储器阵列，冗余存储器单元和多个修复保险丝盒的半导体存储器中，选择与修复保险丝盒相关的冗余存储器单元的方法，包括测试冗余存储器单元以确定它们是有效还是有缺陷并且选择冗余存储器单元，其将有效的冗余存储器单元分配给相应的修复保险丝盒，但不将有缺陷的冗余存储器单元分配给任何维修保险丝盒。

34. 发明申请

US20080191187A1 METHOD FOR MANUFACTURING A PHASE CHANGE MEMORY DEVICE WITH PILLAR BOTTOM ELECTRODE 有权
标题翻译：用于制造具有底部电极的相变存储器件的方法
公开(公告)号：US20080191187A1
公开(公告)日：2008-08-14
申请号：US11764678
申请日：2007-06-18
申请人： HSIANG LAN LUNG , CHIEH-FANG CHEN , YI-CHOU CHEN , SHIH HUNG CHEN , CHUNG HON LAM , ERIC ANDREW JOSEPH , ALEJANDRO GABRIEL SCHROTT , MATTHEW J. BREITWISCH , GEOFFREY WILLIAM BURR , THOMAS D. HAPP , JAN BORIS PHILIPP
发明人： HSIANG LAN LUNG , CHIEH-FANG CHEN , YI-CHOU CHEN , SHIH HUNG CHEN , CHUNG HON LAM , ERIC ANDREW JOSEPH , ALEJANDRO GABRIEL SCHROTT , MATTHEW J. BREITWISCH , GEOFFREY WILLIAM BURR , THOMAS D. HAPP , JAN BORIS PHILIPP
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.
摘要翻译：用于制造蘑菇细胞型相变存储器的方法是基于在包括与接入电路电连通的导电触点阵列的基板上制造底部电极材料的柱。沉积一层电极材料，使其与导电触点阵列可靠地电接触。蚀刻电极材料以在对应的导电触点上形成电极柱的图案。接下来，将介电材料沉积在图案上并且被平坦化以提供暴露电极柱顶表面的电极表面。接下来，沉积诸如硫族化物或其它相变材料的可编程电阻材料层，随后沉积顶层电极材料层。描述了包括具有比顶表面更大的底表面的底部电极柱的装置。

35. 发明申请

US20080147355A1 Die and Wafer Failure Classification System and Method 失效
标题翻译：模具和晶圆失效分类系统和方法
公开(公告)号：US20080147355A1
公开(公告)日：2008-06-19
申请号：US11612541
申请日：2006-12-19
申请人： Kevin L. Fields , Timothy J.A. Bynum
发明人： Kevin L. Fields , Timothy J.A. Bynum
IPC分类号： G06F19/00
CPC分类号： G01R31/2894 , G01R31/31718
摘要： A system and method for classifying failures of semiconductor integrated circuit dies using a unique input vector created from die level characterization data to classify wafer (process related) and die level (defect related) patterns. The failure classification may then be used to assign the appropriate yield loss by die. The classification results produced by the plurality of classifiers are examined with a preference towards assigning a wafer level failure classification to failure data for a die when any of the plurality of failure classification results indicates a presence of a wafer level failure.
摘要翻译：一种用于使用由晶粒级表征数据创建的唯一输入向量来分类半导体集成电路管芯的故障的系统和方法，以对晶片（与工艺相关）和管芯级（缺陷相关）模式进行分类。然后，故障分类可用于通过模具分配适当的产量损失。当多个故障分类结果中的任何一个指示晶片级故障的存在时，对多个分类器产生的分类结果进行检查，优选将晶片级故障分类分配给芯片的故障数据。

36. 发明授权

US07385872B2 Method and apparatus for increasing clock frequency and data rate for semiconductor devices 失效
标题翻译：用于增加半导体器件的时钟频率和数据速率的方法和装置
公开(公告)号：US07385872B2
公开(公告)日：2008-06-10
申请号：US11581350
申请日：2006-10-17
申请人： Klaus Nierle , KoonHee Lee
发明人： Klaus Nierle , KoonHee Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1078 , G11C7/1084 , G11C7/225 , G11C11/4076 , G11C11/4093 , G11C29/006 , G11C29/023
摘要： An embodiment of the present invention receives a data signal and at least one data shift signal that facilitates adjustment of the data signal and produces a resulting data signal with a data rate greater than a data rate of the data signal.
摘要翻译：本发明的一个实施例接收数据信号和至少一个数据移位信号，其有利于数据信号的调整并产生数据速率大于数据信号数据速率的结果数据信号。

37. 发明授权

US08138028B2 Method for manufacturing a phase change memory device with pillar bottom electrode 有权
标题翻译：具有柱底电极的相变存储器件的制造方法
公开(公告)号：US08138028B2
公开(公告)日：2012-03-20
申请号：US11764678
申请日：2007-06-18
申请人： Hsiang Lan Lung , Chieh Fang Chen , Yi Chou Chen , Shih Hung Chen , Chung Hon Lam , Eric Andrew Joseph , Alejandro Gabriel Schrott , Matthew J. Breitwisch , Geoffrey William Burr , Thomas D. Happ , Jan Boris Philipp
发明人： Hsiang Lan Lung , Chieh Fang Chen , Yi Chou Chen , Shih Hung Chen , Chung Hon Lam , Eric Andrew Joseph , Alejandro Gabriel Schrott , Matthew J. Breitwisch , Geoffrey William Burr , Thomas D. Happ , Jan Boris Philipp
IPC分类号： H01L45/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2436 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/14 , H01L45/146 , H01L45/147 , H01L45/148 , H01L45/1625 , H01L45/1641 , H01L45/1675
摘要： A method for manufacturing a mushroom-cell type phase change memory is based upon manufacturing a pillar of bottom electrode material upon a substrate including an array of conductive contacts in electrical communication with access circuitry. A layer of electrode material is deposited making reliable electrical contact with the array of conductive contacts. Electrode material is etched to form a pattern of electrode pillars on corresponding conductive contacts. Next, a dielectric material is deposited over the pattern and planarized to provide an electrode surface exposing top surfaces of the electrode pillars. Next, a layer of programmable resistive material, such as a chalcogenide or other phase change material, is deposited, followed by deposition of a layer of a top electrode material. A device including bottom electrode pillars with larger bottom surfaces than top surfaces is described.
摘要翻译：用于制造蘑菇细胞型相变存储器的方法是基于在包括与接入电路电连通的导电触点阵列的基板上制造底部电极材料的柱。沉积一层电极材料，使其与导电触点阵列可靠地电接触。蚀刻电极材料以在对应的导电触点上形成电极柱的图案。接下来，将介电材料沉积在图案上并且被平坦化以提供暴露电极柱顶表面的电极表面。接下来，沉积诸如硫族化物或其它相变材料的可编程电阻材料层，随后沉积顶层电极材料层。描述了包括具有比顶表面更大的底表面的底部电极柱的装置。

38. 发明授权

US07802133B2 System and method for addressing errors in a multiple-chip memory device 有权
标题翻译：用于解决多芯片存储器件中的错误的系统和方法
公开(公告)号：US07802133B2
公开(公告)日：2010-09-21
申请号：US11819759
申请日：2007-06-29
申请人： KoonHee Lee , Ryan Patterson , Hoon Ryu , Klaus Nierle
发明人： KoonHee Lee , Ryan Patterson , Hoon Ryu , Klaus Nierle
IPC分类号： G06F11/00
CPC分类号： G11C29/802 , G11C5/04 , G11C2029/4402 , G11C2029/5606
摘要： A multiple-chip memory device, comprising: a volatile memory element configured to store a plurality of bits of information, and later access the plurality of bits of information; a non-volatile memory element configured to store initial repair information identifying one or more errors in the volatile memory element; and a master memory controller configured to read the initial repair information, and to provide processed repair information and volatile memory control signals to the volatile memory element, wherein the volatile memory element is configured to store and access the plurality of bits of information based on the processed repair information and logical address information.
摘要翻译：一种多芯片存储器件，包括：易失性存储器元件，被配置为存储多个位的信息，并且稍后访问所述多个位的信息; 非易失性存储器元件，被配置为存储识别所述易失性存储元件中的一个或多个错误的初始修复信息; 以及主存储器控制器，被配置为读取所述初始修复信息，并且向所述易失性存储器元件提供经处理的修复信息和易失性存储器控制信号，其中所述易失性存储器元件被配置为基于所述易失性存储器元件存储和访问所述多个位信息处理修复信息和逻辑地址信息。

39. 发明授权

US07760546B2 Integrated circuit including an electrode having an outer portion with greater resistivity 失效
标题翻译：集成电路包括具有较大电阻率的外部部分的电极
公开(公告)号：US07760546B2
公开(公告)日：2010-07-20
申请号：US12038850
申请日：2008-02-28
申请人： Shoaib Zaidi
发明人： Shoaib Zaidi
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C2213/52 , H01L45/06 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/148 , H01L45/16
摘要： An integrated circuit includes a first electrode including an inner portion and an outer portion laterally surrounding the inner portion. The outer portion has a greater resistivity than the inner portion. The integrated circuit includes a second electrode and resistivity changing material contacting the first electrode and coupled to the second electrode.
摘要翻译：集成电路包括包括内部部分和横向围绕内部部分的外部部分的第一电极。外部部分具有比内部部分更大的电阻率。集成电路包括与第一电极接触并耦合到第二电极的第二电极和电阻率变化材料。

40. 发明授权

US07755338B2 Voltage regulator pole shifting method and apparatus 失效
标题翻译：电压调节器极移方法及装置
公开(公告)号：US07755338B2
公开(公告)日：2010-07-13
申请号：US11776688
申请日：2007-07-12
申请人： Iman Taha , Vincent Acierno
发明人： Iman Taha , Vincent Acierno
IPC分类号： G05F1/575
CPC分类号： G05F1/565
摘要： A voltage regulator comprises first and second amplifier stages, a common-source output stage and a feedback path. The output stage drives a capacitive load with a regulated voltage responsive to a signal applied to the output stage. The capacitive load sets the dominant pole of the voltage regulator. The first amplifier stage amplifies the difference between the regulated voltage and a reference voltage. The second amplifier stage drives the output stage with a signal corresponding to the difference between the regulated voltage and the reference voltage. The feedback path couples an output node of the second amplifier stage to an input node of the second amplifier stage for reducing the output resistance of the second amplifier stage to shift a non-dominant pole of the voltage regulator set by the second amplifier stage.
摘要翻译：电压调节器包括第一和第二放大器级，共源输出级和反馈路径。响应于施加到输出级的信号，输出级以调节电压驱动电容性负载。电容负载设置电压调节器的主极。第一放大器级放大调节电压和参考电压之间的差。第二放大器级用对应于调节电压和参考电压之间的差的信号来驱动输出级。反馈路径将第二放大器级的输出节点耦合到第二放大器级的输入节点，用于减小第二放大器级的输出电阻，以移动由第二放大器级设置的稳压器的非主导极。

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