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31. 发明授权

US4495600A Tabulation system 失效
标题翻译：制表系统
公开(公告)号：US4495600A
公开(公告)日：1985-01-22
申请号：US508577
申请日：1983-06-28
申请人： Yoshiyasu Kikuchi , Masamichi Shutoh , Hitoshi Miyai , Hidetoshi Itoh
发明人： Yoshiyasu Kikuchi , Masamichi Shutoh , Hitoshi Miyai , Hidetoshi Itoh
IPC分类号： G06F17/21 , G06F17/24 , G06F7/00 , B41J21/00 , G06F3/14
CPC分类号： G06F17/245 , G06F17/212
摘要： A tabulation system for delivery to a medium of data information suitably arranged for tabulation of character series and ruled lines, and a control for controlling the data information arrangement applied to the medium. The control operates to allow the medium to sequentially deliver out control information for defining desired vertical ruled lines (columns), information regarding a horizontal ruled line (row) defining the upper side of a field between adjacent vertical ruled lines, information regarding character series to be written in the field and control commands for the writing, and information regarding a horizontal ruled line defining the lower side of the field.
摘要翻译：一种用于传送到适当地布置用于字符串和格线列表的数据信息介质的制表系统，以及用于控制应用于介质的数据信息布置的控制。控制操作以允许介质顺序地输出用于定义所需垂直格线（列）的控制信息，关于限定相邻垂直格线之间的场的上侧的水平划线（行）的信息，关于字符串的信息写在字段中并控制写入命令，以及关于定义字段的下侧的水平划线的信息。

32. 发明授权

US4493046A Apparatus for generation of binary pseudo-random numbers 失效
标题翻译：用于生成二进制伪随机数的装置
公开(公告)号：US4493046A
公开(公告)日：1985-01-08
申请号：US381714
申请日：1982-05-24
申请人： Tadashi Watanabe
发明人： Tadashi Watanabe
IPC分类号： G06F7/58 , H03K3/84 , G06F7/38
CPC分类号： H03K3/84 , G06F7/584 , G06F2207/581 , G06F2207/583
摘要： Apparatus for generation of binary pseudo-random numbers of n bits by use of the maximum-length shift register sequence based on a primitive polynomial, f(x)=x.sup.p +x.sup.q +1, where p and q are positive integers satisfying the relation p>q.gtoreq.1. The apparatus comprises p-bit storage means; (p-q) bit shift means for shifting the contents of said p-bit storage means; exclusive OR means for exclusive-ORing m (m.gtoreq.n) bits resulting from the shifting and consecutive m bits stored in said storage means bit by bit; means for restoring exclusive-ORed results to uppermost bits of said storage means and uppermost (p-m) bits of said storage means to lowermost (p-m) bits thereof; and means for extracting uppermost n bits from said storage means.
摘要翻译：用于通过使用基本多项式f（x）= xp + xq + 1的最大长度移位寄存器序列来生成n位的二进制伪随机数的装置，其中p和q是满足关系p的正整数 > q> / = 1。该装置包括p位存储装置; （p-q）位移位装置，用于移位所述p位存储装置的内容; 异或装置，用于对存储在所述存储装置中的移位和连续m位逐位进行异或运算m（m> / = n）位; 用于将所述存储装置的最高比特和所述存储装置的最上位（p-m）比特恢复到最低（p-m）比特的装置; 以及用于从所述存储装置提取最上面n个比特的装置。

33. 发明授权

US4491834A Display controlling apparatus 失效
标题翻译：显示控制装置
公开(公告)号：US4491834A
公开(公告)日：1985-01-01
申请号：US598360
申请日：1984-04-12
申请人： Tetsuji Oguchi
发明人： Tetsuji Oguchi
IPC分类号： G09G5/34 , G09G1/16
CPC分类号： G09G5/346
摘要： A display control system has a memory for storing display information and a memory access circuit for reading display information out of this memory. This memory access circuit includes a first circuit in which a memory address is set, a second circuit for sequentially varying the memory address by a predetermined value, and a third circuit for adding to the memory address a preset value, which is different from the predetermined value. A control circuit gives a designation of the addresses to the memory, as a result of the cooperation of the second circuit and the third circuit. The control circuit can be achieved so that display information is read while a memory address may be varied by at least two different means (the second and third circuits above). Thus, it becomes possible to selectively designate a part of a memory region and to display the information of the selected memory region.
摘要翻译：显示控制系统具有用于存储显示信息的存储器和用于从该存储器读出显示信息的存储器访问电路。该存储器访问电路包括其中设置存储器地址的第一电路，用于将存储器地址顺序地改变预定值的第二电路，以及用于将存储器地址与预定值不同的预设值相加的第三电路值。作为第二电路和第三电路的协作的结果，控制电路给予存储器地址的指定。可以实现控制电路，使得在存储器地址可以通过至少两个不同装置（上述第二和第三电路）改变时，读取显示信息。因此，可以选择性地指定存储区域的一部分并显示所选存储区域的信息。

34. 发明授权

US4489424A Frequency divider making use of Josephson junction circuits 失效
标题翻译：使用约瑟夫逊结电路的分频器
公开(公告)号：US4489424A
公开(公告)日：1984-12-18
申请号：US376994
申请日：1982-05-11
申请人： Junichi Sone
发明人： Junichi Sone
IPC分类号： H03B19/14 , H01L39/22 , H03K3/38 , H03K21/00 , H03K23/76 , H03K23/80 , H03K23/24
CPC分类号： H03K3/38 , H03K23/763 , Y10S505/83 , Y10S505/864
摘要： A frequency divider is provided by coupling the gate current paths of a pair of Josephson junction gate circuits in parallel with the control current path of a third Josephson junction gate circuit being connected in series with the gate current path of one of the first pair of Josephson junctions. The gate current path of the third Josephson junction is connected in series with the control current path of the other of the first pair of Josephson junctions, and an input signal to be frequency divided is connected in common to the connection point of the control current path of the first Josephson junction and gate current path of the third Josephson junction. Current flowing through the control current path of the first Josephson junction will be at one-half the frequency of the input current. A plurality of frequency dividers may be cascaded to perform 1/2.sup.N frequency division.
摘要翻译：通过将一对约瑟夫逊结门电路的栅极电流路径与第三约瑟夫逊结门电路的控制电流路径并联连接，与第一对约瑟夫森（Josephson）之一的栅极电流路径串联连接来提供分频器路口第三约瑟夫逊结的栅极电流路径与第一对约瑟夫逊结中的另一对的控制电流路径串联连接，并且待分频的输入信号共同连接到控制电流路径的连接点的第一个约瑟夫逊结和第三个约瑟夫逊结的栅极电流路径。流过第一约瑟夫逊结的控制电流路径的电流将为输入电流频率的一半。多个分频器可以级联以执行1 / 2N分频。

35. 发明授权

US4489292A Stub type bandpass filter 失效
标题翻译：桩型带通滤波器
公开(公告)号：US4489292A
公开(公告)日：1984-12-18
申请号：US456620
申请日：1983-01-10
申请人： Hiroshi Ogawa
发明人： Hiroshi Ogawa
IPC分类号： H01P1/20 , H01P1/201 , H01P1/202 , H01P1/203 , H01P1/207 , H01P1/212
CPC分类号： H01P1/2039 , H01P1/207
摘要： A bandpass filter has a line extending from an input terminal to an output terminal. Three stubs are connected to the line at three different locations on the line at a spacing which is 1/8 of the wavelength, at the center frequency of the passband. Each of the three stubs is short-circuited at a first end and open at a second end and has a total length which is 1/4 the wavelength of said center frequency. The outermost of the three stubs is connected to the transmission line, at a position which is 1/6 the wavelength, from the first end. The intermediate of the three stubs is connected to the line at a position which is either 1/8 or 1/4 the wavelength of the center frequency.
摘要翻译：带通滤波器具有从输入端子延伸到输出端子的线。三根短线在线上三个不同位置的线路上，以通带宽度的中心频率为波长1/8的间隔。三个短截线中的每一个在第一端短路并在第二端开放，总长度为所述中心频率波长的1/4。三根短截线的最外侧从第一端连接到距离波长1/6的位置处的传输线。三个短截线的中间在与中心频率的波长的1/8或1/4波长的位置连接。

36. 发明授权

US4485478A Digital burst signal transmission system 失效
标题翻译：数字突发信号传输系统
公开(公告)号：US4485478A
公开(公告)日：1984-11-27
申请号：US382983
申请日：1982-05-28
申请人： Masami Takada
发明人： Masami Takada
IPC分类号： H04J3/00 , H04B7/15 , H04B7/212 , H04J3/10 , H04L25/49 , H04L27/18 , H03C1/06
CPC分类号： H04J3/10 , H04L25/4923
摘要： A gated data burst in a multiplex transmission system is low pass filtered and modulates a carrier wave. The modulated signal has transient skirts on its leading and trailing edges due to the roll-off characteristic of the filter, and these skirts would ordinarily interfere with the signal bursts in adjoining time slots. To avoid this the skirts are clipped off by a further gate signal whose window is slightly wider than that of the first gate, and which is timed such that its edges occur at 0 levels of the burst carrier.
摘要翻译：多路传输系统中的门控数据脉冲串被低通滤波并调制载波。由于滤波器的滚降特性，调制信号在其前缘和后缘具有短暂的裙边，并且这些裙部通常会干扰相邻时隙中的信号脉冲串。为了避免这种情况，裙边被另一个门窗信号挡住，窗口比第一门略宽，并且定时使其边缘出现在突发载波的0电平。

37. 发明授权

US4485461A Memory circuit 失效
标题翻译：存储电路
公开(公告)号：US4485461A
公开(公告)日：1984-11-27
申请号：US367523
申请日：1982-04-12
申请人： Satoru Kobayashi
发明人： Satoru Kobayashi
IPC分类号： G11C7/10 , G11C11/40
CPC分类号： G11C7/10 , G11C7/1033
摘要： A memory circuit which can perform consecutive write operations at a high speed is disclosed. The memory circuit comprises a plurality of bus lines, a plurality of memory cell groups associated with the respective bus lines, a plurality of latch circuits coupled to the respective bus lines, and means for sequentially supplying the bus lines with write data, in which the write data are stored in the latch circuits and transferred to selected memory cells of the respective memory cell groups.
摘要翻译：公开了能够高速执行连续写入操作的存储电路。存储电路包括多个总线，与相应总线相关联的多个存储单元组，耦合到相应总线的多个锁存电路，以及用于顺序向总线线路提供写入数据的装置，其中写入数据被存储在锁存电路中并传送到相应的存储单元组的选择存储单元。

38. 发明授权

US4484358A Receiver having switched capacitor filter 失效
标题翻译：接收器具有开关电容滤波器
公开(公告)号：US4484358A
公开(公告)日：1984-11-20
申请号：US473112
申请日：1983-03-07
申请人： Koji Iwahashi
发明人： Koji Iwahashi
IPC分类号： H03G3/34 , H03H19/00 , H04B1/16 , H04B1/26 , H04B1/10
CPC分类号： H03G3/341 , H03H19/004 , H04B1/26
摘要： A receiver utilizing a switched capacitor filter is disclosed. The switched capacitor filter has a band pass determined by a control signal applied thereto. A waveform shaping circuit generates the control signal as a function of a received signal which has been modulated in angle and amplified. The wave shaper generates the control signal only when the amplified signal is above a predetermined value and generates the signal at a frequency which causes the switched capacitor filter to operate at the correct band pass.
摘要翻译：公开了一种使用开关电容滤波器的接收机。开关电容滤波器具有由施加到其上的控制信号确定的带通。波形整形电路根据已经被角度被调制并被放大的接收信号产生控制信号。波形整形器仅在放大信号高于预定值时产生控制信号，并以使开关电容滤波器以正确频带通过的频率产生信号。

39. 发明授权

US4483000A Circuit for eliminating spurious components resulting from burst control in a TDMA system 失效
标题翻译：用于消除由TDMA系统中的脉冲串控制引起的杂散分量的电路
公开(公告)号：US4483000A
公开(公告)日：1984-11-13
申请号：US338598
申请日：1982-01-11
申请人： Kazuhiro Yamamoto , Masaaki Atobe
发明人： Kazuhiro Yamamoto , Masaaki Atobe
IPC分类号： H04B7/212 , H04J3/10 , H04J3/16
CPC分类号： H04B7/212 , H04J3/10
摘要： In an electronic circuit comprising a modulator (35) and used in each substation of a TDMA system and responsive to a baseband data signal sequence for producing a burst in accordance with a first burst control pulse, spurious components resulting in the burst from the first burst control pulse are eliminated either by allowing the data sequence to pass through a low-pass filter (36) after switching (45) the sequence by the first burst control pulse or by filtering the first burst control pulse by a low-pass filter before switching a local oscillation signal by the first control pulse. An additional switching circuit may switch either a modulated signal supplied from the modulator or the local oscillation signal in response to a second burst control pulse that disappears after extinction of the first burst control pulse. Alternatively, a modifying circuit reverses polarities of a preceding and a following data signals immediately preceding and following the sequence, relative to a leading and a trailing end data signals of the sequence.
摘要翻译：在包括调制器（35）并且在TDMA系统的每个子站中使用并响应于基带数据信号序列以用于根据第一突发控制脉冲产生脉冲串的电子电路中，产生从第一突发通过允许数据序列在切换（45）序列第一突发控制脉冲之后通过低通滤波器（36）或者在切换之前通过低通滤波器对第一突发控制脉冲进行滤波来消除控制脉冲通过第一控制脉冲的本地振荡信号。响应于在第一突发控制脉冲消失之后消失的第二脉冲串控制脉冲，另外的切换电路可以切换从调制器提供的调制信号或本地振荡信号。或者，修改电路相对于序列的前端数据信号和后端数据信号反转在序列之前和之后的先前和后续数据信号的极性。

40. 发明授权

US4479258A Cross-polarization crosstalk canceller 失效
标题翻译：交叉极化串扰消除器
公开(公告)号：US4479258A
公开(公告)日：1984-10-23
申请号：US416112
申请日：1982-09-09
申请人： Junji Namiki
发明人： Junji Namiki
IPC分类号： H04B7/00 , H04L27/06 , H04B1/12
CPC分类号： H04B7/002 , H04L27/06
摘要： A cross-polarization crosstalk canceller is equipped to receive two polarized waves which are orthogonally crossing each other. The cross-polarization interference is eliminated by multiplying the signal received on one side by a compensating coefficient and adding the resulting product to the signal received on the other side. A discrimination error represents the difference between the reception signal after compensation and the identified value thereof. An adder and a subtractor supplies the sum and the difference between the real part and the imaginary part of the discrimination error. A discriminator detects equality between the absolute values of the real part and the imaginary part of the signal received on the interfering polarized wave side and supplies a control signal depending on the quadrant to which the signal belongs. A switch combines and varies a combination of the signs of the outputs of the adder and subtractor in response to the control signal supplied by the discriminator. A low-pass filter smooths the output of the switching in order to give the compensation coefficient.
摘要翻译：配备交叉极化串扰消除器以接收彼此正交交叉的两个偏振波。通过将在一侧接收的信号乘以补偿系数来消除交叉极化干扰，并将得到的乘积与另一侧接收的信号相加。鉴别误差表示补偿后的接收信号与其识别值之间的差。加法器和减法器提供鉴别误差的实部和虚部之和和之差。鉴别器检测在干扰极化波侧接收的信号的实部和虚部的绝对值之间的相等，并且根据信号所属的象限提供控制信号。开关根据由鉴别器提供的控制信号组合并改变加法器和减法器的输出的符号的组合。低通滤波器平滑开关的输出以给出补偿系数。

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