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31. 发明授权

US07650605B2 Method and apparatus for implementing atomicity of memory operations in dynamic multi-streaming processors 有权
标题翻译：用于在动态多流处理器中实现存储器操作的原子性的方法和装置
公开(公告)号：US07650605B2
公开(公告)日：2010-01-19
申请号：US11676541
申请日：2007-02-20
申请人： Stephen Melvin , Mario D. Nemirovsky
发明人： Stephen Melvin , Mario D. Nemirovsky
IPC分类号： G06F9/00 , G06F7/38 , G06F13/28 , G06F12/00
CPC分类号： G06F9/3851 , G06F9/3004 , G06F9/30087
摘要： A multi-streaming processor has a plurality of streams for streaming one or more instruction threads, a set of functional resources for processing instructions from streams, and a lock mechanism for locking selected memory locations shared by streams of the processor, the hardware-lock mechanism operating to set a lock when an atomic memory sequence is started and to clear a lock when an atomic memory sequence is completed. In preferred embodiments the lock mechanism comprises one or more storage locations associated with each stream of the processor, each storage location enabled to store a memory address a lock bit, and a stall bit. Methods for practicing the invention using the apparatus are also taught.
摘要翻译：多流处理器具有用于流式传输一个或多个指令线程的多个流，用于处理来自流的指令的一组功能资源，以及用于锁定由处理器的流共享的所选择的存储器位置的锁定机构，硬件锁定机构操作在原子存储器序列启动时设置锁定，并且当原子存储器序列完成时清除锁定。在优选实施例中，锁定机构包括与处理器的每个流相关联的一个或多个存储位置，每个存储位置能够存储存储器地址锁定位和失速位。还教导了使用该装置实施本发明的方法。

32. 发明授权

US07649901B2 Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing 有权
标题翻译：用于在多流分组处理中优化用于分组处理的可用上下文选择的方法和装置
公开(公告)号：US07649901B2
公开(公告)日：2010-01-19
申请号：US09881628
申请日：2001-06-13
申请人： Enrique Musoll , Mario Nemirovsky
发明人： Enrique Musoll , Mario Nemirovsky
IPC分类号： H04L12/56
CPC分类号： H04L29/06 , G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073 , H04L69/12 , H04L69/22
摘要： A context-selection mechanism is provided for selecting a best context from a pool of contexts for processing a data packet. The context selection mechanism comprises, an interface for communicating with a multi-streaming processor; circuitry for computing input data into a result value according to logic rule and for selecting a context based on the computed value and a loading mechanism for preloading the packet information into the selected context for subsequent processing. The computation of the input data functions to enable identification and selection of a best context for processing a data packet according to the logic rule at the instant time such that a multitude of subsequent context selections over a period of time acts to balance load pressure on functional units housed within the multi-streaming processor and required for packet processing. In preferred aspects, programmable singular or multiple predictive rules of logic are utilized in the selection process.
摘要翻译：提供了一种上下文选择机制，用于从用于处理数据分组的上下文池中选择最佳上下文。上下文选择机制包括：用于与多流处理器通信的接口; 用于根据逻辑规则将输入数据计算到结果值中并基于所计算的值来选择上下文的电路，以及用于将分组信息预加载到所选择的上下文中用于后续处理的加载机制。输入数据的计算功能用于根据逻辑规则来识别和选择用于处理数据分组的最佳上下文，使得在一段时间内多个随后的上下文选择用于平衡负载压力对功能性单元被容纳在多流处理器内并且需要进行数据包处理。在优选方面，在选择过程中利用可编程单数或多重预测逻辑规则。

33. 发明授权

US07636836B2 Fetch and dispatch disassociation apparatus for multistreaming processors 有权
标题翻译：用于多数据流处理器的获取和调度分离装置
公开(公告)号：US07636836B2
公开(公告)日：2009-12-22
申请号：US12173560
申请日：2008-07-15
申请人： Mario D. Nemirovsky , Adolfo M. Nemirovsky , Narendra Sankar , Enrique Musoll
发明人： Mario D. Nemirovsky , Adolfo M. Nemirovsky , Narendra Sankar , Enrique Musoll
IPC分类号： G06F9/24
CPC分类号： G06F9/3851
摘要： A dynamic multistreaming processor has instruction queues, each instruction queue corresponding to an instruction stream, and execution units. The dynamic multistreaming processor also has a dispatch stage to select at least one instruction from one of the instruction queues and to dispatch the selected at least one instruction to one of the execution units. Lastly the dynamic multistreaming processor has a queue counter, associated with each instruction queue, for indicating the number of instructions in each queue, and a fetch counter, associated with each instruction queue, for indicating an address from which to obtain instructions when the associated instruction queue is not full. The dynamic multistreaming processor might also have fetch counters for indicating a next instruction address from which to obtain at least one instruction when the associated instruction queue is not full. The dynamic multistreaming processor could also have a second counter for indicating a next instruction address.
摘要翻译：动态多流处理器具有指令队列，对应于指令流的每个指令队列和执行单元。动态多流处理器还具有调度阶段，用于从一个指令队列中选择至少一个指令，并将所选择的至少一个指令发送到执行单元之一。最后，动态多流处理器具有与每个指令队列相关联的用于指示每个队列中的指令数量的队列计数器，以及与每个指令队列相关联的提取计数器，用于指示当相关联的指令时从其获得指令的地址队列不满。动态多数据流处理器还可以具有用于指示下一个指令地址的读取计数器，当相关联的指令队列未满时，该指令地址从其获得至少一个指令。动态多流处理器还可以具有用于指示下一个指令地址的第二计数器。

34. 发明授权

US07634638B1 Instruction encoding for system register bit set and clear 有权
标题翻译：系统寄存器位的指令编码设置和清零
公开(公告)号：US07634638B1
公开(公告)日：2009-12-15
申请号：US10279210
申请日：2002-10-22
申请人： Michael Gottlieb Jensen
发明人： Michael Gottlieb Jensen
IPC分类号： G06F9/00 , G06F13/24
CPC分类号： G06F9/462 , G06F9/30018 , G06F9/3004 , G06F9/30101 , G06F9/30185 , G06F9/4812
摘要： An instruction encoding architecture is provided for a microprocessor to allow atomic modification of privileged architecture registers. The instructions include an opcode that designates to the microprocessor that the instructions are to execute in privileged (kernel) state only, and that the instructions are to communicate with privileged control registers, a field for designating which of a plurality of privileged architecture registers is to be modified, a field for designating which bit fields within the designated privileged architecture register is to be modified, and a field to designate whether the designated bit fields are to be set or cleared. The instruction encoding allows a single instruction to atomically set or clear bit fields within privileged architecture registers, without reading the privileged architecture registers into a general purpose register. In addition, the instruction encoding allows a programmer to specify whether the previous content of a privileged architecture register is to be saved to a general purpose register during the atomic modification.
摘要翻译：为微处理器提供指令编码架构，以允许对特权架构寄存器进行原子修改。指令包括指定给微处理器的操作码，指令仅在特权（内核）状态下执行，并且指令将与特权控制寄存器进行通信，该字段用于指定多个特权体系结构寄存器中的哪一个到被修改，用于指定要修改指定的特权体系结构寄存器中的哪些位字段的字段以及用于指定是否要设置或清除指定位字段的字段。指令编码允许单个指令在特权体系结构寄存器中原子地设置或清除位字段，而不将特权体系结构寄存器读入通用寄存器。此外，指令编码允许程序员指定在原子修改期间是否将特权架构寄存器的先前内容保存到通用寄存器。

35. 发明申请

US20090249351A1 Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same For Use In Multithreading Microprocessor 审中-公开
标题翻译：在多线程微处理器中使用相同的循环装置和指令调度调度器
公开(公告)号：US20090249351A1
公开(公告)日：2009-10-01
申请号：US12409363
申请日：2009-03-23
申请人： Michael Gottlieb Jensen
发明人： Michael Gottlieb Jensen
IPC分类号： G06F9/50
CPC分类号： G06F9/3851 , G06F7/5055 , G06F9/30079 , G06F9/30087 , G06F9/3009 , G06F9/3802 , G06F9/3814 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3859 , G06F9/3861 , G06F9/3867
摘要： An apparatus for selecting one of N requesters of a shared resource in a round-robin fashion is disclosed. One or more of the N requestors may be disabled from being selected in a selection cycle. The apparatus includes a first input that receives a first value specifying which of the N requestors was last selected. A second input receives a second value specifying which of the N requestors is enabled to be selected. A barrel incrementer, coupled to receive the first and second inputs, 1-bit left-rotatively increments the second value by the first value to generate a sum. Combinational logic, coupled to the barrel incrementer, generates a third value specifying which of the N requestors is selected next.
摘要翻译：公开了一种用于以循环方式选择共享资源的N个请求者之一的装置。 N个请求者中的一个或多个可以在选择周期中被禁止被选择。该装置包括第一输入，其接收指定最后选择的N个请求者中的哪一个的第一值。第二输入接收指定N个请求者中哪一个被选择的第二值。一个桶增量器，耦合以接收第一和第二输入，1位左旋转地使第二值递增第一值以产生和。耦合到桶增量器的组合逻辑生成指定下一个N个请求者中的哪一个的第三值。

36. 发明申请

US20090249046A1 APPARATUS AND METHOD FOR LOW OVERHEAD CORRELATION OF MULTI-PROCESSOR TRACE INFORMATION 审中-公开
标题翻译：用于多处理器跟踪信息的低周期相关的装置和方法
公开(公告)号：US20090249046A1
公开(公告)日：2009-10-01
申请号：US12060214
申请日：2008-03-31
申请人： Thomas Benjamin BERG , Ryan C. KINTER , Jaidev Prasad PATWARDHAN , Radhika THEKKATH
发明人： Thomas Benjamin BERG , Ryan C. KINTER , Jaidev Prasad PATWARDHAN , Radhika THEKKATH
IPC分类号： G06F9/30
CPC分类号： G06F11/3636 , G06F12/0815
摘要： A method of coordinating trace information in a multiprocessor system includes receiving processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a coherence indicator that demarks selective shared memory transactions. Coherence manager trace information is generated for each of the processors. The coherence manager trace information for each processor includes trace metrics and a coherence indicator.
摘要翻译：在多处理器系统中协调跟踪信息的方法包括从一组处理器接收处理器跟踪信息。来自每个处理器的处理器跟踪信息包括处理器标识和相干指示符，其指示选择性共享存储器事务。为每个处理器生成一致性管理器跟踪信息。每个处理器的相干管理器跟踪信息包括跟踪量度和一致性指标。

37. 发明申请

US20090249045A1 APPARATUS AND METHOD FOR CONDENSING TRACE INFORMATION IN A MULTI-PROCESSOR SYSTEM 有权
标题翻译：用于在多处理器系统中冷凝跟踪信息的装置和方法
公开(公告)号：US20090249045A1
公开(公告)日：2009-10-01
申请号：US12060204
申请日：2008-03-31
申请人： Thomas Benjamin BERG , Ryan C. KINTER , Jaidev Prasad PATWARDHAN , Radhika THEKKATH
发明人： Thomas Benjamin BERG , Ryan C. KINTER , Jaidev Prasad PATWARDHAN , Radhika THEKKATH
IPC分类号： G06F9/30
CPC分类号： G06F11/3636 , G06F12/0815
摘要： A computer readable storage medium includes executable instructions to characterize a coherency controller. The executable instructions define ports to receive processor trace information from a set of processors. The processor trace information from each processor includes a processor identity and a condensed coherence indicator. Circuitry produces a trace stream with trace metrics and condensed coherence indicators.
摘要翻译：计算机可读存储介质包括用于表征一致性控制器的可执行指令。可执行指令定义从一组处理器接收处理器跟踪信息的端口。来自每个处理器的处理器跟踪信息包括处理器标识和缩合相干指示符。电路产生具有跟踪量度和浓缩相干指标的跟踪流。

38. 发明申请

US20090198986A1 Configurable Instruction Sequence Generation 有权
标题翻译：可配置指令序列生成
公开(公告)号：US20090198986A1
公开(公告)日：2009-08-06
申请号：US12399330
申请日：2009-03-06
申请人： Kevin D. Kissell
发明人： Kevin D. Kissell
IPC分类号： G06F9/30
CPC分类号： G06F9/3017 , G06F9/30167 , G06F9/30181
摘要： A configurable instruction set architecture is provided whereby a single virtual instruction may be used to generate a sequence of instructions. Dynamic parameter substitution may be used to substitute parameters specified by a virtual instruction into instructions within a virtual instruction sequence.
摘要翻译：提供了可配置的指令集架构，由此可以使用单个虚拟指令来生成指令序列。动态参数替换可用于将由虚拟指令指定的参数替换为虚拟指令序列内的指令。

39. 发明授权

US07562191B2 Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme 有权
标题翻译：具有省电指令高速缓存方式预测器和指令替换方案的微处理器
公开(公告)号：US07562191B2
公开(公告)日：2009-07-14
申请号：US11272719
申请日：2005-11-15
申请人： Matthias Knoth
发明人： Matthias Knoth
IPC分类号： G06F12/12
CPC分类号： G06F12/0864 , G06F9/3802 , G06F12/123 , G06F2212/1028 , G06F2212/6082 , Y02D10/13
摘要： Microprocessor having a power-saving instruction cache way predictor and instruction replacement scheme. In one embodiment, the processor includes a multi-way set associative cache, a way predictor, a policy counter, and a cache refill circuit. The policy counter provides a signal to the way predictor that determines whether the way predictor operates in a first mode or a second mode. Following a cache miss, the cache refill circuit selects a way of the cache and compares a layer number associated with a dataram field of the way to a way set layer number. The cache refill circuit writes a block of data to the field if the layer number is not equal to the way set layer number. If the layer number is equal to the way set layer number, the cache refill circuit repeats the above steps for additional ways until the block of memory is written to the cache.
摘要翻译：具有省电指令高速缓存方式预测器和指令替换方案的微处理器。在一个实施例中，处理器包括多路组相关高速缓存，方式预测器，策略计数器和高速缓存补充电路。策略计数器向预测器提供一种信号，该方式确定预测器在第一模式或第二模式下的运行方式。在缓存未命中之后，高速缓存补充电路选择高速缓存的方式，并将与方式的数据字段相关联的层号与设置层号的方式进行比较。如果层号不等于设置层号的方式，则缓存补充电路将数据块写入字段。如果层号等于设置层号码，则高速缓存补充电路重复上述步骤以获得额外的方式，直到存储器块被写入高速缓存。

40. 发明授权

US07551626B2 Queueing system for processors in packet routing operations 有权
标题翻译：分组路由操作中处理器的排队系统
公开(公告)号：US07551626B2
公开(公告)日：2009-06-23
申请号：US11360338
申请日：2006-02-23
申请人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
发明人： Mario Nemirovsky , Enric Musoll , Stephen Melvin , Narendra Sankar , Nandakumar Sampath , Adolfo Nemirovsky
IPC分类号： H04L12/56 , G06F3/00 , G06F13/00
CPC分类号： G06F9/546 , H04L47/2441 , H04L47/32 , H04L47/621 , H04L47/6215 , H04L49/201 , H04L49/205 , H04L49/90 , H04L49/901 , H04L49/9073
摘要： In a data-packet processor, a configurable queueing system for packet accounting during processing has a plurality of queues arranged in one or more clusters, an identification mechanism for creating a packet identifier for arriving packets, insertion logic for inserting packet identifiers into queues and for determining into which queue to insert a packet identifier, and selection logic for selecting packet identifiers from queues to initiate processing of identified packets, downloading of completed packets, or for requeueing of the selected packet identifiers.
摘要翻译：在数据包处理器中，用于处理期间的分组计费的可配置排队系统具有排列在一个或多个集群中的多个队列，用于创建用于到达分组的分组标识符的识别机制，用于将分组标识符插入到队列中的插入逻辑确定插入分组标识符到哪个队列，以及用于从队列中选择分组标识符以启动已识别分组的处理，完成的分组的下载或用于重新选择所选分组标识符的选择逻辑。

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