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21. 发明授权

US4815032A Portable electronic memorandum device with password accessible memory 失效
标题翻译：便携式电子备忘录设备，密码可访问存储器
公开(公告)号：US4815032A
公开(公告)日：1989-03-21
申请号：US867244
申请日：1986-05-23
申请人： Hiroshi Fujii
发明人： Hiroshi Fujii
IPC分类号： G06F12/14 , G06F15/02 , G06F21/00 , G06F21/24 , G06F7/28 , G06F15/40
CPC分类号： G06F21/78 , G06F15/0283 , G06F21/31 , G06F21/79 , G06F2221/2105
摘要： A portable electronic memorandum device is placed in the password set mode by operating switch Sl. In this mode, if the correct password is set, the secret mode is set up and the secret data is displayed. If user forgets the password, switch Sc is operated in the error display mode. By this operation, the password and the secret data are both cleared, so that secrecy of the secret data can be protected.
摘要翻译：通过操作开关S1将便携式电子备忘录设备置于密码设置模式。在此模式下，如果设置了正确的密码，则设置秘密模式，并显示秘密数据。如果用户忘记密码，则在错误显示模式下操作Sc。通过该操作，密码和秘密数据都被清除，从而可以保护秘密数据的秘密。

22. 发明授权

US4813010A Document processing using heading rules storage and retrieval system for generating documents with hierarchical logical architectures 失效
标题翻译：使用标题规则存储和检索系统的文档处理，用于生成具有分级逻辑架构的文档
公开(公告)号：US4813010A
公开(公告)日：1989-03-14
申请号：US897930
申请日：1986-08-19
申请人： Toshio Okamoto , Miwako Doi , Isamu Iwai
发明人： Toshio Okamoto , Miwako Doi , Isamu Iwai
IPC分类号： G06F17/21 , G06F17/27 , G06F17/30 , G06F3/14 , G06F7/28 , G06F13/00 , G06F15/18
CPC分类号： G06F17/2745
摘要： A document generating system which includes an input device for inputting document data, a heading candidate extraction section for extracting, as a heading candidate, the word corresponding to the heading stored in a heading dictionary from the document data input at the input section. A heading decision section is implemented in the system for checking the heading candiate, that was extracted by the heading candidate extraction section according to a heading rule stored in a heading rule dictionary and for deciding whether the heading candidate is a heading. Also, a document architecture decision section is implemented in the system for checking the heading decided by the heading decision section according to document architecture rules stored in a document architecture rule dictionary. The architecture decision section is for determining the heading as satisfying the document architecture rule as a true heading, and the heading not satisfying the document architecture rule as being false heading.

23. 发明授权

US4633393A Generic key for indexing and searching user data in a digital information storage and retrieval device 失效
标题翻译：用于在数字信息存储和检索设备中索引和搜索用户数据的通用密钥
公开(公告)号：US4633393A
公开(公告)日：1986-12-30
申请号：US544328
申请日：1983-10-21
申请人： John P. Rundell
发明人： John P. Rundell
IPC分类号： G06F12/00 , G06F17/30 , G06F7/28
CPC分类号： G06F17/30952 , Y10S707/99937
摘要： A generic key, for allowing a data use to efficiently search a set of user data recorded in blocks in an efficient method using a multiplicity of user keys. As user data blocks are built up for recording, the unique identifiers are placed in the header of the data block, recorded on the disk surface with the contents stored on the device and the platter index. The user can then sort and search the index based upon which of the multiplicity of user keys he selects.
摘要翻译：通用密钥，用于允许数据使用以有效的方法使用多个用户密钥来有效地搜索记录在块中的一组用户数据。当用户数据块被建立用于记录时，唯一标识符被放置在数据块的标题中，记录在磁盘表面上，其中存储在设备上的内容和盘片索引。然后，用户可以基于他选择的多个用户密钥中的哪一个对索引进行排序和搜索。

24. 发明授权

US4498141A High speed correlation circuit and method 失效
标题翻译：高速相关电路及方法
公开(公告)号：US4498141A
公开(公告)日：1985-02-05
申请号：US342257
申请日：1982-01-25
申请人： J. Carl Cooper
发明人： J. Carl Cooper
IPC分类号： G11B20/10 , G06F17/15 , G11B27/30 , H04L7/08 , G06F7/28
CPC分类号： G06F17/15 , G11B27/3072 , G11B2220/90
摘要： High speed serial data bits of a data stream are received, stored, shifted and compared in parallel to bit contents of a known correlation word. For each bit match a known signal change is provided on a common terminal. High speed current or voltage changes on the common terminal are proportional to the number of matching bits and are monitored to detect presence of the correlation word in the received data stream. The circuit has minimum number of components and built-in temperature compensation.
摘要翻译：接收，存储，移位和并行地比较数据流的高速串行数据位与已知相关字的位内容。对于每个比特匹配，在公共终端上提供已知的信号改变。公共端子上的高速电流或电压变化与匹配位数成比例，并且被监视以检测接收到的数据流中相关字的存在。该电路具有最少数量的组件和内置的温度补偿。

25. 发明授权

US4415984A Synchronous clock regenerator for binary serial data signals 失效
标题翻译：用于二进制串行数据信号的同步时钟再生器
公开(公告)号：US4415984A
公开(公告)日：1983-11-15
申请号：US162806
申请日：1980-06-25
申请人： Dana A. Gryger , Daniel P. Drogichen
发明人： Dana A. Gryger , Daniel P. Drogichen
IPC分类号： H04L7/00 , H04L7/033 , H04L7/04 , G06F7/28 , G06F5/06
CPC分类号： H04L7/0338 , H04L7/0083 , H04L7/044
摘要： Disclosed is a synchronous clock regenerator for generating a clock signal which can be reliably used to strobe a binary serial data signal. The incoming raw clock signal is fed into a tapped delay line which generates multiple delayed versions of the raw clock signal. Upon detection of a framing transition on the incoming data signal, the raw clock signal and multiple delayed clock signals are latched. The latched values are used to address a read only memory (ROM), the ROM containing codes specifying which, if any, of the set including the raw clock signal and multiple delayed clock signals provides the optimum phase to strobe the incoming data signal. The code read from the ROM is decoded, latched and fed to a l-of-n selector circuit. Thereafter, and until the next framing transition occurs, each raw clock pulse received is replaced by the corresponding one of the set of that raw clock pulse and the generated delayed versions of that raw clock pulse as selected by the previously latched inputs to the l-of-n selector.
摘要翻译：公开了一种用于产生可靠地用于选通二进制串行数据信号的时钟信号的同步时钟再生器。输入的原始时钟信号被馈送到产生原始时钟信号的多个延迟版本的抽头延迟线。在检测到输入数据信号上的成帧转换时，原始时钟信号和多个延迟的时钟信号被锁存。锁存的值用于寻址只读存储器（ROM），ROM包含指定包括原始时钟信号和多个延迟时钟信号的集合（如果有的话）的代码提供了选通输入数据信号的最佳相位。从ROM读取的代码被解码，锁存并馈送到n位选择器电路。此后，直到下一个成帧转换发生，接收到的每个原始时钟脉冲被该原始时钟脉冲的一组中的相应一个所代替，并且该原始时钟脉冲的生成的延迟版本被先前锁存的输入选择为1- 的n选择器。

26. 发明授权

US4222101A Arrangement for branching an information flow 失效
标题翻译：分支信息流的排列
公开(公告)号：US4222101A
公开(公告)日：1980-09-09
申请号：US892494
申请日：1978-04-03
申请人： Oleg Avsan , Nils K. Isaksson
发明人： Oleg Avsan , Nils K. Isaksson
IPC分类号： G06F9/22 , G06F9/28 , G06F9/32 , G06F9/38 , G06F13/00 , G06F7/28
CPC分类号： G06F9/28
摘要： Digital words of a pipelined incoming information flow are branched into a number of outgoing information flow branches. The term "pipelined" means that the flow is transferred through memory means whose activation inputs are controlled by clock pulses, the memory means arranged successively with reference to the flow direction being coincidently activated to receive successive words of the flow. A digital branching information flow for ordering into which of the outgoing branches the incoming words have to be branched is generated in step with the incoming flow. The basis for each outgoing branch is obtained from the output of a branching register to which the incoming flow is supplied. The branching registers are activated by the clock pulses, but if an outgoing branch contains only a part of the incoming flow, an activation locking device is used in order to block the clock pulses in dependence on the respective branching information. The branching information flow may be transferred to the locking devices through branching information registers whose activation inputs may also be controlled by locking devices. A branching information register is, however, not to be controlled by the locking device connected to its own output.
摘要翻译：流水线传入信息流的数字字被分支为多个输出信息流分支。术语“流水线”是指通过存储装置传送流程，其存储装置的激活输入由时钟脉冲控制，存储器装置相对于流动方向被连续排列，被一致地激活以接收流的连续字。一个数字分支信息流，用于排序输入分支中的哪一个输入字必须被分支，与进入流一起生成。每个输出分支的基础是从提供输入流的分支寄存器的输出获得的。分支寄存器被时钟脉冲激活，但是如果输出分支仅包含输入流的一部分，则使用激活锁定装置，以便根据相应的分支信息来阻塞时钟脉冲。分支信息流可以通过分支信息寄存器传送到锁定装置，其激活输入也可以由锁定装置控制。但是，分支信息寄存器不受连接到其自身输出的锁定装置的控制。

27. 发明授权

US4125868A Typesetting terminal apparatus having searching and merging features 失效
标题翻译：排版终端设备具有搜索和合并特征
公开(公告)号：US4125868A
公开(公告)日：1978-11-14
申请号：US626075
申请日：1975-10-28
申请人： John F. Hruby , Rex McCleary , Jerome M. O'Hogan , Nathan H. Searle
发明人： John F. Hruby , Rex McCleary , Jerome M. O'Hogan , Nathan H. Searle
IPC分类号： B41B25/00 , B41B27/02 , G06F7/36 , G06F7/28 , G06F15/40 , G11B27/02
CPC分类号： B41B27/02 , B41B25/00
摘要： A typesetting terminal adapted for operating a photo typesetter includes a data processor with a plurality of peripheral devices coupled thereto, such as a keyboard, cathode ray tube display, cursor control and a plurality of tape transports. Information from the keyboard and selected tape transports is read into the data processor memory for access and display by the cathode ray tube and outputting to a further tape device. Desired information can be searched in the various input tapes for display, editing and combination with information derived from another input.
摘要翻译：适于操作照片排版机的排版终端包括具有耦合到其上的多个外围设备的数据处理器，诸如键盘，阴极射线管显示器，光标控制和多个磁带传输。来自键盘和所选磁带传输的信息被读入数据处理器存储器，以便由阴极射线管进行访问和显示，并输出到另一个磁带设备。可以在各种输入磁带中搜索所需的信息以进行显示，编辑和与从另一个输入导出的信息的组合。

28. 发明授权

US4099242A One-pass general associative search processor 失效
标题翻译：单程通用关联搜索处理器
公开(公告)号：US4099242A
公开(公告)日：1978-07-04
申请号：US738392
申请日：1976-11-03
申请人： George B. Houston , Roger H. Simonsen
发明人： George B. Houston , Roger H. Simonsen
IPC分类号： G06F17/30 , G06F7/28 , G06F7/34 , G11C15/00
CPC分类号： G06F17/30985 , Y10S707/99932
摘要： An apparatus for searching stored data in accordance wit a search specification established by a digital computer. The data is stored in data tracks which form the storing medium on a memory device. The data is in the form of logical records, each record comprising a number of data fields. The search specification designates one or more of the data fields as range fields and may designate one field as a value field. The search specification also includes range field values and range field operators for each designated range field, and a value field operator for the designated value field. The apparatus includes a first processor, which comprises a variable number of first subprocessors equal to the number of data tracks simultaneously applied to the input of the apparatus. Each first subprocessor is operative to apply the range field values and operators against the designated range fields, and may also apply them against the designated value field, of each successive record in a data track. This process is referred to as range testing and results in the identification of those logical records which satisfy all the range tests. The designated value field is recognized during range testing and its content is stored. A second processor applies the value operator against the designated value field previously recognized and stored during range testing, and determines which value field, and hence which record, best satisfies the value test among those presented simultaneously at its input. The results of the second processor are then used to update the indication of the one record best satisfying both the range and value tests of all the records previously presented to the apparatus.
摘要翻译：一种用于根据由数字计算机建立的搜索规范搜索存储的数据的装置。将数据存储在形成存储介质的数据轨道上。数据是逻辑记录的形式，每个记录包括多个数据字段。搜索规范将一个或多个数据字段指定为范围字段，并且可以将一个字段指定为值字段。搜索规范还包括每个指定范围字段的范围字段值和范围字段操作符，以及指定值字段的值字段操作符。该装置包括第一处理器，其包括等于同时施加到装置的输入的数据轨道的数量的可变数量的第一子处理器。每个第一子处理器可操作以针对指定范围字段应用范围字段值和操作符，并且也可以将它们应用于数据轨道中每个连续记录的指定值字段。该过程被称为范围测试，并导致满足所有范围测试的逻辑记录的识别。在范围测试期间识别指定值字段，并存储其内容。第二个处理器在范围测试期间将值操作符应用于先前识别和存储的指定值字段，并确定哪个值字段以及因此哪个记录在其输入端同时呈现的那些记录中最符合值测试。然后，第二处理器的结果用于更新一个记录的指示，该记录最好地满足先前提供给设备的所有记录的范围和值测试。

29. 发明授权

US4034348A Apparatus, including delay means, for sampling and recovering data recorded by the double transition recording technique 失效
标题翻译：包括延迟装置的装置，用于采样和恢复由双重转变记录技术记录的数据
公开(公告)号：US4034348A
公开(公告)日：1977-07-05
申请号：US700276
申请日：1976-06-28
申请人： Donald J. Rathbun
发明人： Donald J. Rathbun
IPC分类号： H03M5/12 , G11B20/14 , H04L25/49 , G06F7/28 , H03K5/00
CPC分类号： G11B20/1419
摘要： Data and clock bits are sampled by use of two delay means such as shift registers which are enabled at a clock rate which is set so that a first such delay means coupled to receive the bits includes no more than one bit therein at any time. The receipt of a bit substantially at the midway point of the second delay means, which is coupled serially to receive bits from the first delay means, causes a sampling signal to be generated in response to which a determination is made as to whether another bit has been received by the first delay means. Further logic is provided to recover the data bits.
摘要翻译：通过使用诸如移位寄存器的两个延迟装置对数据和时钟位进行采样，时钟速率被设置为使得耦合到接收位的第一这样的延迟装置在任何时间都不超过一位。基本上在第二延迟装置的中点处接收一个位，其被串行耦合以从第一延迟装置接收位，导致产生采样信号，响应于此，确定另一位是否具有被第一个延迟手段所接收。提供进一步的逻辑来恢复数据位。

30. 发明授权

US3900834A Memory update apparatus utilizing chain addressing 失效
标题翻译：记忆更新装置利用链条寻址
公开(公告)号：US3900834A
公开(公告)日：1975-08-19
申请号：US28657572
申请日：1972-09-05
申请人： BUNKER RAMO
发明人： CASEY RICHARD C , DUGGAN ROBERT J , GROSKY STEPHEN A , JEN DIXSON TEH-CHAO , SERRA JOHN J , WHITEHEAD DONALD SHAFFER , BOYCE THOMAS E
IPC分类号： G06F12/00 , G06F17/30 , G06Q40/04 , G06F7/28 , G06F13/00 , G06F15/40
CPC分类号： G06Q40/04 , G06F17/30345
摘要： This invention relates to a system in which a control computer supplies rapidly changing information concerning a large plurality of data items to a plurality of programmable control units for updating information contained in the memory of each unit. Each programmable control unit memory may contain information relating to a plurality of different items and information relating to a given item may be stored in a number of different locations within the memory, there being no predetermined relationship between these locations. The control computer sends a like update message to the programmable control units for updating of information relating to a particular item at all locations in each programmable control unit memory at which it appears. This is effected by use of a common address table provided in each memory, which table has an entry for each of the item storing locations in the memory. Each entry in the table contains the address of the corresponding item-storing memory location and a chain address to another entry in the table for a location at which information relating to the same item is stored. An update message relating to a given item contains information permitting a first entry in the table for the given item to be accessed. The address in the accessed entry is utilized to route the information in the message to a location in memory which is to be updated while the chain address in the accessed entry is utilized to access the table entry for another memory location containing information relating to the item. Succeeding table entries in the chain are utilized to control memory updates until all memory locations containing information relating to the item have been updated. Where the update message contains more than one field of information, the above-described procedure may be repeated for each received field. The table may also contain an indication of the type of information stored for the item at each memory location and this information-type indication may be utilized to determine whether information in a given input field is to be utilized for updati;ng information at a given location for the item, and, in some instances, to control the updating. The system also provides a capability for changing the items concerning which information is stored at a given location. When this occurs, appropriate changes are made in the table entries for the memory location and the chains for the items involved are modified.

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