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21. 发明申请

US20090218124A1 METHOD OF FILLING VIAS WITH FUSIBLE METAL 审中-公开
标题翻译：用可熔金属填充VIAS的方法
公开(公告)号：US20090218124A1
公开(公告)日：2009-09-03
申请号：US12038891
申请日：2008-02-28
申请人： JAROSLAW A. MAGERA , BRUCE C. DEEMER
发明人： JAROSLAW A. MAGERA , BRUCE C. DEEMER
IPC分类号： H05K1/00 , H05K3/42
CPC分类号： H05K3/421 , H05K1/0366 , H05K3/062 , H05K3/064 , H05K3/108 , H05K3/3436 , H05K3/3473 , H05K2201/09472 , H05K2201/09481 , H05K2201/09509 , H05K2201/09572 , H05K2203/0361 , H05K2203/043 , H05K2203/1394 , Y02P70/613 , Y10T29/49165
摘要： A method is disclosed in which a blind via in a PCB is filled. The vias are plated with a conductor and then with a fusible metal of lower melting point than the conductor. The plated vias are covered with a photoresist and the fusible metal is removed at locations on the PCB other than where the photoresist is disposed. The photoresist is removed and flux is provided on the PCB before the PCB is heated. The heated fusible metal flows into the via.
摘要翻译：公开了一种填充PCB中的盲通孔的方法。通孔用导体电镀，然后与导体熔点低的易熔金属电镀。电镀通孔用光致抗蚀剂覆盖，并且在PCB上的位置处除去可熔金属，而不是设置光致抗蚀剂。在PCB加热之前，去除光致抗蚀剂并在PCB上提供焊剂。加热的可熔金属流入通孔。

22. 发明申请

US20080217047A1 CIRCUIT BOARD SURFACE STRUCTURE 有权
标题翻译：电路板表面结构
公开(公告)号：US20080217047A1
公开(公告)日：2008-09-11
申请号：US12043689
申请日：2008-03-06
申请人： Wen-Hung Hu
发明人： Wen-Hung Hu
IPC分类号： H05K1/09 , H05K1/00 , H05K1/11
CPC分类号： H05K3/3452 , H01L23/49811 , H01L2224/05001 , H01L2224/05022 , H01L2224/05111 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05171 , H01L2224/05572 , H01L2224/05601 , H01L2224/05605 , H01L2224/05609 , H01L2224/05611 , H01L2224/05613 , H01L2224/05616 , H01L2224/05618 , H01L2224/0562 , H01L2224/05623 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/0567 , H01L2224/05671 , H01L2224/16 , H01L2924/01079 , H05K3/0023 , H05K3/243 , H05K3/28 , H05K3/3473 , H05K2203/054 , H05K2203/0594 , H01L2924/00014 , H01L2924/01024 , H01L2924/01082 , H01L2924/013
摘要： A circuit board surface structure includes a circuit board having at least one surface provided with a plurality of electrically connecting pads, an insulating protective layer characterized by photosensitivity and solder resisting and formed on the circuit board, and a plurality of openings formed in the insulating protective layer to expose the electrical connecting pads on the circuit board and tapered upward; and a conductive element formed in the opening, so as to increase the contact area and reinforce bonding between the electrically connecting pads and the conductive element.
摘要翻译：电路板表面结构包括具有设置有多个电连接焊盘的至少一个表面的电路板，形成在电路板上的光敏性和阻焊性特征的绝缘保护层，以及形成在绝缘保护层中的多个开口以暴露电路板上的电连接焊盘并向上锥形; 以及形成在开口中的导电元件，以便增加接触面积并加强电连接焊盘和导电元件之间的接合。

23. 发明申请

US20080188040A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20080188040A1
公开(公告)日：2008-08-07
申请号：US12021664
申请日：2008-01-29
申请人： Takashi Ozawa , Seiji Sato , Masao Nakazawa , Mitsuyoshi Imai , Masatoshi Nakamura , Kei Imafuji
发明人： Takashi Ozawa , Seiji Sato , Masao Nakazawa , Mitsuyoshi Imai , Masatoshi Nakamura , Kei Imafuji
IPC分类号： H01L21/60
CPC分类号： H01L24/32 , H01L21/4853 , H01L21/563 , H01L24/16 , H01L24/81 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/1146 , H01L2224/13099 , H01L2224/16225 , H01L2224/16235 , H01L2224/27013 , H01L2224/29111 , H01L2224/2919 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/81026 , H01L2224/81191 , H01L2224/8121 , H01L2224/814 , H01L2224/81815 , H01L2224/83051 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/14 , H01L2924/15311 , H01L2924/1579 , H05K3/3436 , H05K3/3473 , H05K2201/10674 , H05K2203/043 , H05K2203/0475 , Y02P70/613 , H01L2924/00012 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A solder 14 is formed, by a plating method, on a connecting surface 21A and a side surface 21B in a connecting pad 21 of a wiring board 11 which is opposed to a metal bump 13 formed on an electrode pad 31 of a semiconductor chip 12, and subsequently, the solder 14 is molten to form an accumulated solder 15 taking a convex shape on the connecting surface 21A of the connecting pad 21 and the metal bump 13 is then mounted on the connecting surface 21A of the connecting pad 21 on which the accumulated solder is formed, and the accumulated solder 15 and the metal bump 13 are thus bonded to each other.
摘要翻译：在布线基板11的与半导体芯片12的电极焊盘31上形成的金属凸块13相对的连接焊盘21的连接面21A和侧面21B上，通过电镀法形成焊锡14 随后，焊料14熔化，形成在连接焊盘21的连接面21A上呈凸形的积聚焊料15，然后将金属凸块13安装在连接焊盘21的连接面21A上，形成积累的焊料，并且积累的焊料15和金属凸块13因此彼此结合。

24. 发明授权

US07355288B2 Low fabrication cost, high performance, high reliability chip scale package 有权
标题翻译：低制造成本，高性能，高可靠性芯片级封装
公开(公告)号：US07355288B2
公开(公告)日：2008-04-08
申请号：US11120234
申请日：2005-05-02
申请人： Jin Yuan Lee , Ming Ta Lei , Ching-Cheng Huang , Chuen-Jye Lin
发明人： Jin Yuan Lee , Ming Ta Lei , Ching-Cheng Huang , Chuen-Jye Lin
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/12 , H01L21/563 , H01L21/565 , H01L23/3114 , H01L23/3128 , H01L23/525 , H01L24/11 , H01L24/16 , H01L24/48 , H01L2224/0231 , H01L2224/02311 , H01L2224/03912 , H01L2224/0401 , H01L2224/05599 , H01L2224/11462 , H01L2224/1147 , H01L2224/11831 , H01L2224/11849 , H01L2224/11901 , H01L2224/13023 , H01L2224/131 , H01L2224/45099 , H01L2224/48227 , H01L2224/73203 , H01L2224/85399 , H01L2924/00013 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01018 , H01L2924/01022 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/01041 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01084 , H01L2924/014 , H01L2924/04941 , H01L2924/09701 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/30105 , H01L2924/30107 , H01L2924/351 , H04B1/712 , H05K3/108 , H05K3/243 , H05K3/3473 , H05K2201/0367 , H05K2201/09436 , H05K2201/0949 , H05K2203/043 , H05K2203/054 , H01L2224/13099 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.
摘要翻译：本发明提供了一种新的方法和芯片级封装。本发明从提供接触点的基底开始，接触点通过在钝化层中形成的开口和聚合物或弹性体层暴露。形成屏障/种子层，产生第一光致抗蚀剂掩模，暴露阻挡层/籽晶层，其中该层覆盖在接触焊盘上，并与其邻接，在与接触焊盘相邻的表面区域上并且沿一个方向从接触垫电镀/种子层的暴露表面被电镀以产生互连迹线。从阻挡层/种子层的表面去除第一光致抗蚀剂掩模。产生限定焊料凸块的第二光致抗蚀剂掩模产生暴露与接触焊盘相邻并且在一个方向上从接触焊盘发出的势垒/种子层的表面积。根据第二光致抗蚀剂掩模产生焊料凸块，从阻挡层/种子层的表面去除第二光致抗蚀剂掩模，用覆盖在阻挡层/种子层上的金属电镀暴露电镀和阻挡层/籽晶层。根据由电镀形成的图案蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸点的回流。

25. 发明申请

US20080020602A1 Electrically Connecting Terminal Structure of Circuit Board and Manufacturing Method Thereof 有权
标题翻译：电路板的电气连接端子结构及其制造方法
公开(公告)号：US20080020602A1
公开(公告)日：2008-01-24
申请号：US11781086
申请日：2007-07-20
申请人： Chao-Wen SHIH
发明人： Chao-Wen SHIH
IPC分类号： H05K1/00
CPC分类号： H05K3/3473 , H05K3/244 , H05K2201/094 , H05K2201/09436 , H05K2201/09563 , H05K2201/0989 , H05K2203/043 , H05K2203/054
摘要： An electrically connecting terminal structure of a circuit board and a manufacturing method thereof are disclosed. The method includes: providing a circuit board defined with first and second predetermined areas; forming the first electrically connecting pad in the first predetermined area and the second electrically connecting pad in a portion of the second predetermined area; forming an insulated protecting layer on the circuit board, forming openings on the insulated protecting layer for exposing the first and second electrically connecting pads and a pad-uncovered portion of the second predetermined area; forming a conductive layer on the insulated protecting layer and forming openings of the insulated protecting layer; forming a resist on the conductive layer, forming openings on the resist above the openings of the insulated protecting layer; and forming first and second metals in the openings above the first and second electrically connecting pads and the pad-uncovered portion of the second predetermined area.
摘要翻译：公开了一种电路板的电连接端子结构及其制造方法。该方法包括：提供限定有第一和第二预定区域的电路板; 在所述第二预定区域的一部分中形成所述第一预定区域中的所述第一电连接焊盘和所述第二电连接焊盘; 在所述电路板上形成绝缘保护层，在所述绝缘保护层上形成开口，用于暴露所述第一和第二电连接焊盘和所述第二预定区域的焊盘未覆盖部分; 在绝缘保护层上形成导电层，形成绝缘保护层的开口; 在导电层上形成抗蚀剂，在绝缘保护层的开口上方的抗蚀剂上形成开口; 以及在所述第一和第二电连接焊盘和所述第二预定区域的焊盘未覆盖部分之上的开口中形成第一和第二金属。

26. 发明申请

US20070232059A1 Multilayer interconnection substrate and method of manufacturing the same 有权
标题翻译：多层互连基板及其制造方法
公开(公告)号：US20070232059A1
公开(公告)日：2007-10-04
申请号：US11474453
申请日：2006-06-26
申请人： Tomoyuki Abe
发明人： Tomoyuki Abe
IPC分类号： H01L21/4763 , H01L23/48
CPC分类号： H05K3/4614 , H01L21/486 , H01L23/49822 , H01L23/49827 , H01L2924/0002 , H05K3/3473 , H05K3/4069 , H05K3/4617 , H05K3/462 , H05K2201/0215 , H05K2201/10378 , H01L2924/00
摘要： A multilayer interconnection substrate is disclosed that includes a multilayer interconnection layer having at least a first interconnection layer and a second interconnection layer stacked with an insulating layer provided therebetween, and a connection via configured to electrically connect the first interconnection layer and the second interconnection layer. The connection via includes an internal conductor and a metal film covering the internal conductor. The internal conductor is an aggregate of metal particles.
摘要翻译：公开了一种多层互连衬底，其包括具有至少第一互连层和层叠有设置在其间的绝缘层的第二互连层的多层互连层，以及经配置以电连接第一互连层和第二互连层的连接通孔。连接通孔包括内部导体和覆盖内部导体的金属膜。内部导体是金属颗粒的聚集体。

27. 发明授权

US07273540B2 Tin-silver-copper plating solution, plating film containing the same, and method for forming the plating film 有权
标题翻译：锡 - 银 - 铜电镀溶液，含有它们的镀膜和形成电镀膜的方法
公开(公告)号：US07273540B2
公开(公告)日：2007-09-25
申请号：US11039841
申请日：2005-01-24
申请人： Hiromi Sonoda , Katsuji Nakamura
发明人： Hiromi Sonoda , Katsuji Nakamura
IPC分类号： C25D3/58 , C25D3/60
CPC分类号： C25D21/18 , B23K35/262 , C25D3/60 , C25D5/003 , C25D5/18 , C25D17/002 , C25D17/10 , C25D17/16 , C25D21/06 , H01L23/49582 , H01L2924/0002 , H05K3/3463 , H05K3/3473 , H01L2924/00
摘要： An electrolytic plating method, including: preparing a plating solution including water which is a primary medium, a sulfonic acid, and tin, copper, and silver ions, and a complexing agent, concentrations of the sulfonic acid, and tin, copper, and silver ions being 0.5 to 5 mol/L, 0.21 to 2 mol/L, 0.002 to 0.02 mol/L, and 0.01 to 0.1 mol/L, respectively, a mole ratio of the silver-ion concentration to the copper-ion concentration being in a range of 4.5 to 5.58; and separating a solution around a soluble anode containing 90 percent or more of tin from the plating solution on a cathode side by a non-ionic micro-porous membrane having a pore diameter of 0.01 to 0.05 μm and a thickness of 5 to 100 μm.
摘要翻译：一种电解电镀方法，包括：制备包含主要介质，磺酸和锡，铜和银离子的水的电镀溶液和络合剂，磺酸和锡，铜和银的浓度离子分别为0.5〜5mol / L，0.21〜2mol / L，0.002〜0.02mol / L，0.01〜0.1mol / L，银离子浓度与铜离子浓度的摩尔比为范围为4.5至5.58; 并且通过孔径为0.01〜0.05μm，厚度为5〜100μm的非离子型微孔膜，在阴极侧从电镀液中含有90％以上的锡的可溶性阳极分离。

28. 发明授权

US07265044B2 Method for forming bump on electrode pad with use of double-layered film 有权
标题翻译：使用双层膜在电极焊盘上形成凸块的方法
公开(公告)号：US07265044B2
公开(公告)日：2007-09-04
申请号：US10524510
申请日：2003-08-21
申请人： Masaru Ohta , Katsumi Inomata , Shinichiro Iwanaga
发明人： Masaru Ohta , Katsumi Inomata , Shinichiro Iwanaga
IPC分类号： H01L21/44
CPC分类号： H01L24/12 , H01L24/02 , H01L24/03 , H01L24/11 , H01L2224/0401 , H01L2224/0603 , H01L2224/06102 , H01L2224/10126 , H01L2224/1131 , H01L2224/11334 , H01L2224/1147 , H01L2224/11474 , H01L2224/13022 , H01L2224/13099 , H01L2224/13111 , H01L2224/13147 , H01L2224/1403 , H01L2224/16 , H01L2224/16235 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01007 , H01L2924/01009 , H01L2924/01011 , H01L2924/01012 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01023 , H01L2924/01024 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01041 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/04953 , H01L2924/14 , H01L2924/19042 , H05K3/28 , H05K3/3473 , H05K3/3478 , H05K3/3484 , H05K2201/09472 , H05K2201/09509 , H05K2203/041 , H05K2203/043 , H05K2203/0568 , H05K2203/0577 , H05K2203/0793
摘要： A process for forming bumps on electrode pads for a wiring board including a substrate and a plurality of electrode pads. The process (a) forms a laminated two-layer film on the wiring board and forms a pattern of apertures at positions corresponding to the electrode pads, the laminated two-layer film including a lower layer containing an alkali-soluble radiation-nonsensitive resin composition and an upper layer containing a negative radiation-sensitive resin composition; (b) fills a low-melting metal in the aperture pattern; (c) reflows the low-melting metal by pressing or heating to form bumps; and (d) peels and removes the laminated two-layer film from the board. The laminated film including two layers with different properties permits high resolution and easy peeling.
摘要翻译：一种用于在包括基板和多个电极焊盘的布线板的电极焊盘上形成凸块的工艺。方法（a）在布线板上形成叠层的双层膜，并在对应于电极焊盘的位置处形成孔的图案，层压的双层膜包括含有碱溶性辐射不敏感树脂组合物的下层和含有负辐射敏感性树脂组合物的上层; （b）填充孔径图案中的低熔点金属; （c）通过按压或加热来回流低熔点金属以形成凸块; 和（d）从板剥离并除去层压的二层膜。包括具有不同性质的两层的层压膜允许高分辨率和易剥离。

29. 发明申请

US20070158204A1 TIN AND TIN ALLOY ELECTROPLATING METHOD WITH CONTROLLED INTERNAL STRESS AND GRAIN SIZE OF THE RESULTING DEPOSIT 有权
标题翻译：具有控制内部应力和结晶沉积物粒度的锡合金电镀方法
公开(公告)号：US20070158204A1
公开(公告)日：2007-07-12
申请号：US11620079
申请日：2007-01-05
申请人： E. Jennings Taylor , Jenny J. Sun
发明人： E. Jennings Taylor , Jenny J. Sun
IPC分类号： C25D3/56 , C25D3/30
CPC分类号： C25D5/18 , C25D3/30 , C25D3/32 , C25D3/60 , H05K3/3473 , H05K2203/1492
摘要： A method for electrochemically plating tin or tin alloy onto a workpiece to provide a tin or tin alloy deposit on said workpiece having a stress differential and workpieces characterized by a tin or tin alloy deposit having a stress differential.
摘要翻译：一种将锡或锡合金电化学镀在工件上以在具有应力差的工件上提供锡或锡合金沉积物的方法，其特征在于具有应力差的锡或锡合金沉积物。

30. 发明授权

US07216424B2 Method for fabricating electrical connections of circuit board 有权
标题翻译：电路板电气连接方法
公开(公告)号：US07216424B2
公开(公告)日：2007-05-15
申请号：US11023363
申请日：2004-12-29
申请人： Ying-Tung Wang
发明人： Ying-Tung Wang
IPC分类号： H05K3/02 , H05K3/06 , H05K3/40
CPC分类号： H05K3/3473 , B23K35/02 , H05K3/0035 , H05K3/243 , H05K2201/0391 , H05K2201/09736 , H05K2203/043 , H05K2203/0505 , H05K2203/054 , H05K2203/0723 , Y10T29/49149 , Y10T29/49155 , Y10T29/49156 , Y10T29/49162 , Y10T29/49165 , Y10T29/49204
摘要： A method for fabricating electrical connections of a circuit board is provided. The circuit board has a plurality of electrical connection pads thereon. A protective layer is applied on the circuit board and has a plurality of openings for exposing the electrical connection pads. A conductive layer is formed on the protective layer and the electrical connection pads. A resist layer is applied on the conductive layer and has a set of openings for exposing a portion of the conductive layer covering some of the electrical connection pads. A first metal layer is electroplated in the openings of the resist layer. Another set of openings are formed through the resist layer corresponding to the rest of the electrical connection pads. A second metal layer is electroplated on the first metal layer and above the rest of the electrical connection pads to form different electrical connections on the circuit board.
摘要翻译：提供一种用于制造电路板的电连接的方法。电路板上有多个电连接焊盘。保护层被施加在电路板上，并且具有用于暴露电连接焊盘的多个开口。在保护层和电连接焊盘上形成导电层。将抗蚀剂层施加在导电层上并具有一组用于暴露覆盖一些电连接焊盘的导电层的一部分的开口。将第一金属层电镀在抗蚀剂层的开口中。通过与其余电连接焊盘对应的抗蚀剂层形成另一组开口。第二金属层电镀在第一金属层上并在电连接焊盘的其余部分上方，以在电路板上形成不同的电连接。

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