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21. 发明授权

US06257756B1 Apparatus and method for implementing viterbi butterflies 失效
标题翻译：维特比蝴蝶的装置和方法
公开(公告)号：US06257756B1
公开(公告)日：2001-07-10
申请号：US08895067
申请日：1997-07-16
申请人： Michael Zarubinsky , Yoram Salant , Natan Baron
发明人： Michael Zarubinsky , Yoram Salant , Natan Baron
IPC分类号： G06F1110
CPC分类号： H03M13/6502 , H03M13/3961 , H03M13/4107 , H03M13/4161 , H03M13/4184 , H03M13/6569
摘要： The Viterbi algorithm (20) is performed with a reduced number of calculations when the comparing step (C, 80, 50) is anticipated before the selecting (S, 62, 64, 66, 68) and adding steps (A, 74, 76). During comparing (C), selection decisions (e.g., D (i)) are obtained by analyzing pairs of old path metrics (e.g., P (2i, j−1) at 91, P (2i+1, j−1) at 92) by subtracting and multiplying the path metrics with branch metrics (e.g., B (i, j) at 95) and combining intermediate sign (e.g., SP, SB, S&Dgr;) by e.g., and-logic (50). Selecting decisions (e.g., D (i/2, j+1), D (i/2+N/2, j+1) and new path metrics (e.g., P (i, j), P (i+12, j) are continuously stored and updated.
摘要翻译：当在选择（S，62,64,66,68）之前预期比较步骤（C，80,50）和添加步骤（A，74,76）时，执行维特比算法（20），减少计算次数）。在比较（C）期间，通过分析旧路径度量对（例如，在91处的P（2i，j-1），P（2i + 1，j-1）处的选择决策（例如，D（i）通过将路径度量与分支度量（例如，95处的B（i，j））相减并乘法，并通过例如逻辑（50）组合中间符号（例如，SP，SB，SDELTA）选择决策（例如，D（i / 2，j + 1），D（i / 2 + N / 2，j + 1）和新路径量度（例如，P（i，j） j）被连续存储和更新。

22. 发明授权

US6154870A Signal error-correction system and method 失效
标题翻译：信号纠错系统及方法
公开(公告)号：US6154870A
公开(公告)日：2000-11-28
申请号：US89874
申请日：1998-06-04
申请人： Lisa Fredrickson , Reza M. Dehmohseni
发明人： Lisa Fredrickson , Reza M. Dehmohseni
IPC分类号： G11B20/10 , H03M13/25 , H03M13/41 , H03M13/03
CPC分类号： G11B20/10064 , G11B20/10009 , G11B20/10074 , H03M13/256 , H03M13/41 , H03M13/4161 , H03M13/6343 , H03M13/6505
摘要： A Viterbi PRML system and method providing a new code with distance properties such that some tribits are allowed but no longer sequences are allowed. A code rate 8/ 9 is constructed for EPR4 and E.sup.2 PR4 channels and the system independently maps 8-bit blocks of user data to 9-bit channel sequences. The precoder has transfer function, f(D)=1/(1.sym.D), and produces a binary channel input x(D), which is fed to a coder, to provide an output signal y(D), which is transmitted and corrupted by noise. The corrupted signal is received and fed to a Viterbi detector. The signal is decoded to produce an estimate of the 8-bit data bytes, as reconstructed to be freed from noise corruption. The encoding protocol of the invention is implemented in the encoder. The protocol is: no sequence of 4 consecutive transitions occurs in any 9-bit codeword; no 9-bit codeword ends with a sequence of 2 or more consecutive transitions; no 9-bit codeword begins with more than 2 consecutive transitions; and sequences of 3 consecutive transitions, if any, begin only on a 2nd, 4th, 6th, or 9th bit of said 9-bit codeword. The protocol is preferably augmented by an additional constraint: no 9-bit codeword has the same 1st, 3rd, 5th, 7th, and 9th bit. Other limitations on coding are described to enhance the performance of the system.
摘要翻译：维特比PRML系统和方法提供具有距离属性的新代码，使得允许一些三进制但不允许序列。为EPR4和E2PR4通道构建码率8/9，系统将8位用户数据块独立地映射到9位通道序列。预编码器具有传递函数f（D）= 1 /（1（+）D），并产生馈送到编码器的二进制信道输入x（D），以提供输出信号y（D），其中被噪声传输和损坏。接收到损坏的信号并将其馈送到维特比检测器。对信号进行解码，以产生8位数据字节的估计，重建为免除噪声损坏。本发明的编码协议在编码器中实现。协议是：在任何9位码字中不发生4个连续转换序列; 没有9位码字以2个或更多个连续转换的序列结束; 没有9位码字以超过2个连续的转换开始; 并且如果有的话，3个连续转换的序列仅在所述9位码字的第2，第4，第6或第9位上开始。该协议优选地通过附加约束来增强：否9位码字具有相同的第1，第3，第5，第7和第9位。描述编码的其他限制，以增强系统的性能。

23. 发明授权

US09705531B2 Multi mode viterbi decoder 有权
公开(公告)号：US09705531B2
公开(公告)日：2017-07-11
申请号：US14624872
申请日：2015-02-18
申请人： eTopus Technology Inc.
发明人： Kai Keung Chan , Yu Kou , Tze Yin Cheung , Danfeng Xu
IPC分类号： H03M13/03 , H03M13/39 , H03M13/41 , H03M13/00
CPC分类号： H03M13/3961 , H03M13/4107 , H03M13/4161 , H03M13/6508
摘要： A multi-mode viterbi decoder supporting different decoding modes. The viterbi decoder comprises circuitry to output one or more data symbol values. The circuitry sets the one or more data symbol values to a first quantity of unit intervals in a first decoding mode (e.g. PAM-4). The circuitry sets the one or more data symbol values to a second quantity of unit intervals in a second decoding mode (e.g. NRZ). The second quantity of unit intervals is greater than the first quantity of unit intervals. A branch metric circuit is adapted to, in the first decoding mode, generate a set of viterbi branch metrics based on the data symbol values for the first quantity of unit intervals. The branch metric circuit is adapted to, in the second decoding mode, generate the set of viterbi branch metrics based on the data symbol values for the second quantity of unit intervals.

24. 发明授权

US08762824B2 Error pattern generation for trellis-based detection and/or decoding 有权
标题翻译：基于网格的检测和/或解码的错误模式生成
公开(公告)号：US08762824B2
公开(公告)日：2014-06-24
申请号：US12824517
申请日：2010-06-28
申请人： Shaohua Yang , Seo-How Low , Zining Wu , Gregory Burd
发明人： Shaohua Yang , Seo-How Low , Zining Wu , Gregory Burd
IPC分类号： H03M13/03 , H03M13/41 , H03M13/39
CPC分类号： H03M13/4192 , H03M13/098 , H03M13/3994 , H03M13/4138 , H03M13/4161 , H03M13/4169
摘要： The disclosed technology provides systems and methods for identifying potential error locations, patterns, and likelihood metrics in connection with trellis-based detection/decoding. In one aspect of the invention, the disclosed technology detects information that was previously encoded based on a trellis, and decodes the detected information based on the trellis to provide decoded information. The decoded information corresponds to a winning path through the trellis that ends at a winning state. The disclosed technology can identify one or more alternate paths through the trellis that also end at the winning state, and can generate a potential error pattern for each of the alternate paths.
摘要翻译：所公开的技术提供用于识别与基于网格的检测/解码相关的潜在错误位置，模式和似然度量的系统和方法。在本发明的一个方面，所公开的技术检测先前基于网格编码的信息，并且基于网格对检测到的信息进行解码以提供解码信息。解码的信息对应于通过在获胜状态结束的网格的获胜路径。所公开的技术可以识别通过网格的一个或多个备选路径，其也以胜利状态结束，并且可以为每个备选路径生成潜在的错误模式。

25. 发明授权

US08599959B2 Methods and apparatus for trellis-based modulation encoding 有权
标题翻译：用于网格调制编码的方法和装置
公开(公告)号：US08599959B2
公开(公告)日：2013-12-03
申请号：US12982129
申请日：2010-12-30
申请人： Victor Krachkovsky , Shaohua Yang , Erich F. Haratsch , Johnson Yen
发明人： Victor Krachkovsky , Shaohua Yang , Erich F. Haratsch , Johnson Yen
IPC分类号： H04L27/00
CPC分类号： H04L1/0059 , H03M5/145 , H03M13/256 , H03M13/31 , H03M13/3994 , H03M13/4161 , H03M13/6343 , H04L1/0042
摘要： Methods and apparatus are provided for trellis-based modulation encoding. A signal is modulation encoded by encoding one or more blocks of the signal using one or more corresponding edges in a trellis, wherein each edge in the trellis has a corresponding bit pattern; selecting a winning path through the trellis based on at least one transition-based run-length constraint; and generating an encoded sequence using edges associated with the winning path. Exemplary trellis pruning techniques are also provided. The winning path through the trellis is selected by minimizing one or more modulation metrics.
摘要翻译：为基于网格的调制编码提供了方法和装置。通过使用网格中的一个或多个相应边缘编码信号的一个或多个块来对信号进行调制，其中网格中的每个边缘具有对应的位模式; 基于至少一个基于过渡的游程长度约束来选择通过网格的获胜路径; 以及使用与获胜路径相关联的边缘生成编码序列。还提供了示例性网格修剪技术。通过最小化一个或多个调制度量来选择通过网格的获胜路径。

26. 发明授权

US08495480B2 Method and apparatus for signal-to-noise ratio estimation in convolutional codes (Viterbi) decoder 有权
标题翻译：卷积码（Viterbi）解码器中信噪比估计的方法和装置
公开(公告)号：US08495480B2
公开(公告)日：2013-07-23
申请号：US13110050
申请日：2011-05-18
申请人： Timur G. Kelin , Nikolay A. Vazhenin , Dmitry A. Pyatkov
发明人： Timur G. Kelin , Nikolay A. Vazhenin , Dmitry A. Pyatkov
IPC分类号： H03M13/03
CPC分类号： H03M13/4161 , H03M13/41 , H03M13/6337 , H04L1/0021 , H04L1/0054 , H04L1/20
摘要： A method of estimating signal-to-noise ratio in a Viterbi decoder comprising: setting a threshold SNR value; determining a dependence on SNR of the average decoding path length; filling branch metrics matrix, minimal path metrics matrix, path metrics matrix and paths matrix with initial values; receiving packets from a communication channel; calculating the matrices that contains paths stored during operation of Viterbi algorithm in its rows, and a minimal path metrics matrix, including calculating an estimate of a decoding path length, where all the paths converge, based on the paths matrix; calculating current SNR estimate using an estimate of a decoding path length, based on results of previous steps; setting a decoder control signal to an active state if the current estimated SNR does not exceed the threshold, and to an inactive state otherwise; if the decoder control signal is in active state, the branch metrics matrix, the minimal path metrics matrix, the paths metrics matrix and the paths matrix are filled with the initial values; generating a decoded symbol; and repeating the steps on a next packet if one is available.
摘要翻译：一种在维特比解码器中估计信噪比的方法，包括：设置阈值SNR值; 确定对平均解码路径长度的SNR的依赖性; 填充分支度量矩阵，最小路径度量矩阵，路径度量矩阵和具有初始值的路径矩阵; 从通信信道接收分组; 计算包含在维特比算法在其行中操作期间存储的路径的矩阵，以及最小路径量度矩阵，包括基于路径矩阵计算所有路径收敛的解码路径长度的估计; 基于先前步骤的结果，使用解码路径长度的估计来计算当前SNR估计; 如果当前估计的SNR不超过阈值，则将解码器控制信号设置为活动状态，否则设置为非活动状态; 如果解码器控制信号处于活动状态，则用初始值填充分支度量矩阵，最小路径度量矩阵，路径度量矩阵和路径矩阵; 生成解码符号; 并且如果可用的话，对下一个分组重复步骤。

27. 发明授权

US08301991B2 LDPC (low density parity check) coded modulation symbol decoding 有权
标题翻译： LDPC（低密度奇偶校验）编码调制符号解码
公开(公告)号：US08301991B2
公开(公告)日：2012-10-30
申请号：US12957238
申请日：2010-11-30
申请人： Ba-Zhong Shen , Hau Thien Tran , Kelly Brian Cameron
发明人： Ba-Zhong Shen , Hau Thien Tran , Kelly Brian Cameron
IPC分类号： G06F11/00
CPC分类号： H04L27/2602 , G11B20/1833 , H03M13/1111 , H03M13/1117 , H03M13/112 , H03M13/25 , H03M13/255 , H03M13/256 , H03M13/258 , H03M13/2957 , H03M13/4161 , H03M13/45 , H03M13/6516 , H03M13/6583 , H04L1/0041 , H04L1/005 , H04L1/0058 , H04L1/006 , H04L1/1671 , H04L27/18
摘要： LDPC (Low Density Parity Check) coded modulation symbol decoding. Symbol decoding is supported by appropriately modifying an LDPC tripartite graph to eliminate the bit nodes thereby generating an LDPC bipartite graph (such that symbol nodes are appropriately mapped directly to check nodes thereby obviating the bit nodes). The edges that communicatively couple the symbol nodes to the check nodes are labeled appropriately to support symbol decoding of the LDPC coded modulation signal. The iterative decoding processing may involve updating the check nodes as well as estimating the symbol sequence and updating the symbol nodes. In some embodiments, an alternative hybrid decoding approach may be performed such that a combination of bit level and symbol level decoding is performed. This LDPC symbol decoding out-performs bit decoding only. In addition, it provides comparable or better performance of bit decoding involving iterative updating of the associated metrics.
摘要翻译： LDPC（低密度奇偶校验）编码调制符号解码。通过适当地修改LDPC三部分图来消除比特节点从而生成LDPC二分图（使得符号节点被适当地映射到校验节点从而消除比特节点）来支持符号解码。将符号节点通信地耦合到校验节点的边缘被适当地标记以支持LDPC编码调制信号的符号解码。迭代解码处理可以包括更新校验节点以及估计符号序列和更新符号节点。在一些实施例中，可以执行替代的混合解码方法，使得执行位电平和符号电平解码的组合。该LDPC码解码仅执行比特解码。此外，它提供可比较或更好的比特解码性能，涉及相关度量的迭代更新。

28. 发明授权

US08230308B2 Decoding apparatus and decoding method using an additional add-compare-select operation on decoded data in the event of an error in the decoded data 失效
标题翻译：在解码数据发生错误的情况下，对解码数据使用附加加比较选择操作的解码装置和解码方法
公开(公告)号：US08230308B2
公开(公告)日：2012-07-24
申请号：US12342595
申请日：2008-12-23
申请人： Mitsunori Takanashi
发明人： Mitsunori Takanashi
IPC分类号： G06F11/00
CPC分类号： H03M13/413 , H03M13/09 , H03M13/3753 , H03M13/4161
摘要： The decoding apparatus includes an ACS unit to execute an add-compare-select operation on encoded received data, and an error detector to detect whether there is an error in decoded data calculated based on the executed add-compare-select operation, and if there is an error in the decoded data, the ACS unit additionally executes the add-compare-select operation on the received data.
摘要翻译：解码装置包括对编码的接收数据执行加法比较选择操作的ACS单元，以及检测是否存在基于执行的加法比较选择操作而计算的解码数据中的错误的错误检测器，如果存在是解码数据中的错误，ACS单元另外对接收到的数据执行加法比较选择操作。

29. 发明申请

US20120042228A1 BITWISE RELIABILITY INDICATORS FROM SURVIVOR BITS IN VITERBI DECODERS 有权
标题翻译： VITERBI解码器中的生存位置的可比性可靠性指标
公开(公告)号：US20120042228A1
公开(公告)日：2012-02-16
申请号：US12856143
申请日：2010-08-13
申请人： Andries Pieter Hekstra , Nur Engin
发明人： Andries Pieter Hekstra , Nur Engin
IPC分类号： H03M13/07 , G06F11/10 , G06F11/07
CPC分类号： H04L1/0054 , H03M13/09 , H03M13/2936 , H03M13/373 , H03M13/4138 , H03M13/4161 , H04L1/0059 , H04L1/0065
摘要： Various embodiments relate to the production of erasure flags to indicate errors resulting from decoding of convolutional codes. A Viterbi decoder may use a register exchange method to produce a plurality of survivor codes. At a defined index, a majority vote may take place comparing values of bits in each of the survivor codes. This majority vote may involve obtaining both the quantity of high-order bits and the quantity of low-order bits and obtaining the difference of the two quantities. The absolute value of the difference of high-order bits to low-order bits may be compared to a defined threshold. When the absolute value difference is below the defined quantity, an erasure flag may be produced and associated with the bits of the defined index, indicating that they are eligible for erasure. In some embodiments, a Reed-Solomon decoder may use the erasure flag to target specific survivor bits or survivor bytes for error-correction through erasure.
摘要翻译：各种实施例涉及擦除标志的产生，以指示由卷积码的解码产生的错误。维特比解码器可以使用寄存器交换方法来产生多个幸存代码。在定义的索引中，可以进行多数投票来比较每个幸存者代码中的比特值。这个多数投票可以涉及获得高阶位数量和低位数量，并获得两个数量的差。可以将高阶位与低位的差的绝对值与定义的阈值进行比较。当绝对值差低于定义的数量时，可以产生擦除标志并与定义的索引的位相关联，表示它们符合擦除条件。在一些实施例中，Reed-Solomon解码器可以使用擦除标志来针对特定的幸存者比特或幸存者字节来进行错误校正。

30. 发明授权

US07873881B2 Reconfigurable bit-manipulation node 有权
标题翻译：可重配置位操作节点
公开(公告)号：US07873881B2
公开(公告)日：2011-01-18
申请号：US11682696
申请日：2007-03-06
申请人： Brian Box , John M. Rudosky , Walter James Scheuermann
发明人： Brian Box , John M. Rudosky , Walter James Scheuermann
IPC分类号： G06F11/00
CPC分类号： H03M13/3922 , H03M7/40 , H03M13/00 , H03M13/09 , H03M13/15 , H03M13/2792 , H03M13/2957 , H03M13/3905 , H03M13/4107 , H03M13/4161 , H03M13/6508 , H03M13/6511 , H03M13/6513 , H03M13/6516 , H03M13/6519 , H03M13/6569
摘要： A reconfigurable bit-manipulation node is disclosed. The node includes an execution unit configured to perform a number of bit-oriented functions and a control unit configured to control the execution unit to allow one of the bit-oriented functions to be performed. The execution unit includes a number of elements interconnected with one another to allow the bit-oriented functions to be performed. The elements include a programmable butterfly unit, a number of non-programmable butterfly units, a number of data path elements, a look-up table memory, and a reorder memory. The execution unit is capable of engaging in one of a number of operating modes to perform the bit-oriented functions. The operating modes include a programmable mode and a number of fixed operating modes including Viterbi decoding, turbo decoding and variable length encoding and decoding. The data path elements include a programmable shifter and a programmable combiner.
摘要翻译：公开了可重新配置的位操作节点。节点包括被配置为执行多个位向功能的执行单元和被配置为控制执行单元以允许执行面向位功能之一的控制单元。执行单元包括彼此互连以允许执行面向位的功能的多个元件。元件包括可编程蝶形单元，多个不可编程蝶形单元，多个数据路径元件，查找表存储器和重排序存储器。执行单元能够参与多种操作模式之一来执行面向位的功能。操作模式包括可编程模式和多种固定操作模式，包括维特比解码，turbo解码和可变长度编码和解码。数据路径元件包括可编程移位器和可编程组合器。

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