专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US07259709B2 Pipeline A/D converter 有权
标题翻译：管道A / D转换器
公开(公告)号：US07259709B2
公开(公告)日：2007-08-21
申请号：US11140344
申请日：2005-05-27
申请人： Shinichi Ogita , Mitsuhiko Otani , Kouji Yamaguchi
发明人： Shinichi Ogita , Mitsuhiko Otani , Kouji Yamaguchi
IPC分类号： H03M1/12
CPC分类号： H03M1/007 , H03M1/167
摘要： The present invention provides a pipeline A/D converter having resolution, allowable conversion processing rate and power consumption satisfying the requests of a system incorporating the pipeline A/D converter.The pipeline A/D converter in accordance with the present invention comprises a control section for outputting a control signal according to the operation state of an apparatus incorporating the pipeline A/D converter, and a pipeline A/D conversion section, the resolution and/or allowable conversion processing rate of which are switched by switching the capacitance in a built-in operational amplifier according to the control signal.
摘要翻译：本发明提供一种具有分辨率，允许转换处理速率和功耗的流水线A / D转换器，其满足包含流水线A / D转换器的系统的要求。根据本发明的流水线A / D转换器包括：控制部分，用于根据包含流水线A / D转换器的装置的操作状态和流水线A / D转换部分输出控制信号，分辨率和/ 或允许的转换处理速率根据控制信号切换内置运算放大器中的电容。

22. 发明申请

US20070176818A1 Analog-to-digital converter 有权
标题翻译：模数转换器
公开(公告)号：US20070176818A1
公开(公告)日：2007-08-02
申请号：US11700130
申请日：2007-01-31
申请人： Shigeto Kobayashi
发明人： Shigeto Kobayashi
IPC分类号： H03M1/12
CPC分类号： H03M1/007 , H03M1/162 , H03M1/167
摘要： An A-D converter includes a group of resistors, a group of comparators, an encoder and an output unit. The output unit includes a correction circuit. An inverter constitutes the correction circuit. The encoder is shared in a case where the A-D converter converts an inputted analog signal to a two-bit binary code and a case where the A-D converter converts the inputted analog signal to a 4-bit binary code. The correction circuit corrects the output of the encoder when the A-D converter is to convert the inputted analog signal to the 2-bit binary code.
摘要翻译： A-D转换器包括一组电阻器，一组比较器，编码器和输出单元。输出单元包括校正电路。逆变器构成校正电路。在A-D转换器将输入的模拟信号转换为2位二进制码的情况下和A-D转换器将输入的模拟信号转换为4位二进制码的情况下，共享编码器。当A-D转换器将输入的模拟信号转换为2位二进制码时，校正电路校正编码器的输出。

23. 发明授权

US07224300B2 Floating gate digital-to-analog converter 有权
标题翻译：浮动门数模转换器
公开(公告)号：US07224300B2
公开(公告)日：2007-05-29
申请号：US10308438
申请日：2002-12-02
申请人： Rongqing Dai , James S. Little , Kea-Tiong Tang
发明人： Rongqing Dai , James S. Little , Kea-Tiong Tang
IPC分类号： H03M1/00
CPC分类号： H03M1/1061 , H03M1/007 , H03M1/662 , H03M1/70 , H03M1/742 , H03M1/745
摘要： The present invention provides a DAC constructed from a series of floating gate devices which are programmable to a series of predetermined values. Addressing one or more of the programmed floating gate devices, will select from a wide variety of analog outputs. Reprogramming the floating gate devices, can provide a different variety of analog outputs. For example, the floating gate devices can be preprogrammed to a different range of outputs matching a range of perceptible signals.
摘要翻译：本发明提供一种由一系列可编程为一系列预定值的浮动栅极器件构成的DAC。寻址一个或多个编程的浮动栅极器件，将从各种各样的模拟输出中进行选择。重新编程浮动栅极器件，可以提供不同种类的模拟输出。例如，浮动栅极器件可以被预编程到与一系列可感知信号匹配的不同输出范围。

24. 发明授权

US07015845B2 Digital to analog converter system 有权
标题翻译：数模转换器系统
公开(公告)号：US07015845B2
公开(公告)日：2006-03-21
申请号：US10256897
申请日：2002-09-27
申请人： Michael Anthony Pugel
发明人： Michael Anthony Pugel
IPC分类号： H03M1/66
CPC分类号： H03M1/007 , H03M1/66
摘要： A control arrangement and method includes a digital to analog converter and a mode controller that is operative to provide the digital to analog converter with a plurality of reference voltage ranges (Vref) under a respective plurality of operating modes.
摘要翻译：控制装置和方法包括数模转换器和模式控制器，其可操作以在相应的多个操作模式下向多个参考电压范围（Vref）提供数模转换器。

25. 发明授权

US06700524B2 A/D converter for performing pipeline processing 失效
标题翻译：用于执行流水线处理的A / D转换器
公开(公告)号：US06700524B2
公开(公告)日：2004-03-02
申请号：US10256238
申请日：2002-09-27
申请人： Junichi Naka , Yoichi Okamoto , Yoshitsugu Inagaki , Kenji Murata , Koji Oka
发明人： Junichi Naka , Yoichi Okamoto , Yoshitsugu Inagaki , Kenji Murata , Koji Oka
IPC分类号： H03M138
CPC分类号： H03M1/007 , H03M1/0695 , H03M1/44
摘要： An A/D converter comprises a pipeline stage array in which plural pipeline stages are connected in series, each pipeline stage performing a pipeline operation on an inputted analog voltage to output a digital voltage; a number-of-bits control circuit for outputting a number-of-bits selection signal which indicates whether the operation of each pipeline stage should be carried out or halted, according to a number-of-bits control signal which indicates a resolution; and a correction circuit for compensating a digital value to be output, according to the number-of-bits control signal. Therefore, when resolution of the A/D converter, which is requested by the system, is changed, only the pipeline stages required for realizing the requested resolution are operated while the other pipeline stages are halted, whereby a reduction in power consumption of the A/D converter is realized and, simultaneously, a breakdown of an output from the A/D converter is avoided.
摘要翻译： A / D转换器包括一个其中多个流水线级串联连接的流水线阵列，每个流水线级对所输入的模拟电压进行流水线操作以输出数字电压; 根据指示分辨率的位数控制信号，输出指示每个流水线级的操作是否应被执行或停止的位数选择信号的位数控制电路; 以及根据位数控制信号补偿要输出的数字值的校正电路。因此，当系统请求的A / D转换器的分辨率改变时，仅在实现所请求的分辨率所需的流水线阶段在其它流水线级停止的同时被操作，从而降低了A / D转换器，同时避免了A / D转换器的输出故障。

26. 发明申请

US20030076250A1 Method and apparatus for flexible analog-to-digital conversion 审中-公开
标题翻译：用于灵活模数转换的方法和装置
公开(公告)号：US20030076250A1
公开(公告)日：2003-04-24
申请号：US10147250
申请日：2002-05-16
发明人： Mark P. Enochson , Jimmie C. Vernon , Gary V. Zanders , Richard J. DelRossi
IPC分类号： H03M001/10
CPC分类号： H03M1/004 , H03M1/007 , H03M1/12
摘要： An analog-to-digital converter (ADC) includes storage for one or more configuration parameter values. Configuration parameter values stored in the storage locations are used by control logic to configure the ADC's conversion mechanism. The configuration values may be arranged in lists that the control logic cycles through in order to modify the configuration of the ADC's conversion mechanism. The control logic may change from one list, or series of lists, to another in order to adapt the ADC to changing circumstances. The changing circumstances may include the changing state of charge in a battery monitoring application.
摘要翻译：模数转换器（ADC）包括用于一个或多个配置参数值的存储。存储在存储位置的配置参数值由控制逻辑用于配置ADC的转换机制。配置值可以排列在控制逻辑循环的列表中，以便修改ADC转换机制的配置。控制逻辑可以从一个列表或一系列列表改变到另一个，以便使ADC适应不断变化的环境。不断变化的情况可能包括电池监控应用中的充电状态。

27. 发明申请

US20030058150A1 A/D converter 失效
标题翻译： A / D转换器
公开(公告)号：US20030058150A1
公开(公告)日：2003-03-27
申请号：US10256238
申请日：2002-09-27
申请人： Matsushita Electric Industrial Co., Ltd.
发明人： Junichi Naka , Yoichi Okamoto , Yoshitsugu Inagaki , Kenji Murata , Koji Oka
IPC分类号： H03M001/38
CPC分类号： H03M1/007 , H03M1/0695 , H03M1/44
摘要： An A/D converter comprises a pipeline stage array in which plural pipeline stages are connected in series, each pipeline stage performing a pipeline operation on an inputted analog voltage to output a digital voltage; a number-of-bits control circuit for outputting a number-of-bits selection signal which indicates whether the operation of each pipeline stage should be carried out or halted, according to a number-of-bits control signal which indicates a resolution; and a correction circuit for compensating a digital value to be output, according to the number-of-bits control signal. Therefore, when resolution of the A/D converter, which is requested by the system, is changed, only the pipeline stages required for realizing the requested resolution are operated while the other pipeline stages are halted, whereby a reduction in power consumption of the A/D converter is realized and, simultaneously, a breakdown of an output from the A/D converter is avoided.
摘要翻译： A / D转换器包括一个其中多个流水线级串联连接的流水线阵列，每个流水线级对所输入的模拟电压进行流水线操作以输出数字电压; 根据指示分辨率的位数控制信号，输出指示每个流水线级的操作是否应被执行或停止的位数选择信号的位数控制电路; 以及根据位数控制信号补偿要输出的数字值的校正电路。因此，当系统请求的A / D转换器的分辨率改变时，仅在实现所请求的分辨率所需的流水线阶段在其它流水线级停止的同时被操作，从而降低了A / D转换器，同时避免了A / D转换器的输出故障。

28. 发明授权

US06175520B1 Nonvolatile memory array having local program load line repeaters 失效
标题翻译：具有本地程序加载线中继器的非易失性存储器阵列
公开(公告)号：US06175520B1
公开(公告)日：2001-01-16
申请号：US08866094
申请日：1997-05-30
申请人： T. Damodar Reddy , Abhijit Ray
发明人： T. Damodar Reddy , Abhijit Ray
IPC分类号： G11C1134
CPC分类号： H03M1/007 , H03M1/206 , H03M1/365
摘要： A flash EPROM device (100) is disclosed. During a programming operation, a primary programming voltage circuit (116) drives I/O lines (110) to a programming voltage (Vp) according to input data values. Secondary programming voltage circuits (118) are located remotely from the primary programming voltage circuit (116) and further drive I/O lines to Vp in response to the voltage levels on the I/O lines. This arrangement reduces the effect on the load line response of the impedance intermediate the primary programming voltage circuit (116) and the secondary programming voltage circuits (118).
摘要翻译：闪存EPROM设备（100）被公开。在编程操作期间，主编程电压电路（116）根据输入数据值将I / O线（110）驱动到编程电压（Vp）。第二编程电压电路（118）远离主编程电压电路（116）定位，并且响应于I / O线上的电压电平进一步将I / O线驱动到Vp。这种布置减少了对主编程电压电路（116）和次级编程电压电路（118）之间的阻抗的负载线响应的影响。

29. 发明授权

US5243535A Digital potentiometer with stackable configuration 失效
标题翻译：数字电位器可堆叠配置
公开(公告)号：US5243535A
公开(公告)日：1993-09-07
申请号：US502269
申请日：1990-03-30
申请人： Michael L. Bolan , Robert D. Lee , Gary V. Zanders
发明人： Michael L. Bolan , Robert D. Lee , Gary V. Zanders
IPC分类号： G05B24/02 , H04R25/00
CPC分类号： H03M1/007 , G05B24/02 , H03M1/682 , H03M1/765 , H03M1/804
摘要： An integrated circuit containing two digital potentiometers with each potentiometer including a passive resistor string with tap points. Tap point selection is programmed through a three-wire serial port. An output multiplexing the selected tap points permits tying the two potentiometers in series to form a single potentiometer of twice the size.
摘要翻译：包含两个数字电位器的集成电路，每个电位器包括一个带抽头点的无源电阻串。分接点选择通过三线串行端口编程。输出多路复用所选择的分接点允许串联两个电位器，形成两倍大小的单个电位器。

30. 发明授权

US4396905A Asynchronously controllable successive approximation analog-to-digital converter 失效
公开(公告)号：US4396905A
公开(公告)日：1983-08-02
申请号：US104166
申请日：1979-12-17
申请人： Daniel F. Chan , Willard K. Bucklen
发明人： Daniel F. Chan , Willard K. Bucklen
IPC分类号： H03M1/00 , H03M1/46 , H03K13/03
CPC分类号： H03M1/007 , H03M1/462
摘要： A successive approximation analog-to-digital converter controllable by signals to start and interrupt conversion asynchronously with respect to clock signals used to regulate operation of the converter. Separate control signal processing circuits register the occurrence of start-convert and conversion-interrupt signals supplied by a user of the converter, and generate corresponding control signals synchronized with the clock signals. Asynchronous operation of the converter allows it to function in a short-cycling mode, wherein the number of bits of resolution in the conversion process is automatically reduced as little as possible to complete each conversion in the time allotted by the user. A continuous-conversion signal is also provided, to permit operation on a continuous basis, without providing periodic start-convert signals.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式