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    • 21. 发明授权
    • In system calibration of wake up timer
    • 在唤醒定时器的系统校准中
    • US09510289B1
    • 2016-11-29
    • US14934058
    • 2015-11-05
    • Silicon Laboratories Inc.
    • Hendricus de Ruijter
    • H04B7/00H04W52/02H03L7/14
    • H04W52/0235H03L7/148Y02D70/144Y02D70/26
    • A wireless transceiver includes receiver front-end circuitry for processing an ingoing radio frequency (RF) signal to produce an in-going digital signal to a processor connected to receive the in-going digital signal. The processor includes sync word determination logic configured to identify a received sync word or other event or connection point and to subsequently generate an event determination signal. A low power oscillator produces low frequency pulses to a first counter. A crystal oscillator that produces higher frequency pulses to a second counter is used for the last portion of the desired sleep time for greater resolution. Thus, a calibration controller receives pulse counts from at least one of the first and second counters and determines a period between a common event of subsequent beacon signals or connection events and determines wake up times based on the received pulse counts from at least one of the first and second counters.
    • 无线收发器包括接收机前端电路,用于处理入射射频(RF)信号以产生正在进行的数字信号到连接的处理器以接收正在进行的数字信号。 处理器包括被配置为识别所接收的同步字或其他事件或连接点并且随后生成事件确定信号的同步字确定逻辑。 低功率振荡器产生低频脉冲到第一个计数器。 在第二计数器产生较高频率脉冲的晶体振荡器用于所需睡眠时间的最后部分,以获得更高的分辨率。 因此,校准控制器从第一和第二计数器中的至少一个计数器接收脉冲计数,并且确定后续信标信号或连接事件的公共事件之间的周期,并且基于从至少一个的接收到的脉冲计数确定唤醒时间 第一和第二柜台。
    • 22. 发明申请
    • CLOCK GENERATOR AND SYSTEM INCLUDING THE SAME
    • 时钟发生器和系统,包括它们
    • US20130328604A1
    • 2013-12-12
    • US13964584
    • 2013-08-12
    • FUJITSU LIMITED
    • Atsushi MATSUDA
    • H03L7/14
    • H03L7/148H03L7/107H03L7/16H03L2207/50
    • A clock generator includes a digitally controlled oscillator configured to generate an output clock haying a frequency depending on an input code; phase comparison section configured to output a phase differences signal by comparing a reference phase with a phase of the output clock, the reference phase being based on an input clock and a predetermined frequency multiplication number; low-pass filter configured to provide the input code for the digitally controlled oscillator by filtering the phase difference signal; a waveform generating section configured to generate a predetermined spread spectrum wave, the predetermined spread spectrum wave being to be added with both of the frequency multiplication number and the input code; and a detection/compensation section configured to compensate the input code so that the phase difference is reduced, the phase difference being detected from the phase difference signal.
    • 时钟发生器包括数字控制振荡器,其被配置为根据输入代码产生产生频率的输出时钟; 相位比较部,被配置为通过将参考相位与所述输出时钟的相位进行比较来输出相位差信号,所述参考相位基于输入时钟和预定倍频数; 低通滤波器,被配置为通过对相位差信号进行滤波来提供数字控制振荡器的输入码; 波形发生部分,被配置为产生预定的扩频波,所述预定的扩频波将被加上倍频号和输入码; 以及检测/补偿部,被配置为补偿输入代码,使得相位差减小,从相位差信号检测相位差。