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21. 发明申请

US20190097845A1 CONTINUOUS TIME LINEAR EQUALIZER 审中-公开
公开(公告)号：US20190097845A1
公开(公告)日：2019-03-28
申请号：US15715205
申请日：2017-09-26
申请人： International Business Machines Corporation
发明人： Pier Andrea Francese , Ilter Oezkaya , Alessandro Cevrero
IPC分类号： H04L25/03 , H03F3/45 , H03F3/193
CPC分类号： H04L25/03038 , H03F3/193 , H03F3/34 , H03F3/345 , H03F3/45179 , H03F3/45224 , H03F3/45246 , H03F2203/45022 , H03F2203/45028 , H03F2203/45394 , H04B1/1081 , H04L25/03159 , H04L25/03885 , H04L2025/03541
摘要： The present invention relates to a continuous time linear equalizer comprising a first signal path comprising a high pass filter and a first controllable transconductance unit and a second signal path comprising a second controllable transconductance unit. The continuous time linear equalizer comprises a summation node configured to receive complementary current summation signals of the first transconductance unit and the second transconductance unit. The high pass filter comprises a first port configured to receive an input signal, a second port coupled to a control port of the first transconductance unit and a third port coupled to the summation node. The invention is notably also directed to a corresponding method and a corresponding design structure.

22. 发明授权

US10008931B2 Semiconductor integrated circuit 有权
公开(公告)号：US10008931B2
公开(公告)日：2018-06-26
申请号：US15257131
申请日：2016-09-06
申请人： TOSHIBA MEMORY CORPORATION
发明人： Hiroyuki Ideno , Hidefumi Kushibe
IPC分类号： G05F1/575 , G05F1/56 , G05F1/46 , G05F1/565 , G05F1/618 , H02M3/158
CPC分类号： H02M3/158 , G05F1/563 , G05F1/565 , G05F1/571 , G05F1/575 , H03F3/34 , H03F2200/555 , H03F2200/78
摘要： According to one embodiment, in a semiconductor integrated circuit, a first input terminal of an error amplifier is electrically connected to a third node between a second node and a reference potential. A second input terminal of the error amplifier is electrically connected to a reference voltage. An output terminal of the error amplifier is electrically connected to a gate of an output transistor. A first input terminal of a comparator is electrically connected to a fourth node between the second node and the reference potential. A second input terminal of the comparator is electrically connected to the reference voltage. One end of a coupling capacitance is electrically connected to an output terminal of the comparator. A gate of an auxiliary transistor is electrically connected to the other end of the coupling capacitance. A drain of the auxiliary transistor is electrically connected to the second node.

23. 发明申请

US20150355653A1 Linear Voltage Regulator Utilizing a Large Range of Bypass-Capacitance 有权
标题翻译：线性稳压器利用大范围的旁路电容
公开(公告)号：US20150355653A1
公开(公告)日：2015-12-10
申请号：US14632345
申请日：2015-02-26
申请人： Dialog Semiconductor GmbH
发明人： Stephan Drebinger , Roberto Curra
IPC分类号： G05F1/575
CPC分类号： G05F1/575 , H03F3/34 , H03F3/45183 , H03F2200/297 , H03F2203/45301 , H03F2203/45674
摘要： Amplifiers, notably multi-stage amplifiers, such as linear regulators (e.g. low-dropout regulators) configured to provide a constant output voltage subject to load transients are presented. An amplifier is described, which comprises a first amplification stage configured to provide an intermediate voltage, based on an outer feedback voltage and based on a reference voltage. Furthermore, the amplifier comprises an output stage configured to provide a load current at an output voltage based on the intermediate voltage. In addition, the amplifier comprises an outer feedback circuit configured to derive the outer feedback voltage from the output voltage. The output stage comprises a buffer configured to provide a drive voltage based on the intermediate voltage and based on an inner feedback voltage derived from the output voltage. The buffer comprises a pass device which is configured to provide the load current at the output voltage based on the drive voltage.
摘要翻译：放大器，特别是多级放大器，例如被配置为提供经受负载瞬变的恒定输出电压的线性稳压器（例如低压差稳压器）。描述了放大器，其包括第一放大级，其被配置为基于外部反馈电压并且基于参考电压提供中间电压。此外，放大器包括输出级，其被配置为基于中间电压在输出电压下提供负载电流。此外，放大器包括被配置为从输出电压导出外部反馈电压的外部反馈电路。输出级包括被配置为基于中间电压提供驱动电压并基于从输出电压导出的内部反馈电压的缓冲器。缓冲器包括通过装置，其被配置为基于驱动电压在输出电压下提供负载电流。

24. 发明申请

US20140097698A1 MULTI-MODE POWER AMPLIFYING CIRCUIT, AND MULTI-MODE WIRELESS TRANSMISSION MODULE AND METHOD THEREOF 有权
标题翻译：多模式功率放大电路和多模式无线传输模块及其方法
公开(公告)号：US20140097698A1
公开(公告)日：2014-04-10
申请号：US14045213
申请日：2013-10-03
申请人： REALTEK SEMICONDUCTOR CORP.
发明人： Po-Chih WANG , Ya-Wen YANG
IPC分类号： H01F38/14
CPC分类号： H01F38/14 , H03F1/0277 , H03F3/24 , H03F3/34 , H04B1/0458
摘要： A multi-mode power amplifying circuit, and a multi-mode wireless transmission module and method thereof are provided. The multi-mode wireless transmission module includes the multi-mode power amplifying circuit and an antenna. In the multi-mode power amplifying circuit and the antenna, a first power amplifier is electrically connected between a signal input end and a first impedance matching circuit, and an output end of the first impedance matching circuit is electrically connected to the antenna. A second power amplifier is electrically connected to the signal input end, and a second impedance matching circuit is electrically connected between the second power amplifier and the first impedance matching circuit. A switching circuit is electrically connected to an input end of the second impedance matching circuit. The switching circuit switches on-off corresponding to an operation of the first power amplifier and an operation of the second power amplifier.
摘要翻译：提供了一种多模式功率放大电路以及多模式无线传输模块及其方法。多模无线传输模块包括多模功率放大电路和天线。在多模式功率放大电路和天线中，第一功率放大器电连接在信号输入端和第一阻抗匹配电路之间，第一阻抗匹配电路的输出端电连接到天线。第二功率放大器电连接到信号输入端，并且第二阻抗匹配电路电连接在第二功率放大器和第一阻抗匹配电路之间。开关电路电连接到第二阻抗匹配电路的输入端。开关电路对应于第一功率放大器的操作和第二功率放大器的操作而导通 - 断开。

25. 发明授权

US08059777B2 Method and apparatus for generating phase shifted local oscillator signals for a feedback loop on a transmitter 有权
标题翻译：用于产生发射机中的反馈回路的相移本地振荡器信号的方法和装置
公开(公告)号：US08059777B2
公开(公告)日：2011-11-15
申请号：US11941281
申请日：2007-11-16
申请人： Jeffrey B. Wilhite , Paul H. Gailus
发明人： Jeffrey B. Wilhite , Paul H. Gailus
IPC分类号： H03D3/24
CPC分类号： H03F3/24 , H03F1/34 , H03F3/34 , H03F2200/438 , H03F2200/451 , H03F2200/57 , H04B2001/0433
摘要： A transmitter is provided with a local oscillator (LO) processing unit to maintain stability in the transmitter's feedback loop. The LO processing unit includes at least one delay locked loop (DLL) and a programmable divider to generate phase shifted LO signals for adjusting a loop phase of the feedback loop in the transmitter. The generated phase shifted LO signals are of both a coarse and fine phase shifted nature. The adjustability and control of the coarse and fine phase shifting of the LO signals maintains linearity in the transmitter feedback loop.
摘要翻译：发射机设有本地振荡器（LO）处理单元，以保持发射机反馈环路的稳定性。 LO处理单元包括至少一个延迟锁定环（DLL）和可编程分频器，以产生相移的LO信号，用于调整发射机中的反馈回路的环路相位。产生的相移的LO信号既具有粗调和精细的相移特性。 LO信号的粗调和精细相移的可调性和控制在发射机反馈环路中保持线性。

26. 发明申请

US20110051954A1 SIGNAL CONDITIONER WITH SUPPRESSION OF INTERFERING SIGNALS 审中-公开
标题翻译：信号调节器抑制干扰信号
公开(公告)号：US20110051954A1
公开(公告)日：2011-03-03
申请号：US12863227
申请日：2009-01-20
申请人： Henrik Thomsen , Claus Erdmann Furst
发明人： Henrik Thomsen , Claus Erdmann Furst
IPC分类号： H04B15/00
CPC分类号： H03F3/34 , H03F2200/321 , H03M1/00 , H03M1/181 , H03M1/183 , H04R1/04 , H04R3/00 , H04R3/06 , H04R25/505 , H04R2499/11
摘要： A semiconductor die with an integrated circuit providing a signal conditioner (106) for a capacitive transducer (105), comprising: a gain stage (101) configured to receive an analogue transducer signal; an analogue-to-digital converter (102) coupled to receive a signal outputted from the gain stage (101) and to provide a digital signal. A feedback signal is provided via a digital-to-analogue converter (104) and a digital signal processor (103) that receives the digital signal; and the gain stage (101) is configured with a first input (107) and second input (108) coupled to receive the analogue transducer signal and the feedback signal, respectively.
摘要翻译：一种具有提供用于电容式换能器（105）的信号调节器（106）的集成电路的半导体管芯，包括：增益级（101），被配置为接收模拟换能器信号; 耦合以接收从增益级（101）输出的信号并提供数字信号的模拟 - 数字转换器（102）。经由数模转换器（104）和接收数字信号的数字信号处理器（103）提供反馈信号; 并且增益级（101）被配置有分别耦合以接收模拟换能器信号和反馈信号的第一输入（107）和第二输入（108）。

27. 发明授权

US4274058A Amplifier with separate AC and DC feedback loops 失效
标题翻译：具有单独的交流和直流反馈回路的放大器
公开(公告)号：US4274058A
公开(公告)日：1981-06-16
申请号：US30388
申请日：1979-04-16
申请人： Tadao Suzuki
发明人： Tadao Suzuki
IPC分类号： H03G3/12 , H03F1/30 , H03F1/34 , H03F3/183 , H03F3/185 , H03F3/34 , H03G1/00 , H03G3/02 , H03G3/04 , H03G3/10 , H03F3/45
CPC分类号： H03F1/34 , H03F1/30 , H03F3/183 , H03F3/1855 , H03F3/34 , H03G1/0023 , H03G3/02 , H03G3/04 , H03G3/10
摘要： An amplifier with separate AC and DC feedback loops is disclosed, in which first and second bipolar transistors or field effect transistors (FET) are connected differentially, a resistor is inserted between the emitters or sources of the first and second transistors, the base or gate of the first transistor is supplied with an input signal, the DC component of an output is fed back to the base or gate of the second transistor, the AC component of the output is fed back to the emitter or source of the second transistor to change over the feeding back amount of the AC component.
摘要翻译：公开了具有单独的AC和DC反馈回路的放大器，其中第一和第二双极晶体管或场效应晶体管（FET）差分连接，电阻器插入在第一和第二晶体管的发射极或源极之间，基极或栅极第一晶体管的输入信号被提供有输入信号，输出的直流分量被反馈到第二晶体管的基极或栅极，输出的交流分量被反馈到第二晶体管的发射极或源极以改变超过AC组件的反馈量。

28. 发明授权

US3733514A Wide band amplifier having two separate high and low frequency paths for driving capacitive load with large amplitude signal 失效
标题翻译：具有两个高分辨率和低频率的宽带放大器用于驱动具有大幅度信号的电容性负载
公开(公告)号：US3733514A
公开(公告)日：1973-05-15
申请号：US3733514D
申请日：1971-03-19
申请人： TEKTRONIX INC
发明人： GARUTS V
IPC分类号： H03F1/22 , H03F1/34 , H03F1/42 , H03F1/48 , H03F3/19 , H03F3/34 , H03F3/343 , H01J29/70
CPC分类号： H03F3/19 , H03F1/22 , H03F1/34 , H03F1/48 , H03F3/34 , H03F2200/39
摘要： A wide frequency bandwidth amplifier circuit for driving an output load capacitance with large amplitude signals is described in which two separate paths are provided for low frequency and high frequency portions of such signal. The low frequency path is provided by a shunt feedback amplifier connected as an operational amplifier, while the high frequency path is formed by a series feedback amplifier. The gain of the series feedback amplifier, determined by the ratio of its series feedback capacitance divided by the output load capacitance, is made equal to the gain of the operational amplifier, determined by the ratio of its shunt feedback resistance divided by its input coupling resistance. The low frequency cutoff of the high frequency path is above the high frequency cutoff of the low frequency path. Thus, in one embodiment of the amplifier circuit with a frequency response of D.C. to 200 megahertz, the high frequency path has a response of one megahertz to 200 megahertz and the low frequency path has a response of D.C. to 30 megahertz. This embodiment is used as a horizontal sweep amplifier for driving the horizontal deflection plates of a cathode ray oscilloscope with a ramp shaped output signal of 80 volts amplitude and three nanoseconds rise time.
摘要翻译：描述了用于驱动具有大振幅信号的输出负载电容的宽频带宽放大器电路，其中为这种信号的低频部分和高频部分提供了两条分开的路径。低频路径由作为运算放大器连接的并联反馈放大器提供，而高频路径由串联反馈放大器形成。串联反馈放大器的增益取决于其串联反馈电容除以输出负载电容的比例，由运算放大器的增益决定，其分流反馈电阻除以其输入耦合电阻。高频路径的低频截止值高于低频路径的高频截止频率。因此，在具有DCC至200MHz的频率响应的放大器电路的一个实施例中，高频路径具有1兆赫至200兆赫的响应，低频路径具有DCC至30兆赫的响应。该实施例用作水平扫描放大器，用于驱动具有80伏幅度和三纳秒上升时间的斜坡形输出信号的阴极射线示波器的水平偏转板。

29. 发明授权

US10499150B2 Microphone assembly with digital feedback loop 有权
公开(公告)号：US10499150B2
公开(公告)日：2019-12-03
申请号：US15202404
申请日：2016-07-05
申请人： Knowles Electronics, LLC
发明人： Mohammad Shajaan , Claus Erdmann Fürst , Per Flemming Høvesten , Kim Spetzler Berthelsen , Henrik Thomsen
IPC分类号： H04R3/00 , H03M1/00 , H04R3/02 , H04R3/04 , H03F3/70 , H03F3/34 , H03M3/00 , H03G3/30 , H03M1/18 , H04R1/04
CPC分类号： H04R3/02 , H04R3/04 , H03F3/34 , H03F3/70 , H03G3/30 , H03M1/181 , H03M3/464 , H03M3/48 , H03M3/49 , H04R1/04
摘要： A microphone assembly includes a transducer and a processing circuit. The processing circuit includes an analog-to-digital converter (ADC) configured to receive, sample and quantize an electrical signal generated by the transducer to generate a corresponding digital signal. The processing circuit includes a feedback path including a digital loop filter configured to receive and filter the digital signal to provide a first digital feedback signal and a digital-to-analog converter (DAC) configured to convert the first digital feedback signal into a corresponding analog feedback signal. The processing circuit additionally includes a summing node configured to combine the electrical signal and the analog feedback signal.

30. 发明申请

US20190250246A1 RADAR SIGNAL PROCESSOR AND RADAR SYSTEM 审中-公开
公开(公告)号：US20190250246A1
公开(公告)日：2019-08-15
申请号：US16396977
申请日：2019-04-29
申请人： DENSO CORPORATION
发明人： Tomotoshi MURAKAMI , Nobumasa HASEGAWA , Yoshiyuki UTAGAWA
IPC分类号： G01S7/35 , G01S13/34 , H03F3/195 , H03F1/34
CPC分类号： G01S7/354 , G01S7/35 , G01S13/34 , H03D7/00 , H03F1/34 , H03F3/195 , H03F3/34 , H03F2200/129 , H03F2200/156 , H03F2200/267 , H03F2200/333 , H03F2200/375 , H03F2200/451 , H04B1/16 , H04B1/30
摘要： A radar system includes a transmitter circuit, which transmits a radar wave having a chirp frequency gradually increasing or decreasing to a target, and a frequency conversion circuit, which demodulates a signal of the radar wave reflected at the target by frequency-conversion in correspondence to the chirp frequency. A radar signal processor includes a variable amplifier connected to an output side of the frequency conversion circuit, and a feedback circuit which detects an output of the variable amplifier as a detection signal and feeds back a signal of a frequency band included in the detection signal to an input of the variable amplifier. The feedback circuit is configured to cut off and not cut off a frequency band including a DC offset transient response frequency, which occurs at time of frequency conversion by the frequency conversion circuit, during a specified period and a period other than the specified period, respectively. The specified period is a predetermined first period from starting of a demodulation operation of the frequency conversion circuit and/or a predetermined second period from ending of the demodulation operation of the frequency operation of the frequency conversion circuit.

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