专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明申请

US20140225234A1 SEMICONDUCTOR DEVICE HAVING LATERAL DIODE 审中-公开
标题翻译：具有横向二极管的半导体器件
公开(公告)号：US20140225234A1
公开(公告)日：2014-08-14
申请号：US14258082
申请日：2014-04-22
申请人： DENSO CORPORATION
发明人： Takao YAMAMOTO , Norihito TOKURA , Hisato KATO , Akio NAKAGAWA
IPC分类号： H01L29/868
CPC分类号： H01L29/868 , H01L27/0664 , H01L29/0615 , H01L29/0692 , H01L29/0878 , H01L29/1095 , H01L29/405 , H01L29/42368 , H01L29/7394 , H01L29/7824
摘要： A semiconductor device having a lateral diode includes a semiconductor layer, a first semiconductor region in the semiconductor layer, a contact region having an impurity concentration greater than that of the first semiconductor region, a second semiconductor region located in the semiconductor layer and separated from the contact region, a first electrode electrically connected through the contact region to the first semiconductor region, and a second electrode electrically connected to the second semiconductor region. The second semiconductor region includes a low impurity concentration portion, a high impurity concentration portion, and an extension portion. The second electrode forms an ohmic contact with the high impurity concentration portion. The extension portion has an impurity concentration greater than that of the low impurity concentration portion and extends in a thickness direction of the semiconductor layer.
摘要翻译：具有横向二极管的半导体器件包括半导体层，半导体层中的第一半导体区域，具有大于第一半导体区域的杂质浓度的杂质浓度的接触区域，位于半导体层中并与该半导体层分离的第二半导体区域接触区域，通过接触区域电连接到第一半导体区域的第一电极和与第二半导体区域电连接的第二电极。第二半导体区域包括低杂质浓度部分，高杂质浓度部分和延伸部分。第二电极与高杂质浓度部分形成欧姆接触。延伸部分的杂质浓度大于低杂质浓度部分的杂质浓度，并且在半导体层的厚度方向上延伸。

22. 发明授权

US08754442B2 Silicon on insulator integrated high-current N type combined semiconductor device 有权
标题翻译：绝缘子上集成大电流N型组合半导体器件
公开(公告)号：US08754442B2
公开(公告)日：2014-06-17
申请号：US13819286
申请日：2011-07-11
申请人： Longxing Shi , Qinsong Qian , Changlong Huo , Weifeng Sun , Shengli Lu
发明人： Longxing Shi , Qinsong Qian , Changlong Huo , Weifeng Sun , Shengli Lu
IPC分类号： H01L29/76
CPC分类号： H01L27/1203 , H01L21/743 , H01L27/0705 , H01L29/66325 , H01L29/7394
摘要： A silicon on insulator N type semiconductor device, includes a N type drift region, a P type deep well, an N type buffer well, a P type drain region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer; and an N type triode drift region, a P type deep well, an N type triode buffer well, a P type emitting region, an N type base region, an N type source region and a P type body contact region; a field oxide layer and a gate oxide layer arranged on a silicon surface, and a polysilicon lattice arranged on the gate oxide layer.
摘要翻译：一种绝缘体上的N型半导体器件，包括N型漂移区，P型深阱，N型缓冲阱，P型漏极区，N型源区和P型体接触区; 布置在硅表面上的场氧化物层和栅氧化层，以及布置在栅氧化层上的多晶硅晶格; N型三极管漂移区，P型深阱，N型三极管缓冲阱，P型发射区，N型基极区域，N型源极区域和P型体接触区域; 设置在硅表面上的场氧化物层和栅氧化层，以及布置在栅极氧化物层上的多晶硅晶格。

23. 发明授权

US08748934B2 Vertical selection transistor, memory cell, and three-dimensional memory array structure and method for fabricating the same 有权
标题翻译：垂直选择晶体管，存储单元和三维存储器阵列结构及其制造方法
公开(公告)号：US08748934B2
公开(公告)日：2014-06-10
申请号：US13520166
申请日：2012-03-12
申请人： Liyang Pan , Fang Yuan
发明人： Liyang Pan , Fang Yuan
IPC分类号： H01L29/08 , H01L27/24 , H01L21/70 , H01L29/78
CPC分类号： H01L27/24 , H01L21/70 , H01L27/2445 , H01L27/2481 , H01L29/04 , H01L29/66348 , H01L29/7394 , H01L29/7397 , H01L29/7827 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/145 , H01L45/146 , H01L45/1675
摘要： The present disclosure discloses a vertical selection transistor, a memory cell having the vertical selection transistor, a three-dimensional memory array structure and a method for fabricating the three-dimensional memory array structure. The vertical selection transistor comprises: an upper electrode; a lower electrode; a first semiconductor layer, a second semiconductor layer, a third semiconductor layer and a fourth semiconductor layer vertically stacked between the lower electrode and the upper electrode; and a gate stack formed on a side of the second semiconductor layer, in which the first semiconductor layer and the third semiconductor layer are first type doped layers, the second semiconductor layer and the fourth semiconductor layer are second type doped layers, and a doping concentration of the second semiconductor layer is lower than that of the first semiconductor layer or that of the third semiconductor layer respectively.
摘要翻译：本公开公开了一种垂直选择晶体管，具有垂直选择晶体管的存储单元，三维存储器阵列结构和用于制造三维存储器阵列结构的方法。垂直选择晶体管包括：上电极; 下电极第一半导体层，第二半导体层，第三半导体层和垂直堆叠在下电极和上电极之间的第四半导体层; 以及形成在所述第二半导体层的一侧的栅堆叠，其中所述第一半导体层和所述第三半导体层是第一掺杂层，所述第二半导体层和所述第四半导体层是第二掺杂层，并且掺杂浓度分别低于第一半导体层或第三半导体层的厚度。

24. 发明申请

US20140077260A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140077260A1
公开(公告)日：2014-03-20
申请号：US13780771
申请日：2013-02-28
申请人： KABUSHIKI KAISHA TOSHIBA
发明人： Yoko SAKIYAMA , Kohei MORIZUKA
IPC分类号： H01L29/739 , H01L27/12
CPC分类号： H01L29/7394 , H01L23/552 , H01L24/48 , H01L25/072 , H01L27/1211 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2924/00014 , H01L2924/1203 , H01L2924/1305 , H01L2924/13055 , H01L2924/13091 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The semiconductor device includes a plurality of first flat plates containing a material that absorbs an electromagnetic wave at a high frequency. Any of the first flat plates is disposed above the first connecting wire, and any other of the first flat plates is disposed above the second connecting wire.
摘要翻译：半导体器件包括多个第一平板，其包含以高频率吸收电磁波的材料。任何第一平板都设置在第一连接线上方，并且第一平板中的任何另一个设置在第二连接线的上方。

25. 发明申请

US20140070271A1 LATERAL INSULATED GATE BIPOLAR TRANSISTOR 审中-公开
标题翻译：横向绝缘门双极晶体管
公开(公告)号：US20140070271A1
公开(公告)日：2014-03-13
申请号：US14077510
申请日：2013-11-12
申请人： Denso Corporation
发明人： Shigeki TAKAHASHI , Norihito TOKURA , Satoshi SHIRAKI , Youichi ASHIDA , Akio NAKAGAWA
IPC分类号： H01L29/739
CPC分类号： H01L29/7393 , H01L29/0696 , H01L29/0834 , H01L29/1095 , H01L29/405 , H01L29/7394
摘要： A lateral insulated gate bipolar transistor includes a semiconductor substrate including a drift layer, a collector region, a channel layer, an emitter region, a gate insulating layer, a gate electrode, a collector electrode, an emitter electrode, and a barrier layer. The barrier layer is disposed along either side of the collector region and is located to a depth deeper than a bottom of the channel layer. The barrier layer has an impurity concentration that is higher than an impurity concentration of the drift layer. The barrier layer has a first end close to the collector region and a second end far from the collector region. The first end is located between the channel layer and the collector region, and the second end is located on the bottom of the channel layer.
摘要翻译：横向绝缘栅双极晶体管包括包括漂移层，集电极区域，沟道层，发射极区域，栅极绝缘层，栅电极，集电极，发射极和阻挡层的半导体衬底。阻挡层沿着集电极区域的两侧设置，并且位于比通道层的底部更深的深度。阻挡层的杂质浓度高于漂移层的杂质浓度。阻挡层具有靠近集电极区域的第一端和远离集电极区域的第二端。第一端位于沟道层和集电极区之间，第二端位于沟道层的底部。

26. 发明授权

US08653536B2 Method for manufacturing semiconductor substrate, and semiconductor device 有权
标题翻译：半导体基板的制造方法以及半导体装置
公开(公告)号：US08653536B2
公开(公告)日：2014-02-18
申请号：US13965275
申请日：2013-08-13
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Shunpei Yamazaki
IPC分类号： H01L29/15
CPC分类号： H01L29/1608 , H01L21/76254 , H01L21/8213 , H01L21/84 , H01L27/12 , H01L29/0696 , H01L29/41766 , H01L29/66068 , H01L29/7394 , H01L29/7812 , H01L29/7824 , H01L29/7833
摘要： An object is to provide a novel manufacturing method of a semiconductor substrate containing silicon carbide, and another object is to provide a semiconductor device using silicon carbide. A semiconductor substrate is manufactured through the steps of: adding ions to a silicon carbide substrate to form an embrittlement region in the silicon carbide substrate; bonding the silicon carbide substrate to a base substrate with insulating layers interposed therebetween; heating the silicon carbide substrate and separating the silicon carbide substrate at the embrittlement region to form a silicon carbide layer over the base substrate with the insulating layers interposed between therebetween; and performing heat treatment on the silicon carbide layer at a temperature of 1000° C. to 1300° C. to reduce defects of the silicon carbide layer. A semiconductor device is manufactured using the semiconductor substrate formed as described above.
摘要翻译：本发明的目的是提供一种含有碳化硅的半导体衬底的新颖制造方法，另一个目的是提供一种使用碳化硅的半导体器件。通过以下步骤制造半导体衬底：向碳化硅衬底添加离子以在碳化硅衬底中形成脆化区; 将所述碳化硅衬底粘合到具有插入其间的绝缘层的基底衬底; 加热碳化硅衬底并在脆化区域分离碳化硅衬底以在基底衬底上形成碳化硅层，其间插入有绝缘层; 并在1000℃至1300℃的温度下对碳化硅层进行热处理以减少碳化硅层的缺陷。使用如上所述形成的半导体衬底制造半导体器件。

27. 发明申请

US20140035102A1 POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE 有权
标题翻译：电源设备集成在通用基板上
公开(公告)号：US20140035102A1
公开(公告)日：2014-02-06
申请号：US13939490
申请日：2013-07-11
申请人： I/O Semiconductor Inc.
发明人： Jacek Korec , Boyi Yang
IPC分类号： H01L27/082
CPC分类号： H01L27/082 , H01L27/1203 , H01L29/402 , H01L29/73 , H01L29/7391 , H01L29/7394 , H01L29/861 , H01L29/872 , H01L2224/11 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor structure for facilitating an integration of power devices on a common substrate includes a first insulating layer formed on the substrate and an active region having a first conductivity type formed on at least a portion of the first insulating layer. A first terminal is formed on an upper surface of the structure and electrically connects with at least one other region having the first conductivity type formed in the active region. A buried well having a second conductivity type is formed in the active region and is coupled with a second terminal formed on the upper surface of the structure. The buried well and the active region form a clamping diode which positions a breakdown avalanche region between the buried well and the first terminal. A breakdown voltage of at least one of the power devices is a function of characteristics of the buried well.
摘要翻译：用于促进功率器件集成在公共衬底上的半导体结构包括形成在衬底上的第一绝缘层和形成在第一绝缘层的至少一部分上的具有第一导电类型的有源区。第一端子形成在该结构的上表面上，并且与在活性区域中形成的具有第一导电类型的至少一个其它区域电连接。在有源区域中形成具有第二导电类型的掩埋阱，并且与形成在结构的上表面上的第二端子耦合。掩埋井和有源区域形成钳位二极管，其在掩埋井和第一端子之间定位击穿雪崩区域。功率器件中的至少一个的击穿电压是掩埋阱的特性的函数。

28. 发明申请

US20140035035A1 INSULATED GATE BIPOLAR TRANSISTOR STRUCTURE HAVING LOW SUBSTRATE LEAKAGE 有权
标题翻译：具有低基板泄漏的绝缘栅双极晶体管结构
公开(公告)号：US20140035035A1
公开(公告)日：2014-02-06
申请号：US14051655
申请日：2013-10-11
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Ker Hsiao HUO , Chih-Chang CHENG , Ru-Yi SU , Jen-Hao YEH , Fu-Chih YANG , Chun Lin TSAI
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L29/7394 , H01L21/26533 , H01L21/76243 , H01L21/76283 , H01L29/063 , H01L29/0649 , H01L29/0653 , H01L29/0865 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/42368 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66325 , H01L29/66659 , H01L29/66681 , H01L29/7816 , H01L29/7824 , H01L2924/0002 , H01L2924/00
摘要： A high voltage metal-oxide-semiconductor laterally diffused device (HV LDMOS), particularly an insulated gate bipolar junction transistor (IGBT), and a method of making it are provided in this disclosure. The device includes a semiconductor substrate, a gate structure formed on the substrate, a source and a drain formed in the substrate on either side of the gate structure, a first doped well formed in the substrate, and a second doped well formed in the first well. The gate, source, second doped well, a portion of the first well, and a portion of the drain structure are surrounded by a deep trench isolation feature and an implanted oxygen layer in the silicon substrate.
摘要翻译：在本公开中提供了高电压金属氧化物半导体横向扩散器件（HV LDMOS），特别是绝缘栅双极结型晶体管（IGBT）及其制造方法。该器件包括半导体衬底，形成在衬底上的栅极结构，在栅极结构的任一侧上的衬底中形成的源极和漏极，在衬底中形成的第一掺杂阱和形成在第一衬底中的第二掺杂阱好。栅极，源极，第二掺杂阱，第一阱的一部分和漏极结构的一部分被硅衬底中的深沟槽隔离特征和注入的氧层包围。

29. 发明授权

US08610168B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08610168B2
公开(公告)日：2013-12-17
申请号：US13117498
申请日：2011-05-27
申请人： Mitsuru Soma
发明人： Mitsuru Soma
IPC分类号： H01L29/739
CPC分类号： H01L21/84 , H01L21/76283 , H01L29/36 , H01L29/66325 , H01L29/7394
摘要： In a semiconductor device in which an IGBT, a control circuit for the IGBT and so on are formed on an SOI substrate divided by trenches, the invention is directed to providing the IGBT with a higher breakdown voltage, an enhanced turn-off characteristic and so on. An N type epitaxial layer is formed on a dummy semiconductor substrate, a trench is formed in the N type epitaxial layer, an N type buffer layer and then a P type embedded collector layer are formed on the sidewall of the trench and the front surface of the N type epitaxial layer, and the bottom of the trench and the P+ type embedded collector layer are covered by an embedded insulation film. The embedded insulation film is covered by a polysilicon film, and a P type semiconductor substrate is attached to the polysilicon film with an insulation film being interposed therebetween. Then the dummy semiconductor substrate is removed, thereby forming an SOI substrate having the embedded insulation film, the P+ type embedded collector layer, the N type buffer layer, the N type drift layer and so on that are exposed being almost flush with each other on the bottom of the trench. An IGBT and so on are formed on this SOI substrate.
摘要翻译：本发明涉及一种半导体器件，其中在由沟槽划分的SOI衬底上形成IGBT，IGBT等的控制电路，本发明涉及为IGBT提供更高的击穿电压，增强的截止特性等上。在虚拟半导体衬底上形成N型外延层，在N型外延层中形成沟槽，在沟槽的侧壁上形成N型缓冲层，然后形成P型嵌入集电极层， N型外延层和沟槽的底部以及P +型嵌入式集电极层被嵌入式绝缘膜覆盖。嵌入式绝缘膜被多晶硅膜覆盖，并且P型半导体衬底附着在多晶硅膜上，隔着绝缘膜插入其中。然后去除虚设半导体衬底，从而形成具有嵌入式绝缘膜，P +型嵌入式集电极层，N型缓冲层，N型漂移层等的SOI衬底，其被暴露几乎彼此齐平沟渠的底部。在该SOI衬底上形成IGBT等。

30. 发明申请

US20130299871A1 LATERAL TRANSISTOR ON POLYMER 有权
标题翻译：聚合物上的横向晶体管
公开(公告)号：US20130299871A1
公开(公告)日：2013-11-14
申请号：US13471453
申请日：2012-05-14
申请人： Anton MAUDER , Eric GRAETZ
发明人： Anton MAUDER , Eric GRAETZ
IPC分类号： H01L27/082 , H01L21/331 , H01L29/739
CPC分类号： H01L29/7394 , H01L27/082 , H01L27/12
摘要： Representative implementations of devices and techniques provide a high-voltage device on a semiconductor substrate. An insulating polymer layer is formed on an opposite surface to the high-voltage device, the insulating polymer layer having a thickness of at least twice that of the semiconductor substrate.
摘要翻译：器件和技术的代表性实现在半导体衬底上提供高电压器件。绝缘聚合物层形成在与高电压器件相对的表面上，绝缘聚合物层的厚度至少为半导体衬底的厚度的两倍。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式