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21. 发明申请

US20160043307A1 CONCEPTS FOR IMPROVED MAGNETIC RANDOM ACCESS MEMORY 有权
标题翻译：改进磁性随机存取存储器的概念
公开(公告)号：US20160043307A1
公开(公告)日：2016-02-11
申请号：US14818075
申请日：2015-08-04
申请人： California State University Northridge
发明人： Nicholas Kioussis , Julian Velev , Alan Kalitsov , Artur Useinov
IPC分类号： H01L43/10 , H01L43/08 , G11C11/16 , H01L43/02
CPC分类号： H01L43/10 , G11C11/161 , G11C11/1675 , G11C11/22 , G11C11/2275 , G11C11/5607 , G11C11/5657 , G11C2213/71 , H01L43/08
摘要： The present invention relates to magnetic random access memory (MRAM) storage devices based on multiferroic tunnel junctions in which ferroelectric polarization is used to control and manipulate the memory state. Invention methods include: (1) method of producing tunneling electroresistance (TER) effect in multiferroic tunnel junction (MFTJ) at finite bias; (2) method of controlling the TER effect in an MFTJ at infinite bias via the switching of the relative orientation of the ferromagnetic leads; (3) method of producing monotonous bias dependence of the tunneling magnetoresistance (TMR) in a MFTJ; (4) method of controlling the size and direction of the parallel spin transfer torque (STT) component and the perpendicular STT component across the MFTJ; (5) method of producing a monotonous bias dependence of the perpendicular STT component across an MFTJ; and (6) method of controlling the size and sign of the interlayer exchange coupling in an MFTJ. The invented products are any electric-field-controlled spin transfer torque magnetoresistive memory element based on a multiferoic tunnel junction (MTFJ) with magnetic electrodes and a simple or composite ferroelectric barrier embodying any of the claimed 6 methods.
摘要翻译：本发明涉及基于多铁路隧道结的磁性随机存取存储器（MRAM）存储装置，其中使用铁电极化来控制和操纵存储器状态。发明方法包括：（1）在有限偏差下在多铁路隧道结（MFTJ）中产生隧道电阻（TER）效应的方法; （2）通过切换铁磁引线的相对取向，在无限偏压下控制MFTJ中的TER效应的方法; （3）在MFTJ中产生隧道磁阻（TMR）的单调偏置依赖性的方法; （4）控制MFTJ上的平行自旋转移转矩（STT）分量和垂直STT分量的大小和方向的方法; （5）跨越MFTJ产生垂直STT分量的单调偏差依赖性的方法; 和（6）在MFTJ中控制层间交换耦合的尺寸和符号的方法。本发明的产品是基于具有磁极的多空间隧道结（MTFJ）和体现任何所要求的方法的简单或复合铁电屏障的任何电场控制的自旋转移转矩磁阻存储元件。

22. 发明申请

US20160005451A1 FRAM CELL WITH CROSS POINT ACCESS 有权
标题翻译：具有交叉点访问的框架单元
公开(公告)号：US20160005451A1
公开(公告)日：2016-01-07
申请号：US14324048
申请日：2014-07-03
申请人： Texas Instruments Incorporated
发明人： Saim Ahmad Qidwai , Stephen Keith Heinrich-Barna , William Francis Kraus
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C5/06 , G11C11/22 , G11C11/2253 , G11C11/2257 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C13/004
摘要： A system on chip (SoC) may have an array ferroelectric bit cells. The array may include a plurality of bit cells organized into a plurality of rows and columns. A set of word lines is configured such that one of the plurality of word lines is connected to each bit cell in a row of bit cells. A set of column oriented platelines is provided, wherein each column of bit cells has one of the plurality of platelines connected to each bit cell in the column of bit cells. A set of bitlines is provided, wherein each column of bit cells has one of the plurality of bitlines connected to each bit cell in the column of bit cells. Multiplexors may be used to allow one plateline drivers, bitline drivers, and sense amps to be shared between multiple platelines and bitlines.
摘要翻译：片上系统（SoC）可以具有阵列铁电位单元。阵列可以包括组织成多个行和列的多个位单元。一组字线被配置为使得多个字线中的一个字连接到一行位单元中的每个位单元。提供了一组以列为单位的行列，其中每列位单元具有连接到位单元列中的每个位单元的多个板之一。提供了一组位线，其中每列位单元具有连接到位单元列中的每个位单元的多个位线之一。多路复用器可以用于允许一个平台驱动器，位线驱动器和感测放大器在多个板条和位线之间共享。

23. 发明申请

US20150294705A1 ELECTRONIC DEVICE 有权
标题翻译：电子设备
公开(公告)号：US20150294705A1
公开(公告)日：2015-10-15
申请号：US14563690
申请日：2014-12-08
申请人： Ji-Wang LEE , Dong-Keun KIM , Masahiro TAKAHASHI , Tsuneo INABA
发明人： Ji-Wang LEE , Dong-Keun KIM , Masahiro TAKAHASHI , Tsuneo INABA
IPC分类号： G11C11/16 , G11C13/00
CPC分类号： G11C11/1673 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/5607 , G11C11/5657 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/28 , G11C2013/0054 , G11C2213/79
摘要： A semiconductor memory unit includes first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural number equal to or greater than 2; a reference resistance element having a first reference resistance value; and first to Nth comparison units which correspond to the first to Nth variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding variable resistance element is greater or less than a second reference resistance value, wherein the first to Nth comparison units are commonly coupled to the reference resistance element.
摘要翻译：半导体存储单元包括根据存储在其中的值具有不同电阻值的第一至第N可变电阻元件，其中N是等于或大于2的自然数; 具有第一参考电阻值的参考电阻元件; 以及分别对应于第一至第N可变电阻元件的第一至第N比较单元，并且每个比较单元确定相应的可变电阻元件的电阻值是否大于或小于第二参考电阻值，其中第一至第N 比较单元通常耦合到参考电阻元件。

24. 发明申请

US20150117084A1 MULTI-BIT FERROELECTRIC MEMORY DEVICE AND METHODS OF FORMING THE SAME 有权
标题翻译：多位电磁存储器件及其形成方法
公开(公告)号：US20150117084A1
公开(公告)日：2015-04-30
申请号：US14068887
申请日：2013-10-31
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , F. Daniel Gealy , D.V. Nirmal Ramaswamy , Chandra V. Mouli
IPC分类号： H01L43/02 , H01L43/12 , H01L21/28 , G11C11/22
CPC分类号： G11C11/5657 , G11C11/221 , G11C11/2273 , G11C11/2275 , H01L27/11507 , H01L28/40 , H01L43/02 , H01L43/12
摘要： Multi-bit ferroelectric memory devices and methods of forming the same are provided. One example method of forming a multi-bit ferroelectric memory device can include forming a first ferroelectric material on a first side of a via, removing a material to expose a second side of the via, and forming second ferroelectric material on the second side of the via at a different thickness compared to the first side of the via.
摘要翻译：提供了多位铁电存储器件及其形成方法。形成多位铁电存储器件的一个示例性方法可以包括在通孔的第一侧上形成第一铁电材料，去除材料以暴露通孔的第二面，并在第二侧上形成第二铁电材料与通孔的第一侧相比具有不同的厚度。

25. 发明授权

US08830723B2 Method of driving nonvolatile semiconductor device 有权
标题翻译：驱动非易失性半导体器件的方法
公开(公告)号：US08830723B2
公开(公告)日：2014-09-09
申请号：US14030619
申请日：2013-09-18
申请人： Panasonic Corporation
发明人： Yukihiro Kaneko
IPC分类号： G11C11/22 , G11C11/56 , H01L29/78 , H01L29/51 , H01L21/28 , G11C13/00 , G11C5/02
CPC分类号： G11C11/2275 , G11C5/025 , G11C11/22 , G11C11/5657 , G11C2013/0092 , H01L21/28291 , H01L29/516 , H01L29/78391 , H04L29/12
摘要： Pulse voltages V1 and V2 are applied to the first upper gate electrode and the second upper gate electrode, respectively, for a period T1 which is shorter than a period necessary to invert all the polarizations included in the ferroelectric film, while voltages Vs, Vd, and V3 are applied to the source electrode, the drain electrode, and the lower gate electrode film, respectively, so as to increase the values of the widths WRH1 and WRH2 and so as to decrease the value of the width WRL. The pulse voltages V1 and V2 have a smaller voltage than a voltage necessary to invert all the polarizations included in the ferroelectric film. The voltage Vs, the voltage Vd, the voltage V3, the pulse voltage V1, and the pulse voltage V2 satisfy the following relationship: Vs, Vd, V3
摘要翻译：脉冲电压V1和V2分别施加到第一上栅极电极和第二上栅电极，周期T1短于反转铁电体中包含的所有极化所需的周期，同时电压Vs，Vd，并且V3分别施加到源电极，漏电极和下栅极电极膜，以便增加宽度WRH1和WRH2的值，并且减小宽度WRL的值。脉冲电压V1和V2具有比包含在铁电体膜中的所有极化反转所必需的电压更小的电压。电压Vs，电压Vd，电压V3，脉冲电压V1，脉冲电压V2满足Vs，Vd，V3

26. 发明授权

US08760907B2 Analog memories utilizing ferroelectric capacitors 有权
标题翻译：使用铁电电容器的模拟存储器
公开(公告)号：US08760907B2
公开(公告)日：2014-06-24
申请号：US12956845
申请日：2010-11-30
申请人： Joseph T. Evans, Jr. , Calvin B. Ward
发明人： Joseph T. Evans, Jr. , Calvin B. Ward
IPC分类号： G11C11/22
CPC分类号： G11C11/221 , G11C11/2259 , G11C11/2273 , G11C11/2275 , G11C11/2293 , G11C11/5657 , G11C27/005
摘要： A ferroelectric memory having a plurality of ferroelectric memory cells, each ferroelectric memory cell including a ferroelectric capacitor is disclosed. The ferroelectric memory includes read and write lines and a plurality of ferroelectric memory cell select buses, one select bus corresponding to each of the ferroelectric memory cells. Each of the ferroelectric memory cells includes first and second gates for connecting the ferroelectric memory cell to the read line and the write line, respectively, in response to signals on the ferroelectric memory cell select bus corresponding to that ferroelectric memory cell. A write circuit causes a charge to be stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the write line, the charge having a value determined by a data value having at least three states. A read circuit measures the charge stored in the ferroelectric capacitor of the ferroelectric memory cell currently connected to the read line to generate an output value, the output value corresponding to one of the states.
摘要翻译：公开了具有多个铁电存储单元的铁电存储器，每个强电介质存储单元包括铁电电容器。铁电存储器包括读写线和多个铁电存储器单元选择总线，每个铁电存储单元相应的一个选择总线。每个铁电存储单元包括用于响应于与该铁电存储单元相对应的强电介质存储单元选择总线上的信号而分别将铁电存储单元连接到读取线和写入线的第一和第二栅极。写入电路使电荷存储在当前连接到写入线的强电介质存储单元的铁电电容器中，电荷具有由具有至少三个状态的数据值确定的值。读取电路测量存储在当前连接到读取线的铁电存储器单元的铁电电容器中的电荷，以产生与其中一个状态对应的输出值。

27. 发明授权

US08154002B2 Nanoscale wire-based data storage 有权
标题翻译：基于纳米线的数据存储
公开(公告)号：US08154002B2
公开(公告)日：2012-04-10
申请号：US11792444
申请日：2005-12-06
申请人： Charles M. Lieber , Yue Wu , Hao Yan
发明人： Charles M. Lieber , Yue Wu , Hao Yan
IPC分类号： H01L47/00
CPC分类号： H01L29/0665 , B82Y10/00 , B82Y30/00 , G11C11/22 , G11C11/223 , G11C11/54 , G11C11/56 , G11C11/5657 , G11C13/003 , G11C13/025 , G11C2213/16 , G11C2213/17 , G11C2213/18 , G11C2213/75 , G11C2213/77 , H01L29/0673 , H01L29/068 , H01L29/78391
摘要： The present invention generally relates to nanotechnology and submicroelectronic devices that can be used in circuitry and, in some cases, to nanoscale wires and other nanostructures able to encode data. One aspect of the invention provides a nanoscale wire or other nanostructure having a region that is electrically-polarizable, for example, a nanoscale wire may comprise a core and an electrically-polarizable shell. In some cases, the electrically-polarizable region is able to retain its polarization state in the absence of an external electric field. All, or only a portion, of the electricallypolarizable region may be polarized, for example, to encode one or more bits of data. In one set of embodiments, the electrically-polarizable region comprises a functional oxide or a ferroelectric oxide material, for example, BaTiO3, lead zirconium titanate, or the like. In some embodiments, the nanoscale wire (or other nanostructure) may further comprise other materials, for example, a separation region separating the electrically polarizable region from other regions of the nanoscale wire. For example, in a nanoscale wire, one or more intermediate shells may separate the core from the electrically polarizable shell.
摘要翻译：本发明一般涉及纳米技术和亚微米电子器件，其可用于电路中，并且在一些情况下可用于能够对数据进行编码的纳米线和其他纳米结构。本发明的一个方面提供了具有可电极化的区域的纳米级线或其它纳米结构，例如，纳米线可以包括芯和电可极化的壳。在一些情况下，电极化区域能够在没有外部电场的情况下保持其极化状态。可电极化区域的全部或仅一部分可以被极化，例如编码一个或多个数据位。在一组实施方案中，电极化区域包括功能氧化物或铁电氧化物材料，例如BaTiO 3，钛酸铅锆等。在一些实施例中，纳米级线（或其他纳米结构）可以进一步包括其它材料，例如将电可极化区域与纳米级线材的其它区域分离的分离区域。例如，在纳米尺寸的线中，一个或多个中间壳可以将芯与电可极化壳分离。

28. 发明申请

US20110182102A1 SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件
公开(公告)号：US20110182102A1
公开(公告)日：2011-07-28
申请号：US12730089
申请日：2010-03-23
申请人： Yoshihiro MINAMI
发明人： Yoshihiro MINAMI
IPC分类号： G11C11/22 , G11C7/00
CPC分类号： H01L21/84 , G11C11/22 , G11C11/223 , G11C11/5657 , G11C2211/562 , G11C2211/5648 , H01L27/10802 , H01L27/1159 , H01L29/6684 , H01L29/78391 , H01L29/7841
摘要： A memory includes memory cells on a semiconductor layer, in which each of the memory cells includes a source layer and a drain layer in the semiconductor layer; an electrically floating body region provided in the semiconductor layer between the source layer and the drain layer and configured to accumulate or discharge electric charges in order to store logical data; a gate dielectric film provided on the body region and comprising a ferroelectric film with polarization characteristics; and a gate electrode provided on the gate dielectric film above the body region, wherein each memory cell stores a plurality of logical data depending on an amount of electric charges accumulated in the body region and on a polarization state of the ferroelectric film.
摘要翻译：存储器包括半导体层上的存储单元，其中每个存储单元包括半导体层中的源极层和漏极层; 电浮置体区域，设置在所述源极层和漏极层之间的所述半导体层中，并且被配置为积累或放电电荷以便存储逻辑数据; 设置在所述本体区域上并具有极化特性的铁电体膜的栅极电介质膜; 以及设置在所述体区域上方的所述栅极电介质膜上的栅电极，其中，每个存储单元根据所述体区中累积的电荷量和所述强电介质膜的极化状态来存储多个逻辑数据。

29. 发明申请

US20100157641A1 MEMORY DEVICE WITH ADAPTIVE CAPACITY 有权
标题翻译：具有适应能力的存储器件
公开(公告)号：US20100157641A1
公开(公告)日：2010-06-24
申请号：US12063544
申请日：2007-05-10
申请人： Ofir Shalvi , Dotan Sokolov , Ariel Maislos , Zeev Cohen , Eyal Gurgi , Gil Semo
发明人： Ofir Shalvi , Dotan Sokolov , Ariel Maislos , Zeev Cohen , Eyal Gurgi , Gil Semo
IPC分类号： G11C27/00 , G11C8/00 , G11C7/00
CPC分类号： G11C16/349 , G06F2212/7205 , G06F2212/7206 , G11C11/56 , G11C11/5607 , G11C11/5621 , G11C11/5628 , G11C11/5642 , G11C11/565 , G11C11/5657 , G11C11/5671 , G11C11/5678 , G11C27/005 , G11C2211/5621 , G11C2211/5641
摘要： A method for data storage in a memory (28) that includes a plurality of analog memory cells (32) includes estimating respective achievable storage capacities of the analog memory cells. The memory cells are assigned respective storage configurations defining quantities of data to be stored in the memory cells based on the estimated achievable capacities. The data is stored in the memory cells in accordance with the respective assigned storage configurations. The achievable storage capacities of the analog memory cells are re-estimated after the memory has been installed in a host system and used for storing the data in the host system. The storage configurations are modified responsively to the re-estimated achievable capacities.
摘要翻译：一种用于在包括多个模拟存储器单元（32）的存储器（28）中的数据存储的方法包括估计模拟存储器单元的各个可实现的存储容量。根据估计的可实现的容量，为存储器单元分配相应的存储配置，其定义要存储在存储器单元中的数据量。数据根据相应的分配的存储配置存储在存储器单元中。在存储器已经安装在主机系统中并用于在主机系统中存储数据之后，重新估计模拟存储器单元的可实现的存储容量。存储配置根据重新估计的可实现容量进行修改。

30. 发明授权

US07352619B2 Electronic memory with binary storage elements 失效
标题翻译：具有二进制存储元件的电子存储器
公开(公告)号：US07352619B2
公开(公告)日：2008-04-01
申请号：US11292741
申请日：2005-12-02
申请人： Iu-Meng Tom Ho
发明人： Iu-Meng Tom Ho
IPC分类号： G11C16/04
CPC分类号： G11C11/56 , G11C7/1006 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C11/16 , G11C11/22 , G11C11/4094 , G11C11/4097 , G11C11/5607 , G11C11/5621 , G11C11/565 , G11C11/5657 , G11C11/5678 , G11C13/0004 , G11C16/0408 , G11C16/0416 , G11C16/0441 , G11C16/0491 , G11C2211/4013 , G11C2211/5641 , H01L29/785
摘要： An electronic memory using true and complementary dual bit lines and dual binary storage elements cell architecture comprising a memory cell pair with four binary storage elements with each memory cell pair capable of existing in up to sixteen electronic memory states. The four binary storage elements together, normally used to store two true and complementary data bits, are used to store two, three, or four data bits depending on the noise margin allowed and bit width selection. The memory can be ferroelectric memory FeRAM, a flash memory, a ROM, a dynamic memory DRAM, an OUM, a MRAM, a NAND memory, or a NOR memory.
摘要翻译：一种使用真实且互补的双位线和双二进制存储元件的电子存储器单元架构，其包括具有四个二进制存储元件的存储器单元对，每个存储器单元对能够存在多达十六个电子存储器状态。通常用于存储两个真实和互补数据位的四个二进制存储元件一起用于存储两个，三个或四个数据位，这取决于允许的噪声容限和位宽选择。存储器可以是铁电存储器FeRAM，闪速存储器，ROM，动态存储器DRAM，OUM，MRAM，NAND存储器或NOR存储器。

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