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21. 发明申请

US20140306972A1 Language Level Support for Shared Virtual Memory 审中-公开
标题翻译：共享虚拟内存的语言级支持
公开(公告)号：US20140306972A1
公开(公告)日：2014-10-16
申请号：US14173071
申请日：2014-02-05
申请人： Xiaocheng Zhou , Shoumeng Yan , Ying Gao , Hu Chen , Peinan Zhang , Mohan Rajagopalan , Avi Mendelson , Bratin Saha
发明人： Xiaocheng Zhou , Shoumeng Yan , Ying Gao , Hu Chen , Peinan Zhang , Mohan Rajagopalan , Avi Mendelson , Bratin Saha
IPC分类号： G06T1/60
CPC分类号： G06F9/544 , G06F12/0815 , G06F12/084 , G06F12/1009 , G06F12/1063 , G06F12/1072 , G06F12/1081 , G06F12/109 , G06F2212/161 , G06F2212/622 , G06F2212/656 , G06F2212/657 , G06F2212/682 , G06T1/20 , G06T1/60
摘要： Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.
摘要翻译：本发明的实施例提供对CPU-GPU平台的语言支持。在一个实施例中，可以在CPU和GPU两者上灵活地执行代码。 CPU代码可以将内核卸载到GPU。该内核可能会调用CPU上的预先存在的库，或者调用其他CPU函数。这允许构建应用程序，而不需要重新编译整个调用链。此外，在一个实施例中，数据可以在CPU和GPU之间无缝共享。这包括共享可能具有虚拟功能的对象。因此，如果CPU或GPU调用虚拟功能，这些实施例可以确保在CPU或GPU上调用正确的虚拟功能。

22. 发明申请

US20140223103A1 PERSISTENT MEMORY FOR PROCESSOR MAIN MEMORY 有权
标题翻译：用于处理器主存储器的唯一存储器
公开(公告)号：US20140223103A1
公开(公告)日：2014-08-07
申请号：US14245916
申请日：2014-04-04
申请人： MICRON TECHNOLOGY, INC.
发明人： JOHN RUDELIC , AUGUST CAMBER , MOSTAFA NAGUIB ABDULLA
IPC分类号： G06F12/08
CPC分类号： G06F12/084 , G06F12/0811 , G06F12/0895 , G06F12/1027 , G06F13/1694 , G06F2212/2022 , G06F2212/283 , G06F2212/314 , G06F2212/682 , G11C11/005
摘要： Subject matter disclosed herein relates to a system of one or more processors that includes persistent memory.
摘要翻译：本文公开的主题涉及包括持久存储器的一个或多个处理器的系统。

23. 发明申请

US20140129798A1 REDUCING MICROPROCESSOR PERFORMANCE LOSS DUE TO TRANSLATION TABLE COHERENCY IN A MULTI-PROCESSOR SYSTEM 有权
标题翻译：减少多处理器系统中的翻译表格的微处理器性能损失
公开(公告)号：US20140129798A1
公开(公告)日：2014-05-08
申请号：US13667671
申请日：2012-11-02
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Joerg Deutschle , Ute Gaertner , Lisa C. Heller
IPC分类号： G06F12/10
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/682
摘要： A translation lookaside buffer coherency unit with Emulated Purge (TCUEP) translates a first virtual address for a first instruction into a first physical address. The TCUEP detects a multi-processor coherency operation that will cause hit suppression for certain entries in a TLB and purging of certain entries in the TLB. The TCUEP translates a second virtual address for a second instruction into a second physical address and stores the second physical address in a second entry in the TLB. The TCUEP configures a second marker in the second entry to indicate that the hit suppression is not allowed for the second entry, and that the purging is not allowed for the second entry. The TCUEP receives a first address translation request that indicates a hit in the second entry. The TCUEP resolves the first address translation request by returning the second physical address.
摘要翻译：具有仿真清除（TCUEP）的翻译后备缓冲区一致性单元将用于第一指令的第一虚拟地址转换为第一物理地址。 TCUEP检测多处理器一致性操作，这将导致对TLB中的某些条目的打击抑制以及TLB中某些条目的清除。 TCUEP将第二指令的第二虚拟地址转换为第二物理地址，并将第二物理地址存储在TLB中的第二条目中。 TCUEP在第二个条目中配置第二个标记，以指示第二个条目不允许命中抑制，而第二个条目不允许清除。 TCUEP接收第一个地址转换请求，指示第二个条目中的命中。 TCUEP通过返回第二个物理地址来解析第一个地址转换请求。

24. 发明申请

US20140089680A1 SECURE PROCESSOR AND A PROGRAM FOR A SECURE PROCESSOR 有权
公开(公告)号：US20140089680A1
公开(公告)日：2014-03-27
申请号：US14091483
申请日：2013-11-27
申请人： Fujitsu Semiconductor Limited
发明人： Seiji GOTO , Jun Kamada , Taijji Tamiya
IPC分类号： G06F21/71 , G06F12/14
CPC分类号： G06F21/70 , G06F12/1027 , G06F12/1408 , G06F13/24 , G06F21/52 , G06F21/53 , G06F21/554 , G06F21/575 , G06F21/64 , G06F21/71 , G06F21/72 , G06F21/74 , G06F2212/1052 , G06F2212/682
摘要： The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

25. 发明申请

US20140075151A1 DETECTION OF CONFLICTS BETWEEN TRANSACTIONS AND PAGE SHOOTDOWNS 有权
标题翻译：检测交易与信息页之间的冲突
公开(公告)号：US20140075151A1
公开(公告)日：2014-03-13
申请号：US13606743
申请日：2012-09-07
申请人： Harold W. Cain, III , Hung Q. Le , Bryan Lloyd , Shih-Hsiung Tung
发明人： Harold W. Cain, III , Hung Q. Le , Bryan Lloyd , Shih-Hsiung Tung
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/682 , G06F2212/683
摘要： There is provided a method for detecting a conflict between a transaction and a TLB (Translation Lookaside Buffer) shootdown in a transactional memory in which a TLB shootdown operation message is received by a processor to invalidate at least one entry in a TLB of the processor corresponding to at least one page. The processor tracks pages touched by the transaction. The processor determines whether the received TLB shootdown operation message is associated with one of the touched pages. The processor aborts the transaction in response to determining that the received TLB shootdown operation message is associated with one of the touched pages.
摘要翻译：提供了一种用于检测事务和事务存储器中的TLB（翻译后备缓冲器）冲突之间的冲突的方法，其中处理器接收到TLB击倒操作消息以使处理器的TLB中的至少一个条目相应对应至少一页。处理器跟踪事务触摸的页面。处理器确定接收的TLB拍摄操作消息是否与所触摸的页面中的一个相关联。响应于确定接收到的TLB击倒操作消息与所触摸的页面之一相关联，处理器中止该事务。

26. 发明授权

US07631147B2 Efficient flushing of translation lookaside buffers in a multiprocessor environment 有权
标题翻译：在多处理器环境中高效地刷新翻译后备缓冲区
公开(公告)号：US07631147B2
公开(公告)日：2009-12-08
申请号：US11635105
申请日：2006-12-06
申请人： Shuvabrata Ganguly
发明人： Shuvabrata Ganguly
IPC分类号： G06F12/06
CPC分类号： G06F12/1027 , G06F2212/151 , G06F2212/682
摘要： Various operations are disclosed for improving the operational efficiency of address mapping caches, such as translation lookaside buffers, in a multiprocessor environment. When an address mapping translation is invalidated, unnecessary address mapping cache flushes are avoided by signaling only those processors operating in a virtual machine monitor mode to flush their address mapping caches. Address mapping cache flushes for processors operating in guest modes are postponed until the processor enters a virtual machine monitor mode. Optionally, a counter is maintained for each processor and incremented each time the processor enters virtual machine monitor mode. When an address mapping cache is invalidated, a snapshot of the counter values is stored. When an new address translation for an invalidated address translation is requested, the snapshot is compared with the current value of a counter to determine whether the address mapping cache associated with the counter has been flushed since the invalidation.
摘要翻译：公开了用于在多处理器环境中提高地址映射高速缓存（例如，翻译后备缓冲器）的操作效率的各种操作。当地址映射转换无效时，通过仅信号通过以虚拟机监视器模式操作的处理器来刷新其地址映射高速缓存来避免不必要的地址映射缓存刷新。在访客模式下运行的处理器的地址映射缓存刷新推迟到处理器进入虚拟机监视模式。可选地，为每个处理器维护计数器并且每当处理器进入虚拟机监视器模式时递增计数器。当地址映射缓存无效时，存储计数器值的快照。当请求无效地址转换的新地址转换时，将快照与计数器的当前值进行比较，以确定与该计数器相关联的地址映射缓存是否已被无效化。

27. 发明授权

US07543291B2 Processor purging system and method 有权
标题翻译：处理器清洗系统及方法
公开(公告)号：US07543291B2
公开(公告)日：2009-06-02
申请号：US10632772
申请日：2003-08-01
申请人： Gregg Bernard Lesartr , Douglas Shelborn Stirrett
发明人： Gregg Bernard Lesartr , Douglas Shelborn Stirrett
IPC分类号： G06F9/46 , G06F9/26 , G06F9/34
CPC分类号： G06F12/1027 , G06F2212/682
摘要： A processor purging system comprising a translation lookaside buffer (TLB) having a plurality of translation pairs, at least one memory cache, and logic configured to detect whether at least one of the translation pairs corresponds to a purge signal. The logic is further configured to assert a purge detection signal indicative of whether at least one translation pair corresponds to the purge signal and to determine, based upon the purge detection signal, whether to search the memory cache for a translation pair corresponding to the purge signal.
摘要翻译：一种处理器清洗系统，包括具有多个转换对的翻译后备缓冲器（TLB），至少一个存储器高速缓存和被配置为检测所述转换对中的至少一个对应于清除信号的逻辑。该逻辑被进一步配置为断言指示是否至少一个转换对对应于清除信号的清除检测信号，并且基于清除检测信号确定是否搜索对应于清除信号的转换对的存储器高速缓存。

28. 发明授权

US07536531B2 Scaling address space utilization in a multi-threaded, multi-processor computer 失效
标题翻译：在多线程多处理器计算机中扩展地址空间利用率
公开(公告)号：US07536531B2
公开(公告)日：2009-05-19
申请号：US11828104
申请日：2007-07-25
申请人： Christopher F. McDonald , Bruce Mealey , Mark Douglass Rogers
发明人： Christopher F. McDonald , Bruce Mealey , Mark Douglass Rogers
IPC分类号： G06F9/26 , G06F9/34
CPC分类号： G06F12/1072 , G06F12/1036 , G06F12/109 , G06F2212/682
摘要： Scaling address space utilization in a multi-threaded, multi-processor computer, including attaching to process memory of an exporting process a region of virtual memory specified in a cross-memory descriptor; requesting, by an importing thread of an importing process having process memory, a lightweight attachment of the region of virtual memory to the process memory of the importing process for exclusive use by the importing thread; and lightweight attaching, by an operating system to the process memory of the importing process, the region of virtual memory for exclusive use by the importing thread.
摘要翻译：在多线程多处理器计算机中缩放地址空间利用率，包括将导出进程的进程存储器附加到跨存储器描述符中指定的虚拟存储器区域; 通过具有进程存储器的导入过程的导入线程请求虚拟内存区域到进口流程的进程存储器的轻量级附件，以供导入线程专用; 并且通过操作系统轻松地将进口流程的进程存储器附加到导入线程专用的虚拟内存区域。

29. 发明申请

US20080016315A1 Tagged translation lookaside buffers in a hypervisor computing environment 有权
标题翻译：管理程序计算环境中标记的翻译后备缓冲区
公开(公告)号：US20080016315A1
公开(公告)日：2008-01-17
申请号：US11484949
申请日：2006-07-12
申请人： Ernest S. Cohen , Matthew D. Hendel
发明人： Ernest S. Cohen , Matthew D. Hendel
IPC分类号： G06F12/00
CPC分类号： G06F12/1036 , G06F2212/682
摘要： Tagged translation lookaside buffer consistency is enabled in the presence of a hypervisor of a virtual machine computing environment, in which multiple processes of multiple logical processors of guests are hosted by a virtual machine monitor or hypervisor component. The virtual machine monitor or hypervisor component maintains tagged TLB data associated with the plurality of processes on behalf of each of the plurality of logical processors, thereby ensuring consistency of the tagged TLB data across all of the plurality of processes.
摘要翻译：在存在虚拟机计算环境的虚拟机管理程序的情况下启用标记的翻译后备缓冲器一致性，其中由虚拟机监视器或管理程序组件托管来宾的多个逻辑处理器的多个进程。虚拟机监视器或管理程序组件代表多个逻辑处理器中的每一个维护与多个进程相关联的标记的TLB数据，从而确保所标记的TLB数据跨越所有多个进程的一致性。

30. 发明授权

US07234038B1 Page mapping cookies 有权
标题翻译：页面映射Cookie
公开(公告)号：US07234038B1
公开(公告)日：2007-06-19
申请号：US10857149
申请日：2004-05-28
申请人： Paul Durrant
发明人： Paul Durrant
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/1072 , G06F2212/682
摘要： A method for managing virtual memory including placing a first virtual memory page in a physical memory page to create a virtual-to-physical memory mapping, associating a first page mapping cookie value with the virtual-to-physical memory mapping, determining whether the virtual-to-physical memory mapping is valid using the first page mapping cookie value, and performing a memory operation addressing the first virtual memory page if the virtual-to-physical memory mapping is valid.
摘要翻译：一种用于管理虚拟存储器的方法，包括将第一虚拟存储器页面放置在物理存储器页面中以创建虚拟到物理存储器映射，将第一页面映射cookie值与虚拟到物理存储器映射相关联，确定虚拟到物理存储器映射物理内存映射使用第一页映射cookie值有效，并且如果虚拟到物理内存映射有效，则执行寻址第一虚拟内存页的存储器操作。

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