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21. 发明授权

US5689647A Parallel computing system with processing element number setting mode and shortest route determination with matrix size information 失效
标题翻译：具有处理元件数设定模式的并行计算系统和矩阵尺寸信息的最短路由确定
公开(公告)号：US5689647A
公开(公告)日：1997-11-18
申请号：US551694
申请日：1995-11-01
申请人： Hiroki Miura
发明人： Hiroki Miura
IPC分类号： G06F9/44 , G06F15/173 , G06F15/80
CPC分类号： G06F15/8092 , G06F15/17337 , G06F15/8023 , G06F15/82 , G06F9/4436
摘要： A parallel computer system includes a plurality of processing elements each including a network control unit and a data processing unit. The network control unit of each processing element includes a north, east, west and south ports to each of which a row and column communication lines are connected so as to construct a torus mesh network. A specific mode flag which is set by a reset signal from a host computer coupled to the network and a number register are formed in the data processing unit. If a packet is sent to the network from the host computer when the specific mode flag is set, in the processing element which received the packet, the processing element number included in the packet is set in the number register and the specific mode flag is reset so that the processing element can be identified by that processing element number in a normal mode. In the normal mode, the packet is inputted to the data processing unit when the processing element number of the packet is coincident with its own processing element number. If not coincident, the packet is outputted to a port determined by a predetermined algorithm so that the packet can be transferred to an addressed processing element on the network with the shortest distance.
摘要翻译：并行计算机系统包括多个处理单元，每个处理单元包括网络控制单元和数据处理单元。每个处理元件的网络控制单元包括北，东，西和南端口，每个端口连接一行和一列通信线路，以构成环面网状网络。在数据处理单元中形成由来自耦合到网络的主计算机的复位信号和数字寄存器设置的特定模式标志。如果在设定了特定模式标志的情况下从主计算机发送数据包，则在接收到数据包的处理单元中，包含在数据包中的处理单元号被设定在数字寄存器中，特定模式标志被复位使得处理元件可以通过正常模式中的处理元件号来识别。在正常模式下，当分组的处理单元号与其自身的处理单元号一致时，分组输入到数据处理单元。如果不一致，则将分组输出到由预定算法确定的端口，使得分组可以以最短距离传送到网络上的寻址处理元件。

22. 发明授权

US5664134A Data processor for performing a comparison instruction using selective enablement and wired boolean logic 失效
标题翻译：用于使用选择性启用和有线布尔逻辑执行比较指令的数据处理器
公开(公告)号：US5664134A
公开(公告)日：1997-09-02
申请号：US393602
申请日：1995-02-23
申请人： Michael G. Gallup , L. Rodney Goke , Robert W. Seaton, Jr.
发明人： Michael G. Gallup , L. Rodney Goke , Robert W. Seaton, Jr.
IPC分类号： G06F7/38 , G06F7/483 , G06F7/499 , G06F7/506 , G06F7/544 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/45 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16 , G06N3/063 , G06F17/00
CPC分类号： G06F7/57 , G06F15/17381 , G06F15/78 , G06F15/8023 , G06F15/8092 , G06F7/544 , G06F8/445 , G06F8/447 , G06F9/30 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30079 , G06F9/30083 , G06F9/30094 , G06F9/30101 , G06F9/30116 , G06F9/3802 , G06F9/3812 , G06F9/3851 , G06F9/3867 , G06F9/3877 , G06F9/3887 , G06F9/3889 , G06N3/063 , G06F7/49921
摘要： A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.
摘要翻译：数据处理系统（55）及其方法包括一个或多个数据处理器（10）。数据处理器（10）能够执行向量运算和标量运算。使用单个微定序器（22），数据处理器（10）能够执行向量指令和标量指令。数据处理器（10）还具有能够存储向量操作数和标量操作数的存储器电路（14）。

23. 发明授权

US5628025A Timing and control circuit and method for a synchronous vector processor 失效
标题翻译：同步矢量处理器的时序控制电路及方法
公开(公告)号：US5628025A
公开(公告)日：1997-05-06
申请号：US483778
申请日：1995-06-07
申请人： Moo-Taek Chung , Jim Childers , Hiroshi Miyaguchi , Manfred Becker
发明人： Moo-Taek Chung , Jim Childers , Hiroshi Miyaguchi , Manfred Becker
IPC分类号： F02B75/02 , G06F15/80 , H04N5/14 , H04N5/775 , H04N9/64 , H04N9/79 , G06F3/14
CPC分类号： G06F15/8092 , H04N5/775 , F02B2075/027 , H04N5/14 , H04N9/641 , H04N9/79
摘要： A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.
摘要翻译：一种用于具有以线性阵列组织的多个一位处理器元件的同步矢量处理器（SVP）装置的定时和控制电路和方法。该电路包括主控制器电路，垂直定时发生器电路，恒定发电机电路，水平定时发生器电路和指令发生器电路。

24. 发明授权

US5572689A Data processing system and method thereof 失效
标题翻译：数据处理系统及其方法
公开(公告)号：US5572689A
公开(公告)日：1996-11-05
申请号：US408045
申请日：1995-03-21
申请人： Michael G. Gallup , L. Rodney Goke , Robert W. Seaton, Jr. , Terry G. Lawell , Stephen G. Osborn , Thomas J. Tomazin
发明人： Michael G. Gallup , L. Rodney Goke , Robert W. Seaton, Jr. , Terry G. Lawell , Stephen G. Osborn , Thomas J. Tomazin
IPC分类号： G06F7/38 , G06F7/483 , G06F7/499 , G06F7/506 , G06F7/544 , G06F7/57 , G06F9/30 , G06F9/302 , G06F9/318 , G06F9/32 , G06F9/38 , G06F9/45 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16 , G06N3/063 , G06F9/315
CPC分类号： G06F7/57 , G06F15/17381 , G06F15/78 , G06F15/8023 , G06F15/8092 , G06F7/544 , G06F8/445 , G06F8/447 , G06F9/30 , G06F9/30014 , G06F9/30021 , G06F9/30036 , G06F9/30065 , G06F9/30072 , G06F9/30079 , G06F9/30083 , G06F9/30094 , G06F9/30101 , G06F9/30116 , G06F9/3802 , G06F9/3812 , G06F9/3851 , G06F9/3867 , G06F9/3877 , G06F9/3887 , G06F9/3889 , G06N3/063 , G06F7/49921
摘要： A data processing system (55) and method thereof includes one or more data processors (10). Data processor (10) is capable of performing both vector operations and scalar operations. Using a single microsequencer (22), data processor (10) is capable of executing both vector instructions and scalar instructions. Data processor (10) also has a memory circuit (14) capable of storing both vector operands and scalar operands.
摘要翻译：数据处理系统（55）及其方法包括一个或多个数据处理器（10）。数据处理器（10）能够执行向量运算和标量运算。使用单个微定序器（22），数据处理器（10）能够执行向量指令和标量指令。数据处理器（10）还具有能够存储向量操作数和标量操作数的存储器电路（14）。

25. 发明授权

US5524255A Method and apparatus for accessing global registers in a multiprocessor system 失效
标题翻译：用于在多处理器系统中访问全局寄存器的方法和装置
公开(公告)号：US5524255A
公开(公告)日：1996-06-04
申请号：US379123
申请日：1995-01-27
申请人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
发明人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/17 , G06F15/173 , G06F15/78 , G06F15/80 , G06F15/163
CPC分类号： G06F9/3004 , G06F15/17 , G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30043 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： A global register system provides communication and coordination among a plurality of processors sharing a common memory in a multiprocessor system which access one or more registers within a shared resource circuit that is separate from the common memory and is symmetrically accessible by the plurality of processors in the multiprocessor system. The global register system is accessed by direct addresses determined by the processor from a previously assigned indirect address and an instruction accessing the data stored in global registers. Arithmetic or logic operation on a data value stored in a selected one of the registers are performed by the global register system independent from the processors or the common memory in order to modify the data value in the selected global register as part of an atomic operation performed in response to a single read-and-modify instruction received from one of the processors.
摘要翻译：全局注册系统提供在多处理器系统中共享公共存储器的多个处理器之间的通信和协调，多处理器系统访问共享资源电路内的一个或多个与公共存储器分离的寄存器，并且可由多个处理器对称地访问多处理器系统全局寄存器系统由处理器从先前分配的间接地址确定的直接地址和访问存储在全局寄存器中的数据的指令访问。存储在所选择的一个寄存器中的数据值的算术或逻辑运算由独立于处理器或公共存储器的全局寄存器系统执行，以便修改所选择的全局寄存器中的数据值，作为执行的原子操作的一部分响应于从一个处理器接收的单个读取和修改指令。

26. 发明授权

US5452425A Sequential constant generator system for indicating the last data word by using the end of loop bit having opposite digital state than other data words 失效
标题翻译：顺序常数发生器系统，用于通过使用与其他数据字相反的数字状态的循环位的结尾来指示最后的数据字
公开(公告)号：US5452425A
公开(公告)日：1995-09-19
申请号：US163606
申请日：1993-12-07
申请人： Jim Childers , Hiroshi Miyaguchi , Peter Reinecke
发明人： Jim Childers , Hiroshi Miyaguchi , Peter Reinecke
IPC分类号： F02B75/02 , G06F15/80 , G06F9/26 , G06F9/06
CPC分类号： G06F15/8092 , F02B2075/027
摘要： A constant generator is described which provides a sequence of digital constants in a synchronous vector processor. The constant generator includes a constant loop memory for storing data words organized into a plurality of data constant patterns and an end of loop bit, a constant loop counter for supplying sequential addresses to the constant loop memory, and a constant loop counter controller for loading the counter with one of a set of predetermined starting addresses associated with a desired constant pattern stored in the constant loop memory. Additionally, a method of supplying a sequence of digital constants in said constant generator is disclosed and includes the steps of storing a plurality of data words in a plurality of constant patterns, where each constant pattern includes an end of loop bit, supplying an address to the constant loop memory and supplying sequential addresses to the constant loop memory.
摘要翻译：描述了在同步向量处理器中提供数字常数序列的常数发生器。常数发生器包括用于存储组织成多个数据常数模式和循环位结束的数据字的恒定循环存储器，用于向恒定循环存储器提供顺序地址的常数循环计数器和用于加载计数器与存储在恒定循环存储器中的期望常数模式相关联的一组预定起始地址中的一个。另外，公开了一种在所述常数发生器中提供数字常数序列的方法，包括以多个恒定模式存储多个数据字的步骤，其中每个常数模式包括循环位结束，向恒定循环存储器，并向恒定循环存储器提供顺序地址。

27. 发明授权

US5327541A Global rotation of data in synchronous vector processor 失效
标题翻译：同步矢量处理器中数据的全局旋转
公开(公告)号：US5327541A
公开(公告)日：1994-07-05
申请号：US887228
申请日：1992-05-18
申请人： Peter Reinecke , Jimmie D. Childers , Hiroshi Miyaguchi , Moo-Taek Chung
发明人： Peter Reinecke , Jimmie D. Childers , Hiroshi Miyaguchi , Moo-Taek Chung
IPC分类号： F02B75/02 , G06F15/80 , G06F12/00 , G06F15/76
CPC分类号： G06F15/8092 , G06F15/8015 , F02B2075/027
摘要： An apparatus and method for performing rotation of data in a register file memory. The apparatus utilizes a rotation address generator including rotation value, modulus, and offset registers, a comparator, a data selector, logic circuitry, and a subtractor. A predetermined area (P.times.Q) of the register file memory and a rotation value corresponding to the number of bits to be rotated in the rotation area is designated by an instruction program memory. An instruction decoder signals the register file, modulus register, rotation value register, and offset register of an impending rotation of data, thereby enabling loading of the modulus and rotation value registers and resetting of the offset register. A counter provides a relative address to the comparator and data selector. The comparator compares the relative address with the output of the modulus register, determining whether selected ones of the addressed register file locations fall inside or outside of the rotation area, and send an appropriate signal to the logic circuitry, an OR gate. This OR gate also receives a rotate or not-rotate signal. Consequently, either an absolute address equal to (the value of the relative address-2 * the offset value) mod (8 * the value in the modulus register) or equal to the relative address, based on predetermined conditions, is utilized to access rotationally data from the register file.
摘要翻译：一种用于在寄存器文件存储器中执行数据旋转的装置和方法。该装置使用包括旋转值，模数和偏移寄存器的旋转地址生成器，比较器，数据选择器，逻辑电路和减法器。由指令程序存储器指定寄存器文件存储器的预定区域（PxQ）和与旋转区域中要旋转的位数相对应的旋转值。指令译码器向数据的即将转动的寄存器文件，模数寄存器，旋转值寄存器和偏移寄存器发出信号，从而可以加载模数和旋转值寄存器以及复位偏移寄存器。计数器提供比较器和数据选择器的相对地址。比较器将相对地址与模数寄存器的输出进行比较，确定所寻址的寄存器文件位置中选定的位置是否位于旋转区域的内部或外部，并向OR逻辑电路发送适当的信号。该或门也接收旋转或非旋转信号。因此，利用等于（相对地址-2 *偏移值的值）mod（8 *模数寄存器中的值）或等于相对地址的绝对地址（基于预定条件）被旋转地访问来自寄存器文件的数据。

28. 发明授权

US5208914A Method and apparatus for non-sequential resource access 失效
标题翻译：用于非顺序资源访问的方法和装置
公开(公告)号：US5208914A
公开(公告)日：1993-05-04
申请号：US535786
申请日：1990-06-11
申请人： Jimmie R. Wilson , Douglas R. Beard , Steve S. Chen , Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , Alexander A. Silbey , Brian D. Vanderwarn
发明人： Jimmie R. Wilson , Douglas R. Beard , Steve S. Chen , Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , Alexander A. Silbey , Brian D. Vanderwarn
IPC分类号： G06F9/46 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F12/00 , G06F15/16 , G06F15/173 , G06F15/177 , G06F15/78 , G06F15/80
CPC分类号： G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/3013 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for non-sequential access to shared resources in a multiple requestor system uses a variety of tags to effectively re-order the data at its destination. In simplest form, the tag directs switching logic to where in a buffer to locate another tag for direction information or where in a buffer or processor (register) to put the response associated with the tag. For example, loading data from memory requires that the requestor provide a request signal, an address, and a request tag. The request signal validates the address and request tag. The address specifies the location of the requested data in memory. The request tag specifies where to put the data when it is returned to the processor. The switching logic for the requestor includes a tag queue for storing the request tags associated with the resource requests, logic means for associating the respective request tag from the tag queue with a resource response, and means for returning the resource response and respective request tag to the requestor. The switching logic associated with the shared resource includes switching means to route the request into and out of the shared resource, control logic to correctly route the request, logic to handle multiple decision requests, and logic to store or retrieve the ultimate data entity being requested.
摘要翻译：用于在多请求者系统中非顺序访问共享资源的方法和装置使用各种标签来有效地重新排序其目的地的数据。以最简单的形式，标签将切换逻辑引导到缓冲器中的哪个位置，以定位用于方向信息的另一个标签，或者在缓冲器或处理器（寄存器）中放置与标签相关联的响应的位置。例如，从存储器加载数据要求请求者提供请求信号，地址和请求标签。请求信号验证地址和请求标签。该地址指定所请求的数据在内存中的位置。请求标签指定在将数据返回到处理器时放置数据的位置。用于请求者的切换逻辑包括用于存储与资源请求相关联的请求标签的标记队列，用于将来自标签队列的相应请求标签与资源响应相关联的逻辑装置，以及用于将资源响应和相应请求标签返回到请求者。与共享资源相关联的切换逻辑包括将请求路由到共享资源和从共享资源引出的切换装置，控制逻辑以正确路由请求，处理多个决策请求的逻辑以及存储或检索被请求的最终数据实体的逻辑。

29. 发明授权

US5086498A Parallel computer with asynchronous communication facility 失效
标题翻译：具有异步通信设备的并行计算机
公开(公告)号：US5086498A
公开(公告)日：1992-02-04
申请号：US145614
申请日：1988-01-10
申请人： Teruo Tanaka , Naoki Hamanaka , Junji Nakagoshi , Koichiro Omoda , Shigeo Nagashima
发明人： Teruo Tanaka , Naoki Hamanaka , Junji Nakagoshi , Koichiro Omoda , Shigeo Nagashima
IPC分类号： G06F15/17 , G06F15/173 , G06F15/80 , G06F17/16
CPC分类号： G06F15/8092 , G06F15/17 , G06F15/173
摘要： In a multiprocessor digital computer system ID data, coupled with data for which inter-processor communication is desired, is communicated from one processor and held temporarily with data in a receiver buffer (associative memory) in a receiving processor. This ID is divided into main ID data MK and sub ID data SK. Main ID data MK is used for searching data from a receive buffer. The sub ID data SK are used as an ID of the data in the receive processor.
摘要翻译：在多处理器数字计算机系统ID数据中，与期望的处理器间通信的数据相耦合，从一个处理器传送并暂时保存在接收处理器中的接收缓冲器（关联存储器）中的数据。该ID被划分为主ID数据MK和子ID数据SK。主ID数据MK用于从接收缓冲器搜索数据。子ID数据SK用作接收处理器中的数据的ID。

30. 发明授权

US4901230A Computer vector multiprocessing control with multiple access memory and priority conflict resolution method 失效
标题翻译：具有多访问存储器和优先级冲突解决方法的计算机向量多处理控制
公开(公告)号：US4901230A
公开(公告)日：1990-02-13
申请号：US208809
申请日：1988-06-16
申请人： Steve S. Chen , Alan J. Schiffleger
发明人： Steve S. Chen , Alan J. Schiffleger
IPC分类号： G06F13/18 , G06F15/17 , G06F15/80 , G06F9/46 , G06F15/16
CPC分类号： G06F15/8092 , G06F13/18 , G06F15/17
摘要： A multiprocessing system and method for multiprocessing is disclosed. A pair of processors are provided, and each are connected to a central memory through a plurality of memory reference ports. The processors are further each connected to a plurality of shared registers which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit which senses and prioritizes conflicting references to the central memory. Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one I/O port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides that each register consist of at least two independently addressable memories, to deliver data to or accept data from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and facilitate multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.
摘要翻译：公开了一种用于多处理的多处理系统和方法。提供一对处理器，并且每个处理器通过多个存储器参考端口连接到中央存储器。处理器还进一步连接到多个共享寄存器，这些共享寄存器可以由任一处理器以与处理器内操作相称的速率直接寻址。共享寄存器包括用于保存标量和地址信息的寄存器以及用于保存用于协调通过共享寄存器传送信息的信息的寄存器。提供多端口存储器并且包括冲突解决电路，其感测并优先考虑对中央存储器的冲突引用。每个CPU通过三个端口与中央存储器连接，每个端口处理可以进行的几种不同类型的存储器引用的不同的端口。提供至少一个I / O端口以由处理器在中央存储器和外围存储设备之间传送信息时共享。还公开了用于向量处理计算机中的矢量寄存器设计，并且提供每个寄存器由至少两个可独立寻址的存储器组成，以向功能单元传送数据或从功能单元接收数据。多处理方法允许多处理器中的多任务处理，其中共享寄存器允许单个作业的不同作业或相关任务的独立任务并行运行，并且通过允许多个关键代码区域被独立同步来促进操作系统的多线程化。

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