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21. 发明申请

US20160110274A1 MICROCONTROLLER FAULT INJECTION METHOD AND SYSTEM 有权
标题翻译：微控制器故障注入方法和系统
公开(公告)号：US20160110274A1
公开(公告)日：2016-04-21
申请号：US14890200
申请日：2013-06-06
申请人： HITACHI, LTD.
发明人： Yasuhiro Ito , Yasuo SUGURE
IPC分类号： G06F11/263 , G06F11/26 , G06F11/22
CPC分类号： G06F11/263 , G06F11/22 , G06F11/2236 , G06F11/26 , G06F11/261
摘要： Temporary fault injection to existing hardware is performed using only software without changing an implementation of the hardware. A fault injection interrupt process starts on an operation of a CPU using an interrupt that is not used by software, and an internal state of hardware is updated to the same value as a result obtained when a fault has occurred during the interrupt process. A clock of the CPU during the interrupt process is accelerated so that a period of time of the interrupt process is smaller than a period of time until a fault becomes effective.
摘要翻译：对现有硬件的临时故障注入仅使用软件进行，而不改变硬件的实现。故障注入中断处理在使用软件不使用的中断的CPU的操作下开始，并且硬件的内部状态被更新为与在中断处理期间发生故障时获得的结果相同的值。在中断处理期间CPU的时钟被加速，使得中断处理的时间段小于直到故障生效的时间段。

22. 发明授权

US09310434B2 Scan topology discovery in target systems 有权
标题翻译：在目标系统中扫描拓扑发现
公开(公告)号：US09310434B2
公开(公告)日：2016-04-12
申请号：US14918854
申请日：2015-10-21
申请人： Texas Instruments Incorporated
发明人： Gary L. Swoboda
IPC分类号： G01R31/28 , G01R31/3177 , G01R31/3185
CPC分类号： G01R31/3177 , G01R31/31701 , G01R31/31713 , G01R31/31723 , G01R31/31727 , G01R31/318533 , G01R31/318538 , G01R31/318544 , G06F11/22 , G06F11/267 , G06F11/27 , G06F11/36 , G06F11/3656 , G06F2201/88 , H04L43/50
摘要： Topology discovery of a target system having a plurality of components coupled with a scan topology may be performed by driving a low logic value on the data input signal and a data output signal of the scan topology. An input data value and an output data value for each of the plurality of components is sampled and recorded. A low logic value is then scanned through the scan path and recorded at each component. The scan topology may be determined based on the recorded data values and the recorded scan values.
摘要翻译：可以通过驱动数据输入信号上的低逻辑值和扫描拓扑的数据输出信号来执行具有与扫描拓扑结合的多个分量的目标系统的拓扑发现。对多个分量中的每一个的输入数据值和输出数据值进行采样和记录。然后通过扫描路径扫描低逻辑值，并记录在每个组件上。可以基于记录的数据值和记录的扫描值来确定扫描拓扑。

23. 发明授权

US09286002B1 Dynamic restriping in nonvolatile memory systems 有权
标题翻译：非易失性存储器系统中的动态重新安装
公开(公告)号：US09286002B1
公开(公告)日：2016-03-15
申请号：US13841706
申请日：2013-03-15
申请人： Virident Systems Inc.
发明人： Vijay Karamcheti , Swamy Gowda , Rajendra Prasad Mishra , Shibabrata Mondal
IPC分类号： G06F12/00 , G06F3/06 , G06F11/18 , G11C29/00 , G06F11/22 , G06F11/20
CPC分类号： G06F3/064 , G06F3/0619 , G06F3/0629 , G06F3/0647 , G06F3/0653 , G06F3/0688 , G06F11/108 , G06F11/1096 , G06F11/18 , G06F11/20 , G06F11/22 , G06F2201/84 , G06F2211/1028 , G06F2211/1059 , G11C29/70 , G11C29/76 , G11C29/765
摘要： Data is stored as a first collection of memory blocks distributed across a first set of memory devices. It is determined that a first memory device in the first set is in a degraded state. Data is recovered corresponding to a first memory block in the first collection of memory blocks that is stored in the first memory device, which is configured to include a first number of memory blocks. The recovered data is stored in a second memory device as a new memory block, which is added to the first collection of memory blocks. The first memory device is removed from the first set and reconfigured with a second number of memory blocks that is less than the first number of memory blocks. Memory blocks in a second collection of memory blocks distributed across a second set of memory devices is stored in the reconfigured first memory device.
摘要翻译：数据被存储为分布在第一组存储器件上的存储块的第一集合。确定第一组中的第一存储器件处于劣化状态。数据被恢复对应于存储在第一存储器设备中的存储块的第一集合中的第一存储器块，其被配置为包括第一数量的存储器块。恢复的数据作为新的存储器块存储在第二存储器件中，其被添加到存储块的第一集合中。第一存储器件从第一组中移除并且被重新配置成小于第一数量的存储器块的第二数量的存储器块。分配在第二组存储器设备上的第二存储器块集合中的存储器块被存储在重新配置的第一存储器设备中。

24. 发明授权

US09274909B2 Method and apparatus for error management of an integrated circuit system 有权
标题翻译：集成电路系统的误差管理方法和装置
公开(公告)号：US09274909B2
公开(公告)日：2016-03-01
申请号：US14084222
申请日：2013-11-19
申请人： Scaleo Chip
发明人： Bruno Sallé
IPC分类号： G06F11/00 , G06F11/22 , G06F11/07
CPC分类号： G06F11/2236 , G06F11/0706 , G06F11/0781 , G06F11/22
摘要： An apparatus and method for error management in an integrated circuit system are presented. An error management unit (EMU) apparatus manages critical and non-critical errors that may be masked or non-masked. An EMU includes an EMU state machine, having a BOOT state, a CONFIG state, a FUNCT state, a WARNING state and an ERROR state. The method discloses transitions in the EMU state machine. While in the ERROR state an error reaction may be applied. The objective of the error reaction is to recover errors by software and hardware means. The EMU may further appropriately alert the system while in ERROR state and therefore be used as a safety mechanism permitting to collect error signals issued by fault detector units and can further cause action on faulty units for recovery purposes.
摘要翻译：提出了一种用于集成电路系统中的误差管理的装置和方法。错误管理单元（EMU）设备管理可能被屏蔽或未被屏蔽的关键和非关键错误。 EMU包括具有BOOT状态，CONFIG状态，FUNCT状态，WARNING状态和ERROR状态的EMU状态机。该方法公开了EMU状态机中的转换。当处于ERROR状态时，可能会应用错误反应。错误反应的目的是通过软件和硬件手段恢复错误。 EMU可以在错误状态下进一步适当地警告系统，因此用作安全机制，允许收集故障检测器单元发出的错误信号，并且可以进一步对故障单元采取行动以进行恢复。

25. 发明申请

US20160055047A1 PROCESSOR SYSTEM, ENGINE CONTROL SYSTEM AND CONTROL METHOD 有权
标题翻译：处理器系统，发动机控制系统和控制方法
公开(公告)号：US20160055047A1
公开(公告)日：2016-02-25
申请号：US14804970
申请日：2015-07-21
申请人： Renesas Electronics Corporation
发明人： Tatsushi Okamoto
IPC分类号： G06F11/07
CPC分类号： G06F11/079 , G06F11/0724 , G06F11/16 , G06F11/1641 , G06F11/1687 , G06F11/22 , G06F2201/845
摘要： A processor system includes a master processor that successively processes a plurality of tasks, a checker processor that successively processes at least one of the plurality of tasks, and a control circuit that performs control so that the checker processor operates when the master processor and the checker processor perform a lock-step operation, and the checker processor stops its operation when the master processor and the checker processor do not perform the lock-step operation, the lock-step operation being an operation in which each of the master and checker processors processes the same task, in which the control circuit performs control so that a period from when a task is processed by the lock-step operation to when another task is processed in the next lock-step operation is equal to or shorter than a maximum test period, the maximum test period being a test period acceptable to the processor system.
摘要翻译：处理器系统包括连续处理多个任务的主处理器，连续地处理多个任务中的至少一个任务的检查器处理器，以及执行控制的控制电路，以便当主处理器和检验器处理器执行锁定步骤操作，并且当主处理器和检查器处理器不执行锁定步骤操作时，检验器处理器停止其操作，该锁定步骤操作是主机和检查器处理器中的每个处理器相同的任务，其中控制电路进行控制，使得从下一个锁步骤操作中的任务被处理的时间段到在下一个锁步骤操作中的另一个任务被处理的时间段等于或小于最大测试周期最大测试周期是处理器系统可接受的测试周期。

26. 发明授权

US09239765B2 Application triggered state migration via hypervisor 有权
标题翻译：应用程序通过管理程序触发状态迁移
公开(公告)号：US09239765B2
公开(公告)日：2016-01-19
申请号：US12873052
申请日：2010-08-31
申请人： Frederick P. Block , Anjur S. Krishnakumar , Parameshwaran Krishnan , Navjot Singh , Shalini Yajnik
发明人： Frederick P. Block , Anjur S. Krishnakumar , Parameshwaran Krishnan , Navjot Singh , Shalini Yajnik
IPC分类号： G06F9/455 , G06F21/00 , G06F11/00 , G06F11/20 , G06F11/14 , G06F9/48 , G06F11/22
CPC分类号： G06F11/2046 , G06F9/45558 , G06F9/4881 , G06F11/1484 , G06F11/203 , G06F11/2043 , G06F11/22 , G06F21/00 , G06F2009/4557
摘要： Systems and methods that enable migration for state of an application, from a primary machine to a backup machine in platform virtualization systems. The migration employs a hybrid approach, wherein both a hypervisor, and an application itself determine states that are to migrate from the primary machine to the backup machine. Based on a direct communication between the application and the hypervisor—without assistance of local operating system—the hypervisor arranges for migration of the required states over to the backup virtual machine.
摘要翻译：能够在平台虚拟化系统中从主机到备份机的状态迁移的系统和方法。迁移采用混合方法，其中管理程序和应用程序本身都确定要从主机迁移到备份机的状态。基于应用程序和管理程序之间的直接通信 - 无需本地操作系统的帮助 - 管理程序将所需状态迁移到备份虚拟机。

27. 发明申请

US20150347037A1 VERIFICATION OF MANAGEMENT OF REAL STORAGE VIA MULTI-THREADED THRASHERS IN MULTIPLE ADDRESS SPACES 有权
标题翻译：通过多个地址空间中的多通道THRASHER实现真实存储的管理验证
公开(公告)号：US20150347037A1
公开(公告)日：2015-12-03
申请号：US14288979
申请日：2014-05-28
申请人： International Business Machines Corporation
发明人： Alfred F. Foster , Robert Miller, JR. , Thomas F. Rankin
IPC分类号： G06F3/06 , G06F12/02
CPC分类号： G06F3/0614 , G06F3/0604 , G06F3/0644 , G06F3/0659 , G06F3/0665 , G06F3/0671 , G06F3/0683 , G06F3/0689 , G06F9/00 , G06F11/22 , G06F12/0284 , G06F12/0623 , G06F12/08 , G06F12/0842 , G06F2212/1008 , G06F2212/1032 , G06F2212/1048 , G06F2212/261 , G06F2212/50 , G06F2212/652 , G06F2212/656 , G06F2212/657
摘要： A method, system, and computer program product to verify management of real storage via multi-threaded thrashers in multiple address spaces are described. The method includes dynamically scaling a number of units of work and a number of address spaces based on a number of available processors and dynamically scaling an amount and page size of storage pages representing virtual storage accessed by each of the number of units of work based on a total available memory. The method also includes obtaining, at each of the units of work, different types of storage frame sizes and attributes, accessing the storage pages corresponding with the respective different types of storage frame sizes and attributes and performing a respective function, and verifying, for each of the units of work performing the respective function, a location of the storage pages and content of the storage pages based on the respective function.
摘要翻译：描述了一种在多个地址空间中通过多线程触发器验证对真实存储的管理的方法，系统和计算机程序产品。该方法包括基于可用处理器的数量来动态地缩放多个工作单元和多个地址空间，并且动态地缩放表示由每个工作单元数量访问的虚拟存储器的存储页面的数量和页面大小基于总可用内存该方法还包括在每个工作单元中获得不同类型的存储帧大小和属性，访问与各种不同类型的存储帧大小和属性相对应的存储页面并执行相应的功能，并且对于每个执行相应功能的工作单元，存储页面的位置和存储页面的内容基于相应的功能。

28. 发明授权

US09195554B2 Information processing apparatus and maintenance method of an information processing apparatus 有权
标题翻译：信息处理装置的信息处理装置及维护方法
公开(公告)号：US09195554B2
公开(公告)日：2015-11-24
申请号：US13771288
申请日：2013-02-20
申请人： FUJITSU LIMITED
发明人： Takeshi Watanabe , Hidejirou Daikokuya , Kazuhiko Ikeuchi , Chikashi Maeda , Norihide Kubota , Atsushi Igashira , Kenji Kobayashi , Ryota Tsukahara
IPC分类号： G06F11/00 , G06F11/22 , G06F11/07
CPC分类号： G06F11/22 , G06F11/0724 , G06F11/0751
摘要： An information processing apparatus includes: processing units to perform information processing, the processing units being capable of continuing the information processing even if a processing unit in the processing units stops its operation; and a control unit to perform a potential failure detection process of restarting the processing units one by one and outputting information requesting replacement or repair of a processing unit that is not restarted up.
摘要翻译：信息处理设备包括：处理单元执行信息处理，处理单元能够继续信息处理，即使处理单元中的处理单元停止其操作; 以及控制单元，用于逐个执行重新启动处理单元的潜在故障检测处理，并输出请求替换或修复未重新启动的处理单元的信息。

29. 发明申请

US20150309907A1 SYSTEM AND METHOD FOR TESTING COMPUTING HARDWARE IN COMPUTER RACK 有权
标题翻译：用于测试计算机机架中计算硬件的系统和方法
公开(公告)号：US20150309907A1
公开(公告)日：2015-10-29
申请号：US14694103
申请日：2015-04-23
申请人： HON HAI PRECISION INDUSTRY CO., LTD.
发明人： CHO-HAO WANG
IPC分类号： G06F11/267 , G06F9/50 , H04L29/08 , G06F9/48
CPC分类号： G06F11/267 , G06F9/4856 , G06F9/5088 , G06F11/0709 , G06F11/22 , G06F11/26 , G06F11/263 , H04L67/1008
摘要： A method for testing computing hardware detects the current time as being within a predetermined time period and transfers virtual machines (VMs) from a plurality of physical machines to other physical machines as targets according to a load balancing strategy. The load balancing strategy sums of a load ratio of one physical machine including the VM and a load ratio of one physical machine as a target for the transfer; if the sum of the two ratios is less than a preset load ratio, the VM-transferring physical machine is put into a standby state when the transfer takes place as long as the current time is still inside the predetermined time period. Physical machines which are in the standby state and have not been tested are awoken, and the awoken physical machines are connected to the server for testing.
摘要翻译：用于测试计算硬件的方法将当前时间检测为在预定时间段内，并根据负载平衡策略将虚拟机（VM）从多个物理机器传送到其他物理机器作为目标。包括VM的一个物理机的负载比的负载平衡策略和作为转移的目标的一个物理机的负载比的总和; 如果两个比率的总和小于预设的负载比率，则只要当前时间仍在预定时间段内，则在转移发生时VM传送物理机器处于待机状态。处于待机状态并未经测试的物理机器被唤醒，并且唤醒的物理机器连接到服务器进行测试。

30. 发明授权

US09164853B2 Multi-core re-initialization failure control system 有权
标题翻译：多核重新初始化故障控制系统
公开(公告)号：US09164853B2
公开(公告)日：2015-10-20
申请号：US13798423
申请日：2013-03-13
申请人： International Business Machines Corporation
发明人： Peter J. Heyrman , Stuart Z. Jacobs , David A. Larson
IPC分类号： G06F11/00 , G06F11/20 , G06F11/22 , G06F11/14 , G06F11/07
CPC分类号： G06F11/202 , G06F11/0706 , G06F11/0793 , G06F11/1402 , G06F11/143 , G06F11/22 , G06F2201/815
摘要： A method of a computer system recovering from a core re-initialization failure is described. The method may include automatically detect a core re-initialization failure during a core re-initialization process by a hypervisor. The hypervisor automatically determines whether the core re-initialization failure is a permanent failure. If the core re-initialization failure is a permanent failure, then automatically determine, by the hypervisor, which cores are re-initialized and which cores are indeterminate. Automatically allocate the re-initialized cores between one or more virtual machines by the hypervisor.
摘要翻译：描述了从核心重新初始化故障中恢复的计算机系统的方法。该方法可以包括在管理程序的核心重新初始化过程期间自动检测核心重新初始化故障。管理程序自动确定核心重新初始化故障是永久性故障。如果核心重新初始化故障是永久性故障，则由管理程序自动确定哪些内核被重新初始化，哪些内核是不确定的。由管理程序自动分配一个或多个虚拟机之间重新初始化的内核。

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