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21. 发明公开

US20240230990A1 INTEGRATED OPTICAL WAVEGUIDE 审中-公开
公开(公告)号：US20240230990A1
公开(公告)日：2024-07-11
申请号：US18557444
申请日：2022-03-24
申请人： IHP GmbH-Innovations for High Performance Microelectronics/Leibniz-Instit. für innovative , Technische Hochschule Wildau
发明人： Patrick STEGLICH , Christian MAI , Andreas MAI , Francesco VILLASMUNTA , Claus VILLRINGER , Sigurd SCHRADER
IPC分类号： G02B6/122 , G02B6/12 , G02B6/136 , G02B6/43
CPC分类号： G02B6/122 , G02B6/136 , G02B6/43 , G02B2006/12121
摘要： An integrated optical waveguide formed in a substrate is disclosed. The integrated optical waveguide includes a hole, a core, and one or more bridges. The hole extends in an axial direction of the substrate. The core is made of the same material as the substrate, arranged in the hole, and extends in the axial direction. The core has a first refractive index and a sidewall which is at least partly surrounded by a surrounding material which has a second refractive index which is lower than the first refractive index and such that a refractive index difference between the first refractive index and the second refractive index allows to guide light within the core. The bridges extend from the sidewall of the core to a sidewall of the hole. The bridges may be made of the same material as the substrate. Furthermore, one or more of the sidewalls of the core, the hole, and the bridges may be tapered sidewalls which include a section which is oblique to the axial direction. Additionally an axial length of one or more of the bridges may be shorter than an axial length of the core.

22. 发明申请

US20230055351A1 Switchable Combiner and/or Splitter Circuit Comprising Wilkinson Elements 有权
公开(公告)号：US20230055351A1
公开(公告)日：2023-02-23
申请号：US17888790
申请日：2022-08-16
申请人： IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut fur Innovative Mikro
发明人： Andrea Malignaggi , Aniello Franzese
IPC分类号： H01P5/12 , H03K17/60
摘要： A switchable combiner and/or splitter circuit comprising at least two Wilkinson elements is suggested. The switchable circuit comprises one first terminal and for each Wilkinson element one pair of second terminals associated with the corresponding Wilkinson element. Each Wilkinson element connects the first terminal with the associated pair of second terminals. Each Wilkinson element includes a switchable component enabling selectively activating the associated pair of second terminals. The proposed solution combines a Single-Pole-Double-Through switch and a Wilkinson element and, thus, reduces the chip area required for integrating the circuit.

23. 发明申请

US20220206750A1 PROGRAMMABLE ANALOG SIGNAL PROCESSING ARRAY FOR TIME-DISCRETE PROCESSING OF ANALOG SIGNALS 有权
公开(公告)号：US20220206750A1
公开(公告)日：2022-06-30
申请号：US17563493
申请日：2021-12-28
申请人： IHP GmbH - Innovations for High Performance Microelectronics / Leibniz-Institut fur Innovative Mikro
发明人： Gerhard KAHMEN , Eckhard GRASS
IPC分类号： G06F7/523 , H03K5/135
摘要： A programmable analog processing array for programmable time-discrete processing of analog input signals in accordance with a desired signal processing function comprises a network of mutually interconnectable and pre-configurable analog processing slices that form unit circuit cells of the network. Each processing slice comprises a set of cell circuit elements including: a switchable clock input port for receiving a clock signal, a delay element for receiving a respective analog slice input signal and for forwarding the received slice input signal with a pre-configurable time delay as a respective delayed slice input signal, an analog multiplier element receiving the delayed slice input signal for providing an analog multiplier output signal corresponding to a product of the delayed slice input signal with a pre-configurable multiplication factor, an analog adder element receiving a pre-configurable selection of at least two adder input signals including the multiplier output signal and for providing an analog adder output signal corresponding to a sum of the adder input signals, and including an analog resample element for receiving the adder output signal and for providing the received adder output with a pre-configurable time delay as an analog slice output signal.

24. 发明申请

US20220076718A1 SELF-CORRECTING MODULAR-REDUNDANCY-MEMORY DEVICE 有权
公开(公告)号：US20220076718A1
公开(公告)日：2022-03-10
申请号：US17466015
申请日：2021-09-03
申请人： IHP GmbH - Innovations for High Performance MIcroelectronics / Leibniz- Institut fur innovative Mikr
发明人： Oliver SCHRAPE , Anselm BREITENREITER , Frank VATER , Milos KRSTIC
IPC分类号： G11C7/10 , G11C7/22 , H03K5/135 , H03K5/15
摘要： The invention is directed to a self-correcting modular-redundancy-memory device, comprising three bistable-memory elements and a majority voter. The bistable-memory elements receive respective binary data signal, clock signal, and a feedback signal. Each of the bistable-memory elements is configured, in response to the clock signal assuming a first value, to provide a binary output signal with an output-signal value correlated to a data-signal value of the data signal, and in response to the clock signal assuming a second clock-signal value, to provide the output signal with the output-signal value indicative of a current feedback-signal value of the feedback signal. The majority voter receives the output signals each of the bistable-memory elements and is configured to provide the feedback signal with the feedback-signal value indicative of that output-signal value taken on by a majority of the currently received output signals.

25. 发明授权

US11061996B2 Intrinsic authentication of program code 有权
公开(公告)号：US11061996B2
公开(公告)日：2021-07-13
申请号：US15546803
申请日：2016-01-28
申请人： IHP GmbH—Innovations for High Performance Microelectronics/Leibniz-Institut Fur Innovative Mikroelektronik
发明人： Oliver Stecklina , Peter Langendorfer
IPC分类号： H04L29/06 , G06F21/12 , H04L9/06
摘要： A cryptoprocessor has a processor core for receiving and executing instructions of a program code based on a program flow chart, a program memory unit which stores the program code with instructions in an individually encrypted format, wherein the respective instructions contain at least one instruction data word and an instruction data key allocated to the respective instruction, a respective instruction is encrypted using a program data key and the instruction data key of a respective preceding instruction, which is to be executed immediately beforehand in accordance with the program flow chart, and wherein the same instruction data key is allocated to the corresponding possible preceding instructions only in the event that a corresponding instruction in the program flow chart has a plurality of possible preceding instructions, the respective instruction data keys otherwise being unique to the instruction. A decryption unit is also described.

26. 发明授权

US10666213B2 Amplification circuit with read/write circuit 有权
公开(公告)号：US10666213B2
公开(公告)日：2020-05-26
申请号：US16106108
申请日：2018-08-21
申请人： IHP GmbH—Innovations for High Performance Microelectronics/Leibniz-Institut fur Innovative Mikroelektronik
发明人： Ahmed Awny , Alexey Balashov , Dietmar Kissinger
IPC分类号： H03G3/20 , H03G3/30 , H03F3/45 , H03G3/02 , H03G3/04
摘要： The invention relates to an amplification circuit (100), comprising: a VGA (2), an AGC loop (10) for automatically controlling the gain of the VGA (2), a switching circuit (14) for switching between an AGC mode, in which the gain of the VGA (2) is automatically controlled by an output signal of the AGC loop (10) and a manual gain control, MGC, mode, in which the gain of the VGA (2) can be manually controlled by an input signal, and a read/write circuit (30) with a contact (31) for connection to a peripheral system, wherein the read/write circuit (30) is configured, in the MGC mode, to provide the input signal from the contact (31) via a write-mode path (32) to the VGA (2), and, in the AGC mode, to provide the output signal of the AGC loop (10) via a read-mode path (33) on the contact (31).

27. 发明授权

US09824984B2 Individualised voltage supply of integrated circuits components as protective means against side channel attacks 有权
公开(公告)号：US09824984B2
公开(公告)日：2017-11-21
申请号：US14438341
申请日：2013-10-25
申请人： IHP GmbH—Innovations for High Performance Microelectronics/Leibniz-Institut Fur Innovative Mikroelektronik
发明人： Zoya Dyka , Peter Langendorfer
IPC分类号： H01L23/48 , H01L23/00 , H01L23/532 , H01L23/528 , H01L27/118 , H01L27/02 , H01L23/522
CPC分类号： H01L23/573 , H01L23/5226 , H01L23/528 , H01L23/5286 , H01L23/53204 , H01L27/0292 , H01L27/11807 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device, in particular an integrated circuit with protection against side channel attacks, in particular imaging- and probing-based attacks, EMA and reverse engineering, in which a metallic conductive layer of a first (104) and/or a second potential supply line (106) are each connected directly and individually to all the circuit components via respective individual conductor path structures (V1, V2).

28. 发明授权

US09590045B2 Graphene base transistor and method for making the same 有权
标题翻译：石墨烯基晶体管及其制造方法
公开(公告)号：US09590045B2
公开(公告)日：2017-03-07
申请号：US14894090
申请日：2014-05-23
申请人： IHP GMBH—INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ—INSTITUT FÜR INNOVATIVE MIKROELEKTRONIK
发明人： Andre Wolff , Wolfgang Mehr , Grzegorz Lupina , Jaroslaw Dabrowski , Gunther Lippert , Mindaugas Lukosius , Chafik Meliani , Christian Wenger
IPC分类号： H01L29/06 , H01L29/16 , H01L29/66 , H01L29/737 , H01L21/308 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/45 , H01L29/73
CPC分类号： H01L29/1606 , H01L21/308 , H01L29/0649 , H01L29/0692 , H01L29/0804 , H01L29/0821 , H01L29/1004 , H01L29/41708 , H01L29/45 , H01L29/66037 , H01L29/73 , H01L29/737
摘要： A graphene base transistor comprises on a semiconductor substrate surface an emitter pillar and an emitter-contact pillar, which extend from a pillar foundation in a vertical direction. A dielectric filling layer laterally embeds the emitter pillar and the emitter-contact pillar above the pillar foundation. The dielectric filling layer has an upper surface that is flush with a top surface of the emitter pillar and with the at least one base-contact arm of a base-contact structure. A graphene base forms a contiguous layer between a top surface of the emitter pillar and a top surface of the base-contact arm. A collector stack and the base have the same lateral extension parallel to the substrate surface and perpendicular to those edges of the top surface of the emitter pillar and the base-contact arm that face each other.
摘要翻译：石墨烯基晶体管包括在半导体衬底表面上的从立柱基部在垂直方向上延伸的发射极柱和发射极 - 接触柱。电介质填充层横向地嵌入支柱基座上方的发射极柱和发射极 - 接触柱。电介质填充层具有与发射极柱的顶表面齐平的上表面和与基底接触结构的至少一个基底接触臂。石墨烯底座在发射极柱的顶表面和基底接触臂的顶表面之间形成连续的层。集电体堆叠和基座具有与基板表面平行的垂直于发射极柱和基座接触臂的顶表面的那些边缘的相同的横向延伸部。

29. 发明授权

US09147998B2 Light-emitting semiconductor structure and optoelectronic component therefrom 有权
标题翻译：发光半导体结构及其光电子元件
公开(公告)号：US09147998B2
公开(公告)日：2015-09-29
申请号：US13688330
申请日：2012-11-29
申请人： IHP GmbH—Innovations for High Performance Microelectronics
发明人： Martin Kittler , Tzanimir Arguirov , Manfred Reiche
IPC分类号： H01S5/30 , H01L33/00 , H01L33/02 , H01L33/34 , H01L33/58
CPC分类号： H01S5/305 , H01L33/0037 , H01L33/0079 , H01L33/025 , H01L33/34 , H01L33/58
摘要： A light emitting semiconductor device according the invention includes an SOI substrate, a collector and an injector. The SOI substrate includes a carrier layer, a buried oxide layer on the carrier layer, and a doped silicon layer structure with a conductivity type. The doped silicon layer structure with the conductivity type includes at least two silicon- or silicon germanium layers arranged adjacent to one another, wherein a dislocation network is configured in their interface portions at which dislocation network a radiative charge carrier combination with a light energy is provided, which light energy is smaller than a band gap energy of the silicon- or silicon germanium layers. The collector is formed as a pn-junction in a portion between the dislocation network and a surface of the silicon layer structure that is oriented away from the carrier layer, and wherein the injector is configured as a metal insulator semiconductor diode.
摘要翻译：根据本发明的发光半导体器件包括SOI衬底，集电极和注射器。 SOI衬底包括载体层，载体层上的掩埋氧化物层和具有导电类型的掺杂硅层结构。具有导电类型的掺杂硅层结构包括彼此相邻布置的至少两个硅或锗锗层，其中位错网络在其界面部分中配置，在该界面部分中提供了具有光能的辐射电荷载流子组合，其光能小于硅或锗锗层的带隙能量。集电体在位错网络和硅层结构的远离载体层的表面之间的部分中形成为pn结，并且其中注入器被配置为金属绝缘体半导体二极管。

30. 发明授权

US08932405B2 Apparatus for low-temperature epitaxy on a plurality semiconductor substrates 有权
标题翻译：用于在多个半导体衬底上进行低温外延的装置
公开(公告)号：US08932405B2
公开(公告)日：2015-01-13
申请号：US11579276
申请日：2005-05-10
申请人： Thomas Grabolla , George Ritter , Bernd Tillack
发明人： Thomas Grabolla , George Ritter , Bernd Tillack
IPC分类号： C23C16/00 , C23C16/54 , C30B25/08
CPC分类号： C23C16/54 , C30B25/08
摘要： A reactor arrangement for layer deposition on a plurality of substrates (hereafter substrates) comprising a first reactor chamber for simultaneous cleaning the substrates, at least one second reactor chamber for depositing at least one layer on each of the substrates, a first heating device for setting the substrate temperature of the substrates in the first reactor chamber, a second heating device for setting the substrate temperature of the substrates in the second reactor chamber, a device for producing a gas atmosphere of predetermined composition and predetermined pressure, a transport device for transporting the substrates simultaneously from the first to the second reactor chamber, and a control device for controlling the heating devices and device for producing the gas atmosphere in such a way that the substrates are moved or stored in an interruption-free manner in a reducing gas atmosphere as long as the substrate temperature is above critical temperature Tc.
摘要翻译：一种反应器装置，用于在多个基板（以下称为基板）上层压沉积，该基板包括用于同时清洁基板的第一反应器室，用于在每个基板上沉积至少一层的至少一个第二反应室，用于设定的第一加热装置第一反应器室中的基板的基板温度，用于设定第二反应器室中的基板的基板温度的第二加热装置，用于制造预定组成和预定压力的气体气氛的装置，用于输送基板同时从第一反应室到第二反应室，以及控制装置，用于控制加热装置和用于产生气体气氛的装置，使得基板在还原气体气氛中以无中断的方式移动或储存，如只要衬底温度高于临界温度Tc。

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