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21. 发明授权

US08587065B2 Local bottom gates for graphene and carbon nanotube devices 有权
标题翻译：石墨烯和碳纳米管器件的局部底栅
公开(公告)号：US08587065B2
公开(公告)日：2013-11-19
申请号：US13364273
申请日：2012-02-01
申请人： Zhihong Chen , Aaron D. Franklin , James B. Hannon , George S. Tulevski
发明人： Zhihong Chen , Aaron D. Franklin , James B. Hannon , George S. Tulevski
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/7781 , H01L29/78684 , H01L51/0048 , H01L51/0516 , H01L51/0525 , H01L51/0545 , H01L51/055
摘要： Transistor devices having nanoscale material-based channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device includes a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel. A method of fabricating a transistor device is also provided.
摘要翻译：提供了具有基于纳米材料的通道的晶体管器件及其制造技术。一方面，晶体管器件包括衬底; 衬底上的绝缘体; 嵌入绝缘体中的栅极与栅极的顶表面基本上与绝缘体的表面共面; 栅极和绝缘体上的介电层; 形成在所述栅极上的所述电介质层上的碳纳米结构材料的沟道，其中所述栅极和所述绝缘体上的所述电介质层提供其上形成有所述沟道的平坦表面; 并通过通道连接源极和漏极触点。还提供了一种制造晶体管器件的方法。

22. 发明申请

US20120175594A1 Graphene Devices with Local Dual Gates 有权
标题翻译：石墨烯器件与本地双门
公开(公告)号：US20120175594A1
公开(公告)日：2012-07-12
申请号：US12986342
申请日：2011-01-07
申请人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han
发明人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han
IPC分类号： H01L29/15 , H01L21/336
CPC分类号： H01L29/66045 , H01L21/02178 , H01L21/02181 , H01L21/02527 , H01L21/044 , H01L29/1606 , H01L29/42376 , H01L29/42384 , H01L29/4908 , H01L29/4916 , H01L29/517 , H01L29/66015 , H01L29/66742 , H01L29/78645 , H01L29/78648 , H01L29/78684
摘要： An electronic device comprises an insulator, a local first gate embedded in the insulator with a top surface of the first gate being substantially coplanar with a surface of the insulator, a first dielectric layer formed over the first gate and insulator, and a channel. The channel comprises a bilayer graphene layer formed on the first dielectric layer. The first dielectric layer provides a substantially flat surface on which the channel is formed. A second dielectric layer formed over the bilayer graphene layer and a local second gate formed over the second dielectric layer. Each of the local first and second gates is capacitively coupled to the channel of the bilayer graphene layer. The local first and second gates form a first pair of gates to locally control a first portion of the bilayer graphene layer.
摘要翻译：电子设备包括绝缘体，嵌入在绝缘体中的局部第一栅极，第一栅极的顶表面与绝缘体的表面基本共面;形成在第一栅极和绝缘体上的第一介电层，以及沟道。通道包括形成在第一介电层上的双层石墨烯层。第一电介质层提供基本上平坦的表面，在其上形成沟道。形成在双层石墨烯层上的第二介电层和在第二介电层上形成的局部第二栅极。局部第一和第二栅极中的每一个电容耦合到双层石墨烯层的沟道。局部第一和第二栅极形成第一对栅极以局部控制双层石墨烯层的第一部分。

23. 发明申请

US20120146001A1 ULTRATHIN SPACER FORMATION FOR CARBON-BASED FET 有权
标题翻译：基于碳的FET的超声波分离器形成
公开(公告)号：US20120146001A1
公开(公告)日：2012-06-14
申请号：US13401967
申请日：2012-02-22
申请人： Zhihong Chen , Dechao Guo , Shu-Jen Han , Kai Zhao
发明人： Zhihong Chen , Dechao Guo , Shu-Jen Han , Kai Zhao
IPC分类号： H01L29/78 , B82Y99/00
CPC分类号： H01L29/1606 , H01L29/4908 , H01L29/66742 , H01L29/7781 , H01L29/78684
摘要： A carbon-based field effect transistor (FET) includes a substrate; a carbon layer located on the substrate, the carbon layer comprising a channel region, and source and drain regions located on either side of the channel region; a gate electrode located on the channel region in the carbon layer, the gate electrode comprising a first dielectric layer, a gate metal layer located on the first dielectric layer, and a nitride layer located on the gate metal layer; and a spacer comprising a second dielectric layer located adjacent to the gate electrode, wherein the spacer is not located on the carbon layer.
摘要翻译：碳基场效应晶体管（FET）包括基板; 位于所述基板上的碳层，所述碳层包括沟道区，以及位于所述沟道区两侧的源区和漏区; 位于所述碳层中的沟道区上的栅电极，所述栅电极包括第一电介质层，位于所述第一电介质层上的栅极金属层和位于所述栅极金属层上的氮化物层; 以及间隔件，其包括邻近所述栅电极的第二电介质层，其中所述间隔物不位于所述碳层上。

24. 发明授权

US08193032B2 Ultrathin spacer formation for carbon-based FET 有权
标题翻译：碳基FET的超薄间隔物形成
公开(公告)号：US08193032B2
公开(公告)日：2012-06-05
申请号：US12826221
申请日：2010-06-29
申请人： Zhihong Chen , Dechao Guo , Shu-jen Han , Kai Zhao
发明人： Zhihong Chen , Dechao Guo , Shu-jen Han , Kai Zhao
IPC分类号： H01L21/00
CPC分类号： H01L29/1606 , H01L29/4908 , H01L29/66742 , H01L29/7781 , H01L29/78684
摘要： A method for formation of a carbon-based field effect transistor (FET) includes depositing a first dielectric layer on a carbon layer located on a substrate; forming a gate electrode on the first dielectric layer; etching an exposed portion of the first dielectric layer to expose a portion of the carbon layer; depositing a second dielectric layer over the gate electrode to form a spacer, wherein the second dielectric layer is deposited by atomic layer deposition (ALD), and wherein the second dielectric layer does not form on the exposed portion of the carbon layer; forming source and drain contacts on the carbon layer and forming a gate contact on the gate electrode to form the carbon-based FET.
摘要翻译：一种用于形成碳基场效应晶体管（FET）的方法包括：在位于衬底上的碳层上沉积第一介电层; 在所述第一电介质层上形成栅电极; 蚀刻第一介电层的暴露部分以暴露碳层的一部分; 在所述栅电极上沉积第二电介质层以形成间隔物，其中所述第二电介质层通过原子层沉积（ALD）沉积，并且其中所述第二电介质层不在所述碳层的暴露部分上形成; 在碳层上形成源极和漏极接触，并在栅电极上形成栅极接触以形成碳基FET。

25. 发明授权

US08124463B2 Local bottom gates for graphene and carbon nanotube devices 有权
标题翻译：石墨烯和碳纳米管器件的局部底栅
公开(公告)号：US08124463B2
公开(公告)日：2012-02-28
申请号：US12563553
申请日：2009-09-21
申请人： Zhihong Chen , Aaron D. Franklin , James B. Hannon , George S. Tulevski
发明人： Zhihong Chen , Aaron D. Franklin , James B. Hannon , George S. Tulevski
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/7781 , H01L29/78684 , H01L51/0048 , H01L51/0516 , H01L51/0525 , H01L51/0545 , H01L51/055
摘要： Transistor devices having nanoscale material-based channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device includes a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel. A method of fabricating a transistor device is also provided.
摘要翻译：提供了具有基于纳米材料的通道的晶体管器件及其制造技术。一方面，晶体管器件包括衬底; 衬底上的绝缘体; 嵌入绝缘体中的栅极与栅极的顶表面基本上与绝缘体的表面共面; 栅极和绝缘体上的介电层; 形成在所述栅极上的所述电介质层上的碳纳米结构材料的沟道，其中所述栅极和所述绝缘体上的所述电介质层提供其上形成有所述沟道的平坦表面; 并通过通道连接源极和漏极触点。还提供了一种制造晶体管器件的方法。

26. 发明申请

US20120032149A1 Vertical Stacking of Carbon Nanotube Arrays for Current Enhancement and Control 有权
标题翻译：碳纳米管阵列的垂直堆叠，用于电流增强和控制
公开(公告)号：US20120032149A1
公开(公告)日：2012-02-09
申请号：US12850095
申请日：2010-08-04
申请人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han
发明人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L51/0048 , B82Y10/00 , H01L51/0558 , Y10S977/742 , Y10S977/938
摘要： Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.
摘要翻译：提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。一方面，提供一种晶体管器件。晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。还提供了一种制造晶体管器件的方法。

27. 发明申请

US20110068323A1 Local Bottom Gates for Graphene and Carbon Nanotube Devices 有权
标题翻译：石墨烯和碳纳米管装置的局部底盖
公开(公告)号：US20110068323A1
公开(公告)日：2011-03-24
申请号：US12563553
申请日：2009-09-21
申请人： Zhihong Chen , Aaron D. Franklin , James B. Hannon , George S. Tulevski
发明人： Zhihong Chen , Aaron D. Franklin , James B. Hannon , George S. Tulevski
IPC分类号： H01L29/66 , H01L21/336
CPC分类号： H01L29/1606 , B82Y10/00 , H01L29/7781 , H01L29/78684 , H01L51/0048 , H01L51/0516 , H01L51/0525 , H01L51/0545 , H01L51/055
摘要： Transistor devices having nanoscale material-based channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device includes a substrate; an insulator on the substrate; a gate embedded in the insulator with a top surface of the gate being substantially coplanar with a surface of the insulator; a dielectric layer over the gate and insulator; a channel comprising a carbon nanostructure material formed on the dielectric layer over the gate, wherein the dielectric layer over the gate and the insulator provides a flat surface on which the channel is formed; and source and drain contacts connected by the channel. A method of fabricating a transistor device is also provided.
摘要翻译：提供了具有基于纳米材料的通道的晶体管器件及其制造技术。一方面，晶体管器件包括衬底; 衬底上的绝缘体; 嵌入绝缘体中的栅极与栅极的顶表面基本上与绝缘体的表面共面; 栅极和绝缘体上的介电层; 形成在所述栅极上的所述电介质层上的碳纳米结构材料的沟道，其中所述栅极和所述绝缘体上的所述电介质层提供其上形成有所述沟道的平坦表面; 并通过通道连接源极和漏极触点。还提供了一种制造晶体管器件的方法。

28. 发明授权

US5929642A Method of locating a fault in a predetermined monitoring region of a multiphase electric power transmission system 失效
标题翻译：在多相电力传输系统的预定监视区域中定位故障的方法
公开(公告)号：US5929642A
公开(公告)日：1999-07-27
申请号：US836621
申请日：1997-11-19
申请人： Luc Philippot , Zhihong Chen
发明人： Luc Philippot , Zhihong Chen
IPC分类号： G01R31/08 , G01R31/02
CPC分类号： G01R31/085 , G01R31/088
摘要： A method for locating a fault in an electric power transmission line to form measured precursor fault vector values of two aerial modes from sample values from currents and voltages stored immediately before and during an occurrence of the fault, using the Clarke transformation. For synchronization, the phase angle is determined from these measured vector values, so that fault vector voltage values of both aerial modes can be generated without distortion by asynchronously forming the sample values. The fault vector voltage values of one aerial mode are subtracted from those of the other aerial mode, and the resulting differences are squared. The location of the fault is determined by estimating the minimum value of the sum of the squared differences.
摘要翻译： PCT No.PCT / DE95 / 01594 Sec。 371日期：1997年11月19日 102（e）日期1997年11月19日PCT 1995年11月6日PCT PCT。公开号WO96 / 14585 日期1996年5月17日一种用于在电力输电线路中定位故障的方法，使用克拉克变换形成从故障发生之前和期间存储的电流和电压的样本值得到的两个空中模式的前兆故障向量值。为了同步，从这些测量的矢量值确定相位角，使得可以通过异步地形成采样值而不失真地产生两个空中模式的故障矢量电压值。一个空中模式的故障矢量电压值从另一个空中模式的故障矢量电压值中减去，得到的差值平方。通过估计平方差的和的最小值来确定故障的位置。

29. 发明授权

US09250211B2 Magnetic separation of lipoproteins using dextran sulfate 有权
标题翻译：使用硫酸葡聚糖磁性分离脂蛋白
公开(公告)号：US09250211B2
公开(公告)日：2016-02-02
申请号：US13340547
申请日：2011-12-29
申请人： Michael P. Caulfield , Jackie Liu , Dawn Shalhout , Zhihong Chen
发明人： Michael P. Caulfield , Jackie Liu , Dawn Shalhout , Zhihong Chen
IPC分类号： G01N27/62 , C07K1/22 , C07K1/30 , C07K1/36
CPC分类号： C07K1/30 , C07K1/22 , C07K1/36 , G01N27/447 , G01N27/622
摘要： The invention provides apparatus and methods of preparation of lipoproteins from a biological sample, including HDL, LDL, Lp(a), IDL, and VLDL, for diagnostic purposes utilizing differential charged-particle mobility analysis methods. Further provided are methods for analyzing the size distribution of lipoproteins by differential charged-particle mobility, which lipoproteins are prepared by methods of the invention. Further provided are methods for assessing lipid-related health risk, cardiovascular condition, risk of cardiovascular disease, and responsiveness to a therapeutic intervention, which methods utilize lipoprotein size distributions determined by methods of the invention.
摘要翻译：本发明提供了用于利用差示带电粒子迁移率分析方法的诊断目的从生物样品（包括HDL，LDL，Lp（a），IDL和VLDL）制备脂蛋白的装置和方法。还提供了通过差异带电粒子迁移率分析脂蛋白的尺寸分布的方法，该脂蛋白通过本发明的方法制备。还提供了评估脂质相关健康风险，心血管疾病，心血管疾病风险以及对治疗性干预的反应性的方法，该方法利用通过本发明方法测定的脂蛋白大小分布。

30. 发明申请

US20130015428A1 Vertical Stacking of Carbon Nanotube Arrays for Current Enhancement and Control 有权
标题翻译：碳纳米管阵列的垂直堆叠，用于电流增强和控制
公开(公告)号：US20130015428A1
公开(公告)日：2013-01-17
申请号：US13610089
申请日：2012-09-11
申请人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han
发明人： Zhihong Chen , Aaron Daniel Franklin , Shu-Jen Han
IPC分类号： H01L27/088 , H01L21/8234
CPC分类号： H01L51/0048 , B82Y10/00 , H01L51/0558 , Y10S977/742 , Y10S977/938
摘要： Transistor devices having vertically stacked carbon nanotube channels and techniques for the fabrication thereof are provided. In one aspect, a transistor device is provided. The transistor device includes a substrate; a bottom gate embedded in the substrate with a top surface of the bottom gate being substantially coplanar with a surface of the substrate; a stack of device layers on the substrate over the bottom gate, wherein each of the device layers in the stack includes a first dielectric, a carbon nanotube channel on the first dielectric, a second dielectric on the carbon nanotube channel and a top gate on the second dielectric; and source and drain contacts that interconnect the carbon nanotube channels in parallel. A method of fabricating a transistor device is also provided.
摘要翻译：提供具有垂直堆叠的碳纳米管通道的晶体管器件及其制造技术。一方面，提供一种晶体管器件。晶体管器件包括衬底; 嵌入基板中的底栅与底栅的顶表面基本上与基板的表面共面; 在底栅上的衬底上的一叠器件层，其中堆叠中的每个器件层包括第一电介质，第一电介质上的碳纳米管通道，碳纳米管通道上的第二电介质和第二电介质; 以及并联连接碳纳米管通道的源极和漏极触点。还提供了一种制造晶体管器件的方法。

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