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21. 发明申请

US20110131044A1 TARGET VOICE EXTRACTION METHOD, APPARATUS AND PROGRAM PRODUCT 失效
标题翻译：目标语音提取方法，装置和程序产品
公开(公告)号：US20110131044A1
公开(公告)日：2011-06-02
申请号：US12955882
申请日：2010-11-29
申请人： Takashi Fukuda , Osamu Ichikawa , Masafumi Nishimura
发明人： Takashi Fukuda , Osamu Ichikawa , Masafumi Nishimura
IPC分类号： G10L17/00
CPC分类号： G10L25/78 , G10L15/20 , G10L21/028 , G10L2021/02166
摘要： An apparatus, program product and method is provided for separating a target voice from a plurality of other voices having different directions of arrival. The method comprises the steps of disposing a first and a second voice input device at a predetermined distance from one another and upon receipt of voice signals at said devices calculating discrete Fourier transforms for the signals and calculating a CSP (cross-power spectrum phase) coefficient by superpositioning multiple frequency-bin components based on correlation of the two spectra signals received and then calculating a weighted CSP coefficient from said two discrete Fourier-transformed speech signals. A target voice is separated when received by said devices from other voice signals in a spectrum by using the calculated weighted CSP coefficient.
摘要翻译：提供了一种用于将目标语音与具有不同到达方向的多个其他语音分离的装置，程序产品和方法。该方法包括以下步骤：将第一和第二语音输入设备彼此隔开预定的距离，并且在所述设备接收到语音信号时，为信号计算离散付里叶变换并计算CSP（交叉功率谱相位）系数通过基于所接收的两个频谱信号的相关性叠加多个频率分量，然后从所述两个离散傅里叶变换的语音信号计算加权的CSP系数。通过使用计算的加权CSP系数，通过所述设备从频谱中的其他语音信号接收目标语音。

22. 发明授权

US07599836B2 Voice recording system, recording device, voice analysis device, voice recording method and program 有权
标题翻译：录音系统，录音设备，语音分析设备，录音方式和程序
公开(公告)号：US07599836B2
公开(公告)日：2009-10-06
申请号：US11136831
申请日：2005-05-25
申请人： Osamu Ichikawa , Masafumi Nishimura , Tetsuya Takiguchi
发明人： Osamu Ichikawa , Masafumi Nishimura , Tetsuya Takiguchi
IPC分类号： G10L17/00
CPC分类号： G10L21/028
摘要： To provide a method of specifying each of speakers of individual voices, based on recorded voices made by a plurality of speakers, with a simple system configuration, and to provide a system using the method. The system includes: microphones individually provided for each of the speakers; a voice processing unit which gives a unique characteristic to each pair of two-channel voice signals recorded with each of the microphones 10, by executing different kinds of voice processing on the respective pairs of voice signals, and which mixes the voice signals for each channel; and an analysis unit which performs an analysis according to the unique characteristics, given to the voice signals concerning the respective microphones through the processing by the voice processing unit, and which specifies the speaker for each speech segment of the voice signals.
摘要翻译：为了提供一种基于由多个扬声器产生的记录的声音以简单的系统配置来指定各个语音的每个扬声器的方法，并且提供使用该方法的系统。该系统包括：为每个扬声器单独提供的麦克风; 语音处理单元，通过对各个语音信号对执行不同种类的语音处理，并且将每个声道的语音信号进行混合，为记录在每个麦克风10中的每对双声道语音信号提供独特的特性 ; 以及分析单元，其根据通过语音处理单元的处理给予关于各个麦克风的语音信号的独特特性进行分析，并且指定语音信号的每个语音段的说话者。

23. 发明申请

US20080270131A1 METHOD, PREPROCESSOR, SPEECH RECOGNITION SYSTEM, AND PROGRAM PRODUCT FOR EXTRACTING TARGET SPEECH BY REMOVING NOISE 有权
标题翻译：方法，预处理程序，语音识别系统和通过删除噪声提取目标语音的程序产品
公开(公告)号：US20080270131A1
公开(公告)日：2008-10-30
申请号：US12105621
申请日：2008-04-18
申请人： Takashi Fukuda , Osamu Ichikawa , Masafumi Nishimura
发明人： Takashi Fukuda , Osamu Ichikawa , Masafumi Nishimura
IPC分类号： G10L15/00 , G10L19/14
CPC分类号： G10L15/20 , G10L15/02 , G10L21/02 , G10L21/0272 , G10L2021/02161
摘要： The present invention relates to a method, preprocessor, speech recognition system, and program product for extracting a target speech by removing noise. In an embodiment of the invention target speech is extracted from two input speeches, which are obtained through at least two speech input devices installed in different places in a space, applies a spectrum subtraction process by using a noise power spectrum (Uω) estimated by one or both of the two speech input devices (Xω(T)) and an arbitrary subtraction constant (α) to obtain a resultant subtracted power spectrum (Yω(T)). The invention further applies a gain control based on the two speech input devices to the resultant subtracted power spectrum to obtain a gain-controlled power spectrum (Dω(T)). The invention further applies a flooring process to said resultant gain-controlled power spectrum on the basis of arbitrary Flooring factor (β) to obtain a power spectrum for speech recognition (Zω(T)).
摘要翻译：本发明涉及通过去除噪声来提取目标语音的方法，预处理器，语音识别系统和程序产品。在本发明的一个实施例中，从通过安装在空间中的不同位置的至少两个语音输入设备获得的两个输入语音提取目标语音，通过使用由一个估计的噪声功率谱（Uomega）来应用频谱减法处理或两个语音输入装置（Xomega（T））和任意减法常数（α）两者以获得合成的减去的功率谱（Yomega（T））。本发明还将基于两个语音输入装置的增益控制应用于合成的减去的功率谱以获得增益控制的功率谱（Domega（T））。本发明还基于任意地板因子（β）对所得的增益控制功率谱进行地板处理，以获得用于语音识别的功率谱（Zomega（T））。

24. 发明授权

US07348595B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 失效
标题翻译：半导体配线基板，半导体装置，半导体装置的测试方法以及半导体装置的安装方法
公开(公告)号：US07348595B2
公开(公告)日：2008-03-25
申请号：US10828492
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G11C5/02
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.
摘要翻译：通过将多个芯片智能特性（IP）安装在公共半导体布线基板上构成的半导体器件，测试器件的方法和安装芯片IP的方法。提供了可以安装芯片IP的硅布线基板。通过连接触发器在硅布线基板上形成用于边界扫描测试的电路。触发器连接到布线并被布置成测试布线中的连接。整个IP On Super Sub（IPOS）设备或每个芯片IP可以被布置成便于在芯片IP的内部电路上进行扫描测试，内置自检（BIST）等。

25. 发明授权

US07295028B2 Semiconductor integrated circuit and memory test method 有权
标题翻译：半导体集成电路和存储器测试方法
公开(公告)号：US07295028B2
公开(公告)日：2007-11-13
申请号：US11166345
申请日：2005-06-27
申请人： Osamu Ichikawa
发明人： Osamu Ichikawa
IPC分类号： G01R31/02
CPC分类号： G11C29/36 , G11C29/14 , G11C2029/3602
摘要： The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data. The frequency of the second clock is lower than, for example, one quarter or one half, the frequency of the first clock.
摘要翻译：本发明提供一种半导体集成电路，即使在集成电路的内置自检电路的运算速度受到限制的情况下，能够以存储器的实际运行速度测试高速存储器。为了测试在第一时钟上操作的存储器，集成电路设置有用于产生测试数据的第二测试数据的第二测试模式生成部分，以及在第三时钟上工作的第二测试模式生成部分，第二个时钟的反相时钟，用于生成测试数据。此外，集成电路设置有测试数据选择部分，用于根据第二时钟的信号值选择性地输出从第一测试模式生成部分输出的测试数据或从第二测试模式产生部分输出的测试数据，从而将测试数据作为测试数据输入存储器。第二个时钟的频率比第一个时钟的频率低四分之一或一半。

26. 发明申请

US20060099471A1 Fuel cell system 失效
标题翻译：燃料电池系统
公开(公告)号：US20060099471A1
公开(公告)日：2006-05-11
申请号：US11262010
申请日：2005-10-28
申请人： Osamu Ichikawa , Kuri Kasuya
发明人： Osamu Ichikawa , Kuri Kasuya
IPC分类号： H01M8/04
CPC分类号： H01M8/04029 , H01M8/04097 , H01M8/04164
摘要： A fuel cell system includes a fuel cell, a fluid passage for warming, a gas-liquid separator, a supply passage and a recirculating module. The fuel cell generates power with supply of a reaction gas. The gas-liquid separator separates moisture contained in an anode exhaust gas which is discharged from the fuel cell. The supply passage returns the anode exhaust gas, from which the moisture has been separated by the gas-liquid separator, to an inlet side of the reaction gas. The recirculating module mixes the anode exhaust gas, which is returned via the supply passage, with the reaction gas. The gas-liquid separator lies adjacent to the recirculating module, and the fluid passage for warming is disposed between the gas-liquid separator and the recirculating module.
摘要翻译：燃料电池系统包括燃料电池，用于加温的流体通道，气液分离器，供应通道和再循环模块。燃料电池通过反应气体的供给而发电。气液分离器分离从燃料电池排出的阳极废气中含有的水分。供给通道将由气液分离器分离的水分的阳极废气返回到反应气体的入口侧。再循环模块将通过供应通道返回的阳极废气与反应气体混合。气液分离器位于循环模块附近，用于加温的流体通道设置在气 - 液分离器和循环模块之间。

27. 发明授权

US07032196B2 Semiconductor wiring substrate, semiconductor device, method for testing semiconductor device, and method for mounting semiconductor device 失效
公开(公告)号：US07032196B2
公开(公告)日：2006-04-18
申请号：US10828230
申请日：2004-04-21
申请人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
发明人： Sadami Takeoka , Mitsuyasu Ohta , Osamu Ichikawa , Masayoshi Yoshimura
IPC分类号： G06F17/50 , H01L23/58 , G01R31/28
CPC分类号： G01R31/28 , G01R31/318505 , G01R31/318538 , G01R31/318558 , G06F17/50 , G11C5/02 , G11C5/025 , G11C29/48 , G11C2029/3202 , H01L23/12
摘要： A semiconductor device constructed by mounting a plurality of chip intellectual properties (IPs) on a common semiconductor wiring substrate, a method for testing the device and a method for mounting the chip IPs. A silicon wiring substrate on which chip IPs can be mounted is provided. A circuit for a boundary scan test is formed on the silicon wiring substrate by connecting flip flops. The flip flops are connected to wiring and are arranged to test connections in the wiring. The entire IP On Super-Sub (IPOS) device or each chip IP may be arranged to facilitate a scan test, a built-in self-test (BIST), etc., on the internal circuit of the chip IP.

28. 发明申请

US20060005095A1 Semiconductor integrated circuit and memory test method 有权
标题翻译：半导体集成电路和存储器测试方法
公开(公告)号：US20060005095A1
公开(公告)日：2006-01-05
申请号：US11166345
申请日：2005-06-27
申请人： Osamu Ichikawa
发明人： Osamu Ichikawa
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G11C29/36 , G11C29/14 , G11C2029/3602
摘要： The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the built-in self-test circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data. The frequency of the second clock is lower than, for example, one quarter or one half, the frequency of the first clock.
摘要翻译：本发明提供一种半导体集成电路，即使在集成电路的内置自检电路的运算速度受到限制的情况下，能够以存储器的实际运行速度测试高速存储器。为了测试在第一时钟上操作的存储器，集成电路设置有用于产生测试数据的第二测试数据的第二测试模式生成部分，以及在第三时钟上工作的第二测试模式生成部分，第二个时钟的反相时钟，用于生成测试数据。此外，集成电路设置有测试数据选择部分，用于根据第二时钟的信号值选择性地输出从第一测试模式生成部分输出的测试数据或从第二测试模式产生部分输出的测试数据，从而将测试数据作为测试数据输入存储器。第二个时钟的频率比第一个时钟的频率低四分之一或一半。

29. 发明申请

US20050216810A1 Semiconductor integrated circuit and memory test method 失效
公开(公告)号：US20050216810A1
公开(公告)日：2005-09-29
申请号：US11142323
申请日：2005-06-02
申请人： Osamu Ichikawa
发明人： Osamu Ichikawa
IPC分类号： G11C29/36 , G01R31/28
CPC分类号： G11C29/12015 , G11C29/36 , G11C2029/3602
摘要： The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the BIST circuit of the integrated circuit is restricted. In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data. The frequency of the second clock is half the frequency of the first clock.

30. 发明授权

US06917215B2 Semiconductor integrated circuit and memory test method 失效
标题翻译：半导体集成电路和存储器测试方法
公开(公告)号：US06917215B2
公开(公告)日：2005-07-12
申请号：US10647506
申请日：2003-08-26
申请人： Osamu Ichikawa
发明人： Osamu Ichikawa
IPC分类号： G11C29/36 , G01R31/26 , G11C29/00
CPC分类号： G11C29/12015 , G11C29/36 , G11C2029/3602
摘要： The present invention provides a semiconductor integrated circuit capable of testing a high-speed memory at the actual operation speed of the memory even when the operation speed of the BIST circuit of the integrated circuit is restricted.In order to test a memory operating on a first clock, the integrated circuit is provided with a first test pattern generation section, operating on a second clock, for generating test data, and a second test pattern generation section, operating on a third clock, the inverted clock of the second clock, for generating test data. Furthermore, the integrated circuit is provided with a test data selection section for selectively outputting either the test data output from the first test pattern generation section or the test data output from the second test pattern generation section depending on the signal value of the second clock, thereby inputting the test data to the memory as test data. The frequency of the second clock is half the frequency of the first clock.
摘要翻译：本发明提供一种半导体集成电路，即使在集成电路的BIST电路的运算速度受到限制的情况下，也能够以存储器的实际运行速度对高速存储器进行测试。为了测试在第一时钟上操作的存储器，集成电路设置有用于产生测试数据的第二测试数据的第二测试模式生成部分，以及在第三时钟上工作的第二测试模式生成部分，第二个时钟的反相时钟，用于生成测试数据。此外，集成电路设置有测试数据选择部分，用于根据第二时钟的信号值选择性地输出从第一测试模式生成部分输出的测试数据或从第二测试模式产生部分输出的测试数据，从而将测试数据作为测试数据输入存储器。第二个时钟的频率是第一个时钟频率的一半。

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