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21. 发明授权

US5978294A Memory cell evaluation semiconductor device, method of fabricating the same and memory cell evaluation method 失效
标题翻译：存储单元评估半导体器件，其制造方法和存储单元评估方法
公开(公告)号：US5978294A
公开(公告)日：1999-11-02
申请号：US112506
申请日：1998-07-09
申请人： Shuichi Ueno , Tomohiro Yamashita , Hidekazu Oda , Shigeki Komori
发明人： Shuichi Ueno , Tomohiro Yamashita , Hidekazu Oda , Shigeki Komori
IPC分类号： G01R31/28 , G11C7/14 , G11C11/401 , G11C11/406 , G11C29/12 , G11C29/24 , H01L21/66 , H01L21/8242 , H01L27/108 , G11C7/02 , G11C11/24
CPC分类号： G11C7/14 , G11C11/406 , G11C29/24
摘要： A dummy cell part includes a capacitor having a first end which is connected to one of a plurality of pads and a P-N junction element having a first end which is connected to one of the plurality of pads and a second end which is connected to one of the plurality of pads . A sense part is connected to a second end of the capacitor , for sensing a potential on the second end of the capacitor and outputting the result of sensing to one of the plurality of pads . Thus, a memory cell evaluation semiconductor device which can evaluate a single memory cell, a method of fabricating the same and a memory cell evaluation method are obtained.
摘要翻译：虚设单元部分31包括具有连接到多个焊盘<2>中的一个的第一端的电容器<311>和具有连接到多个焊盘中的一个的第一端的PN结元件<312> 的焊盘<2>和连接到多个焊盘<2>之一的第二端。感测部分<32>连接到电容器<311>的第二端，用于感测电容器<311>的第二端上的电位，并将感测结果输出到多个焊盘<2>之一。因此，可以获得能够评估单个存储单元的存储单元评估半导体器件，其制造方法和存储单元评估方法。

22. 发明授权

US09102786B2 Epoxy resin composition, cured object obtained therefrom, and light-emitting diode 有权
标题翻译：环氧树脂组合物，由其获得的固化物和发光二极管
公开(公告)号：US09102786B2
公开(公告)日：2015-08-11
申请号：US12678166
申请日：2008-09-22
申请人： Takashi Sato , Shuichi Ueno , Takeshi Koyama
发明人： Takashi Sato , Shuichi Ueno , Takeshi Koyama
IPC分类号： H01L23/29 , C08L63/00 , C08K5/13 , C08G59/24 , H01L51/52 , C08G59/22 , C08G59/42 , H01L33/56
CPC分类号： C08G59/24 , C08G59/226 , C08G59/42 , C08L63/00 , H01L33/56 , H01L51/5237 , H01L51/5246 , C08L2666/22
摘要： Provided are an epoxy resin composition including acid anhydrides (A) and epoxy resins (B), in which: (a) cyclohexane-1,2,4-tricarboxylic acid-1,2-anhydride accounts for 50 to 90 mass % of the acid anhydrides (A); (b) an alicyclic epoxy resin compound accounts for 30 to 90 mass % of the epoxy resins (B) and an epoxy resin compound represented by the following general formula (1) accounts for 10 to 50 mass % of the epoxy resins (B); and (c) contents of the acid anhydrides (A) and the epoxy resins (B) are such that a blending equivalent ratio between the acid anhydrides and the epoxy resins ranges from 0.4 to 0.7, a cured product of the composition, and a light-emitting diode. The epoxy resin composition has the following characteristics. That is, (1) the composition has a low viscosity after the mixing, a low degree of viscosity increase in standing at room temperature, and excellent workability, (2) the composition has satisfactory curability even when no curing accelerator is added, and (3) a cured product is colorless and transparent, has crack resistance, and changes its color to a small extent with long-term light irradiation and heating. The composition is suitable for an encapsulant for a photoelectric conversion element such as a blue LED or white LED. (In the formula, R's each independently represent a hydrogen atom or a methyl group, m represents an integer of 1 to 3, and n represents an integer of 2 to 8.)
摘要翻译：提供一种包含酸酐（A）和环氧树脂（B））的环氧树脂组合物，其中：（a）环己烷-1,2,4-三羧酸-1,2-酐占50〜90质量％酸酐（A）; （b）环氧树脂（B）的脂环族环氧树脂化合物占30〜90质量％，由通式（1）表示的环氧树脂化合物占环氧树脂（B）的10〜50质量％ ; 和（c）酸酐（A）和环氧树脂（B）的含量使得酸酐与环氧树脂的混合当量比为0.4〜0.7，组合物的固化物和光发光二极管。环氧树脂组合物具有以下特征。也就是说，（1）组合物在混合后具有低粘度，在室温下的静置粘度增加低，加工性优异，（2）即使不加入固化促进剂，组合物也具有令人满意的固化性，（ 3）固化产物无色透明，具有抗裂性，并在长时间的光照射和加热下颜色变化很小。该组合物适用于诸如蓝色LED或白色LED的光电转换元件的密封剂。（式中，R 3各自独立地表示氢原子或甲基，m表示1〜3的整数，n表示2〜8的整数。）

23. 发明申请

US20120301975A1 SEMICONDUCTOR DEVICE INCLUDING A MAGNETIC TUNNEL JUNCTION DEVICE INCLUDING A LAMINATED STRUCTURE AND MANUFACTURING METHOD THEREFOR 有权
标题翻译：包括包括层压结构在内的磁性隧道连接装置的半导体装置及其制造方法
公开(公告)号：US20120301975A1
公开(公告)日：2012-11-29
申请号：US13566739
申请日：2012-08-03
申请人： Ryoji Matsuda , Shuichi Ueno , Haruo Furuta , Takashi Takenaga , Takeharu Kuroiwa
发明人： Ryoji Matsuda , Shuichi Ueno , Haruo Furuta , Takashi Takenaga , Takeharu Kuroiwa
IPC分类号： H01L21/02
CPC分类号： H01L43/08 , H01L27/228 , H01L43/12
摘要： A semiconductor device having a MTJ device excellent in operating characteristics and a manufacturing method therefor are provided. The MTJ device is formed of a laminated structure which is obtained by laminating a lower magnetic film, a tunnel insulating film, and an upper magnetic film in this order. The lower and upper magnetic films contain noncrystalline or microcrystalline ferrocobalt boron (CoFeB) as a constituent material. The tunnel insulating film contains aluminum oxide (AlOx) as a constituent material. A CAP layer is formed over the upper magnetic film and a hard mask is formed over the CAP layer. The CAP layer contains a substance of crystalline ruthenium (Ru) as a constituent material and the hard mask contains a substance of crystalline tantalum (Ta) as a constituent material. The film thickness of the hard mask is larger than that of the CAP layer.
摘要翻译：提供一种具有优异的操作特性的MTJ装置的半导体装置及其制造方法。 MTJ装置由层叠结构形成，其通过依次层叠下磁性膜，隧道绝缘膜和上磁性膜而获得。下部和上部磁性膜含有非结晶或微晶铁硼（CoFeB）作为构成材料。隧道绝缘膜包含氧化铝（AlOx）作为构成材料。在上磁性膜上形成CAP层，在CAP层上形成硬掩模。 CAP层包含结晶钌（Ru）作为构成材料的物质，硬掩模含有结晶钽（Ta）作为构成材料的物质。硬掩模的膜厚大于CAP层的膜厚。

24. 发明申请

US20120142822A1 THERMOSETTING RESIN COMPOSITION FOR SURFACE PROTECTION LAYERS 有权
标题翻译：表面保护层的热固性树脂组合物
公开(公告)号：US20120142822A1
公开(公告)日：2012-06-07
申请号：US13389972
申请日：2010-08-06
申请人： Takashi Sato , Shuichi Ueno
发明人： Takashi Sato , Shuichi Ueno
IPC分类号： C08K5/07 , C08K5/05 , B05D5/00 , C08L63/02 , B05D3/00 , C08L63/00 , C08K5/09
CPC分类号： C08G59/4215 , C08L63/00 , C09D163/00
摘要： A thermosetting resin composition which includes an epoxy-containing component and a curing agent component containing a cyclohexanetricarboxylic anhydride. The cured product of the thermosetting resin composition is excellent in surface hardness, solvent resistance, transparency, and adhesion to substrate, and is useful as a surface protection layer of the substrate.
摘要翻译：一种热固性树脂组合物，其包含含环氧基的组分和含有环己烷三羧酸酐的固化剂组分。热硬化性树脂组合物的固化物的表面硬度，耐溶剂性，透明性和与基材的粘合性优异，可用作基材的表面保护层。

25. 发明申请

US20090315128A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090315128A1
公开(公告)日：2009-12-24
申请号：US12549695
申请日：2009-08-28
申请人： Haruo Furuta , Ryoji Matsuda , Shuichi Ueno , Takeharu Kuroiwa
发明人： Haruo Furuta , Ryoji Matsuda , Shuichi Ueno , Takeharu Kuroiwa
IPC分类号： H01L43/00
CPC分类号： H01L43/08 , B82Y10/00 , H01L27/228 , H01L43/12
摘要： The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.
摘要翻译：具有包含记忆精度不劣化的TMR膜的存储单元的半导体装置及其制造方法。在数字线的形成区域的一部分的TMR下电极的平面图中对应的区域选择性地形成TMR元件（TMR膜，TMR上电极）。 TMR上电极由Ta的30-100nm厚度形成，并且在制造过程中也用作硬掩模。在TMR元件的整个表面和TMR下电极的整个表面上形成由LT-SiN形成的层间绝缘膜，覆盖包括TMR下电极的侧表面的整个表面的层间绝缘膜和包括LT-SiN。形成覆盖整个表面并包含SiO 2的层间绝缘膜。

26. 发明授权

US07554837B2 Magnetic memory device 失效
标题翻译：磁存储器件
公开(公告)号：US07554837B2
公开(公告)日：2009-06-30
申请号：US12213505
申请日：2008-06-20
申请人： Yoshinori Okumura , Shuichi Ueno , Haruo Furuta
发明人： Yoshinori Okumura , Shuichi Ueno , Haruo Furuta
IPC分类号： G11C11/14 , G11C11/10
CPC分类号： H01L43/08 , B82Y10/00 , G11C11/15 , G11C11/1659 , G11C11/1675 , H01L27/228
摘要： A width and a thickness of a bit line are represented as W1 and T1, respectively, a thickness of a digit line is represented as T2, and a distance from a center of the digit line in a thickness direction to a center of a free layer of an MTJ element in the thickness direction is represented as L1. A width of the digit line is represented as W2, and a distance from a center of the bit line in the thickness direction to the center of the free layer of the MTJ element in the thickness direction is represented as L2. The distances L1 and L2 and the cross-sectional areas S1 and S2 are set in such a manner that when L1/L2≧1, a relation of (⅓)·(L1/L2)≦S2/S1≦1 is satisfied and when L1/L2≦1, a relation of 1≦S2/S1≦3(L1/L2) is satisfied.
摘要翻译：位线的宽度和厚度分别表示为W1和T1，数字线的厚度表示为T2，从数字线的中心到厚度方向的中心到自由层的中心的距离的厚度方向上的MTJ元件表示为L1。数字线的宽度表示为W2，从厚度方向的位线的中心到厚度方向的MTJ元件的自由层的中心的距离表示为L2。距离L1和L2以及横截面积S1和S2以如下方式设定：当L1 / L2> = 1时，（1/3）（L1 / L2）<= S2 / S1 <= 1，并且当L1 / L2 <= 1时，满足1 <= S2 / S1 <= 3（L1 / L2）的关系。

27. 发明申请

US20070108543A1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US20070108543A1
公开(公告)日：2007-05-17
申请号：US11593548
申请日：2006-11-07
申请人： Haruo Furuta , Ryoji Matsuda , Shuichi Ueno , Takeharu Kuroiwa
发明人： Haruo Furuta , Ryoji Matsuda , Shuichi Ueno , Takeharu Kuroiwa
IPC分类号： H01L43/00
CPC分类号： H01L43/08 , B82Y10/00 , H01L27/228 , H01L43/12
摘要： The semiconductor device which has a memory cell including the TMR film with which memory accuracy does not deteriorate, and its manufacturing method are obtained. A TMR element (a TMR film, a TMR upper electrode) is selectively formed in the region which corresponds in plan view on a TMR lower electrode in a part of formation area of a digit line. A TMR upper electrode is formed by 30-100 nm thickness of Ta, and functions also as a hard mask at the time of a manufacturing process. The interlayer insulation film formed from LT-SiN on the whole surface of a TMR element and the upper surface of a TMR lower electrode is formed, and the interlayer insulation film which covers the whole surface comprising the side surface of a TMR lower electrode, and includes LT-SiN is formed. The interlayer insulation film which covers the whole surface and includes SiO2 is formed.
摘要翻译：具有包含记忆精度不劣化的TMR膜的存储单元的半导体装置及其制造方法。在数字线的形成区域的一部分的TMR下电极的平面图中对应的区域选择性地形成TMR元件（TMR膜，TMR上电极）。 TMR上电极由Ta的30-100nm厚度形成，并且在制造过程中也用作硬掩模。在TMR元件的整个表面和TMR下电极的整个表面上形成由LT-SiN形成的层间绝缘膜，覆盖包括TMR下电极的侧表面的整个表面的层间绝缘膜和包括LT-SiN。形成覆盖整个表面并包括SiO 2的层间绝缘膜。

28. 发明授权

US06731535B1 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US06731535B1
公开(公告)日：2004-05-04
申请号：US10455523
申请日：2003-06-06
申请人： Tsukasa Ooishi , Shuichi Ueno , Shigehiro Kuge
发明人： Tsukasa Ooishi , Shuichi Ueno , Shigehiro Kuge
IPC分类号： G11C1114
CPC分类号： H01L27/224 , G11C11/16 , H01L27/228
摘要： A nonvolatile semiconductor memory device includes a silicon substrate, bit lines, word lines, and memory cells. The bit line is positioned above the main surface of the silicon substrate and the word line is provided to intersect the bit line. The memory cell is positioned at a region where the bit line and the word line intersect and has one end electrically connected to the bit line and the other end electrically connected to the word line. The memory cell includes a TMR element and an access diode electrically connected in series. The access diode includes an n-type silicon layer and a p-type silicon layer recrystallized by melting-recrystallization and has a pn junction at the interface between the n-type silicon layer and the p-type silicon layer. As a result, a nonvolatile semiconductor memory device reduced in size and having high performance can be manufactured inexpensively.
摘要翻译：非易失性半导体存储器件包括硅衬底，位线，字线和存储单元。位线位于硅衬底的主表面上方，并且字线被提供以与位线相交。存储单元位于位线和字线相交的区域，并且其一端电连接到位线，另一端电连接到字线。存储单元包括串联电连接的TMR元件和存取二极管。存取二极管包括n型硅层和通过熔融重结晶重结晶的p型硅层，并且在n型硅层和p型硅层之间的界面处具有pn结。结果，可以廉价地制造尺寸减小并且具有高性能的非易失性半导体存储器件。

29. 发明授权

US06475844B1 Field effect transistor and method of manufacturing same 失效
标题翻译：场效应晶体管及其制造方法相同
公开(公告)号：US06475844B1
公开(公告)日：2002-11-05
申请号：US09629485
申请日：2000-07-31
申请人： Hidekazu Oda , Tomohiro Yamashita , Shuichi Ueno
发明人： Hidekazu Oda , Tomohiro Yamashita , Shuichi Ueno
IPC分类号： H01L2972
CPC分类号： H01L27/10852 , H01L21/28518 , H01L27/10873 , H01L27/10888 , H01L27/10894 , H01L29/4983 , H01L29/66659
摘要： A silicided region (11a) is formed in part of a surface of a gate electrode (3a) which is far from a storage node when a diffusion region (7a) is connected to a bit line and a diffusion region (8a) is connected to the storage node. A silicided region (12a) is formed in a surface of the diffusion region (7a) connected to the bit line. A MOSFET which suppresses a leakage current from the storage node to the gate electrode and decreases the resistance of the diffusion region connected to the bit line and the resistance of said gate electrode is provided.
摘要翻译：当扩散区域（7a）连接到位线并且扩散区域（8a）连接到栅极电极（3a）的远离存储节点的表面的一部分中时，形成硅化区域（11a）存储节点。在与位线连接的扩散区域（7a）的表面形成硅化区域（12a）。提供一种MOSFET，其抑制从存储节点到栅电极的漏电流并且降低连接到位线的扩散区域的电阻和所述栅电极的电阻。

30. 发明授权

US06380036B1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US06380036B1
公开(公告)日：2002-04-30
申请号：US09694003
申请日：2000-10-23
申请人： Hidekazu Oda , Shuichi Ueno , Takehisa Yamaguchi
发明人： Hidekazu Oda , Shuichi Ueno , Takehisa Yamaguchi
IPC分类号： H01L21336
CPC分类号： H01L21/26506 , H01L29/1033 , H01L29/105 , H01L29/66575
摘要： A boron diffusion region is formed at a surface of a silicon substrate. A pair of n-type source/drain regions are formed at a surface of boron diffusion region. A gate electrode is formed at a region located between paired source/drain regions with a gate insulating film therebetween. A nitrogen implanted region is formed at the surface of silicon substrate located between paired n-type source/drain regions. Nitrogen implanted region has a peak nitrogen concentration at a position of a depth not exceeding 500 Å from the surface of silicon substrate. Thereby, a transistor structure which can be easily miniaturized can be obtained.
摘要翻译：在硅衬底的表面上形成硼扩散区。在硼扩散区的表面形成一对n型源/漏区。在位于成对的源/漏区之间的区域之间形成有栅极电极，其间具有栅极绝缘膜。在位于成对的n型源极/漏极区之间的硅衬底的表面处形成氮注入区。氮注入区域在硅衬底表面的深度不超过500的位置具有峰值氮浓度。由此，可以获得容易小型化的晶体管结构。

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