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21. 发明授权

US6015725A Vertical field effect transistor and manufacturing method thereof 失效
标题翻译：垂直场效应晶体管及其制造方法
公开(公告)号：US6015725A
公开(公告)日：2000-01-18
申请号：US914096
申请日：1997-08-19
申请人： Teruo Hirayama
发明人： Teruo Hirayama
IPC分类号： H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/115 , H01L29/78 , H01L29/788 , H01L29/792 , H01L21/8232
CPC分类号： H01L29/66666 , H01L21/823487 , H01L27/115 , H01L27/11556 , H01L29/66825 , H01L29/7827
摘要： A vertical field effect transistor (1) and a method of manufacturing thereof are disclosed, in which a buried layer (3) of a conduction type opposite to that of a substrate (2) is formed to a predetermined depth in the substrate (2) by ion implantation. The bottom of recess (2a) for forming a protrusion (2b) on the substrate (2) is located within the corresponding one of the buried layer (3). The width of the recess (2a) is set smaller than the width of the buried layer (3). The surface of the protrusion (2b) and the bottom of the recess (2a) are formed with impurities regions (4a, 4b; 5a, 5b) constituting a source and a drain, respectively. A channel length (L) of the channel region formed on the side wall of the protrusion (2b) is defined by the distance between the buried layer (3) and the impurities regions (5a, 5b) on the surface of the protrusion (2b).
摘要翻译：公开了一种垂直场效应晶体管（1）及其制造方法，其中在衬底（2）中形成与衬底（2）相反的导电类型的掩埋层（3）至预定深度，通过离子注入。用于在基板（2）上形成突起（2b）的凹部（2a）的底部位于相应的一个埋层（3）内。凹部（2a）的宽度被设定为小于掩埋层（3）的宽度。突起（2b）的表面和凹部（2a）的底部分别形成有构成源极和漏极的杂质区域（4a，4b; 5a，5b）。形成在突起（2b）的侧壁上的沟道区域的沟道长度（L）由突起（2b）表面上的掩埋层（3）和杂质区域（5a，5b）之间的距离限定）。

22. 发明授权

US6001680A Static random memory device 失效
标题翻译：静态随机存储设备
公开(公告)号：US6001680A
公开(公告)日：1999-12-14
申请号：US104913
申请日：1998-06-25
申请人： Minoru Ishida , Teruo Hirayama
发明人： Minoru Ishida , Teruo Hirayama
IPC分类号： G11C11/412 , H01L27/11 , H01L21/8244
CPC分类号： G11C11/412 , H01L27/1104
摘要： A static random access memory device (SRAM) keeping a resistance value of a resistance element at a predetermined level regardless a process variation, by improving a special margin of a diffusion layer region at which the resistance element is formed and a node for connecting a gate electrode thereto. In the SRAM, there is provided a diffusion layer region in a substrate, having a first part of which may form a the resistance element, a second part of which is connected to the drain or source of the MIS access transistor, and a third part of which is connected to the source or drain of the MIS driver transistor and is defined the node, and there is provided an electrode layer connecting the gate of the MIS driver transistor and the node in the diffusion layer region. The diffusion layer region is formed so that the diffusion layer region is bent at the first part which may form the resistance element and is defined the node and a first direction between the first part and the second part and a second direction between the first part and the third part intersect at an obtuse angle.
摘要翻译：一种静态随机存取存储器件（SRAM），通过改善形成电阻元件的扩散层区域的特殊余量和用于连接栅极的节点，将电阻元件的电阻值保持在预定水平而不管工艺变化如何电极。在SRAM中，在基板中设置有扩散层区域，其第一部分可以形成电阻元件，第二部分连接到MIS存取晶体管的漏极或源极，第三部分其连接到MIS驱动器晶体管的源极或漏极，并且被定义为节点，并且提供连接MIS驱动器晶体管的栅极和扩散层区域中的节点的电极层。扩散层区域被形成为使得扩散层区域在可形成电阻元件的第一部分处弯曲并且被限定为节点和第一部分与第二部分之间的第一方向以及在第一部分与第二部分之间的第二方向第三部分以钝角相交。

23. 发明授权

US5302187A Concentration process of gaseous chlorine 失效
标题翻译：气态氯的浓缩过程
公开(公告)号：US5302187A
公开(公告)日：1994-04-12
申请号：US975158
申请日：1992-11-12
申请人： Hiroyuki Itoh , Yoshitsugu Kono , Shinji Takenaka , Yukihiro Yoshikawa , Isao Kikuchi , Teruo Hirayama
发明人： Hiroyuki Itoh , Yoshitsugu Kono , Shinji Takenaka , Yukihiro Yoshikawa , Isao Kikuchi , Teruo Hirayama
IPC分类号： B01D53/04 , B01D53/047 , C01B7/01 , C01B7/07
CPC分类号： B01D53/02 , B01D53/047 , C01B7/01 , C01B7/0743 , B01D2253/102 , B01D2253/108 , B01D2256/12 , B01D2256/22 , B01D2257/2025 , B01D2257/504 , B01D2259/403 , Y02C10/08 , Y02P20/152
摘要： Disclosed herein is a process comprising introducing a chlorine-containing gas through an adsorbent to adsorb chlorine and thereafter reducing the pressure of the adsorbent to a pressure lower than that during the introduction, thereby obtaining an effluent gas with a higher chlorine concentration than that of the introduced gas. Among preferably usable adsorbents are zeolite, non-zeolite-type porous acidic oxides and active carbon.
摘要翻译： PCT No.PCT / JP90 / 01632 Sec。 371日期1991年8月15日 102（e）日期1991年8月15日PCT 1990年12月14日PCT PCT。出版物WO91 / 08824 日期：1991年6月27日。这里公开了一种方法，其包括通过吸附剂引入含氯气体以吸附氯，然后将吸附剂的压力降低至低于引入期间的压力，从而获得具有氯浓度高于导入气体。优选可用的吸附剂是沸石，非沸石型多孔酸性氧化物和活性炭。

24. 发明申请

US20130038818A1 DISPLAY DEVICE, METHOD OF MANUFACTURING THE SAME, AND ELECTRONIC APPARATUS 审中-公开
标题翻译：显示装置，其制造方法和电子装置
公开(公告)号：US20130038818A1
公开(公告)日：2013-02-14
申请号：US13561801
申请日：2012-07-30
申请人： Atsushi Toda , Teruo Hirayama
发明人： Atsushi Toda , Teruo Hirayama
IPC分类号： H05B33/14 , H05B33/10 , G02F1/13357 , B82Y20/00
CPC分类号： G02F1/133615 , G02F1/133617 , G02F2202/102 , G02F2202/106 , G02F2202/107 , G02F2202/108
摘要： A display device includes: a light source section that emits excitation light for each pixel; and a light emitting layer that includes a quantum dot and emits emission light for each of the pixels. The quantum dot generates, based on the excitation light, the emission light having a wavelength longer than a wavelength of the excitation light.
摘要翻译：一种显示装置，包括：对每个像素发射激发光的光源部; 以及包括量子点并发射每个像素的发射光的发光层。量子点基于激发光产生具有比激发光的波长长的波长的发射光。

25. 发明授权

US5831898A Static random access memory semiconductor layout 失效
标题翻译：静态随机存取存储器半导体布局
公开(公告)号：US5831898A
公开(公告)日：1998-11-03
申请号：US783209
申请日：1997-01-14
申请人： Minoru Ishida , Teruo Hirayama
发明人： Minoru Ishida , Teruo Hirayama
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： H01L27/1104 , G11C11/412 , Y10S257/904
摘要： A static random access memory device (SRAM) keeping a resistance value of a resistance element at a predetermined level regardless a process variation, by improving a special margin of a diffusion layer region at which the resistance element is formed and a node for connecting a gate electrode thereto. In the SRAM, there is provided a diffusion layer region in a substrate, having a first part of which may form a the resistance element, a second part of which is connected to the drain or source of the MIS access transistor, and a third part of which is connected to the source or drain of the MIS driver transistor and is defined the node, and there is provided an electrode layer connecting the gate of the MIS driver transistor and the node in the diffusion layer region. The diffusion layer region is formed so that the diffusion layer region is bent at the first part which may form the resistance element and is defined the node and a first direction between the first part and the second part and a second direction between the first part and the third part intersect at an obtuse angle.
摘要翻译：一种静态随机存取存储器件（SRAM），通过改善形成电阻元件的扩散层区域的特殊余量和用于连接栅极的节点，将电阻元件的电阻值保持在预定水平而不管工艺变化如何电极。在SRAM中，在基板中设置有扩散层区域，其第一部分可以形成电阻元件，第二部分连接到MIS存取晶体管的漏极或源极，第三部分其连接到MIS驱动器晶体管的源极或漏极，并且被定义为节点，并且提供连接MIS驱动器晶体管的栅极和扩散层区域中的节点的电极层。扩散层区域被形成为使得扩散层区域在可形成电阻元件的第一部分处弯曲并且被限定为节点和第一部分与第二部分之间的第一方向以及在第一部分与第二部分之间的第二方向第三部分以钝角相交。

26. 发明授权

US5169823A Method for stabilizing treatment of catalytic activity 失效
标题翻译：用于稳定催化活性处理的方法
公开(公告)号：US5169823A
公开(公告)日：1992-12-08
申请号：US721332
申请日：1991-07-01
申请人： Yukihiro Yoshikawa , Tooru Hihara , Teruo Hirayama , Kunihiro Yamada , Shinji Takenaka
发明人： Yukihiro Yoshikawa , Tooru Hihara , Teruo Hirayama , Kunihiro Yamada , Shinji Takenaka
IPC分类号： B01J23/26 , B01J37/06 , C01B7/04
CPC分类号： C01B7/04 , B01J23/26 , B01J37/06 , Y02P20/228
摘要： Disclosed herein is a method for the stabilizing treatment of a catalyst comprising washing the catalyst with hot washing water following the preparation of the catalyst, the catalyst being composed principally of chromium oxide and used in the production of chlorine by the oxidation of hydrogen chloride with an oxygen-containing gas, thereby improving its catalytic activity and prolonging its life.

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