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21. 发明申请

US20060038229A1 Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：US20060038229A1
公开(公告)日：2006-02-23
申请号：US11116327
申请日：2005-04-28
申请人： Yoshinori Tsuchiya , Junji Koga
发明人： Yoshinori Tsuchiya , Junji Koga
IPC分类号： H01L21/00 , H01L27/01 , H01L21/84 , H01L27/12 , H01L31/0392
CPC分类号： H01L21/823814 , H01L21/26513 , H01L21/28061 , H01L21/823835 , H01L21/84 , H01L29/517 , H01L29/518 , H01L29/665 , H01L29/66643 , H01L29/7839
摘要： Disclosed is a semiconductor device comprising a semiconductor substrate having isolation regions, and a MIS transistor comprising a gate electrode formed above the semiconductor substrate with a gate insulating film interposed therebetween, and a pair of contact layers formed on the semiconductor substrate sandwiching the gate electrode, the contact layers having an interfacial layer at an interface between the semiconductor substrate and the contact layers, the interfacial layer comprising a metal silicide containing at least one selected from a group consisting of Er, Gd, Tb, Dy, Ho, Tm, Yb, Lu, and Pt.
摘要翻译：公开了一种半导体器件，其包括具有隔离区域的半导体衬底，以及MIS晶体管，其包括形成在半导体衬底上方的栅电极，栅极绝缘膜插入其间的栅极电极和形成在夹持栅电极的半导体衬底上的一对接触层，所述接触层在所述半导体衬底和所述接触层之间的界面处具有界面层，所述界面层包含含有选自Er，Gd，Tb，Dy，Ho，Tm，Yb中的至少一种的金属硅化物，卢和铂。

22. 发明授权

US07977182B2 Method of manufacturing MISFET with low contact resistance 失效
标题翻译：具有低接触电阻的MISFET的制造方法
公开(公告)号：US07977182B2
公开(公告)日：2011-07-12
申请号：US12323770
申请日：2008-11-26
申请人： Yoshifumi Nishi , Yoshinori Tsuchiya , Takashi Yamauchi , Junji Koga
发明人： Yoshifumi Nishi , Yoshinori Tsuchiya , Takashi Yamauchi , Junji Koga
IPC分类号： H01L21/8238 , H01L29/04 , H01L29/10 , H01L31/036 , H01L21/285
CPC分类号： H01L29/4975 , H01L21/26506 , H01L21/28097 , H01L21/28518 , H01L21/28537 , H01L21/324 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L23/485 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.
摘要翻译：这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。第二金属沉积在金属半导体化合物层上。通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。

23. 发明申请

US20090152652A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND THE SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件和半导体器件的方法
公开(公告)号：US20090152652A1
公开(公告)日：2009-06-18
申请号：US12323770
申请日：2008-11-26
申请人： Yoshifumi NISHI , Yoshinori Tsuchiya , Takashi Yamauchi , Junji Koga
发明人： Yoshifumi NISHI , Yoshinori Tsuchiya , Takashi Yamauchi , Junji Koga
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/4975 , H01L21/26506 , H01L21/28097 , H01L21/28518 , H01L21/28537 , H01L21/324 , H01L21/823814 , H01L21/823835 , H01L21/823842 , H01L23/485 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Described herein is a method of manufacturing a semiconductor device realizing higher performance by reducing contact resistance of an electrode. In the method, a gate insulating film, a gate electrode are formed on a semiconductor substrate. A first metal is deposited substrate, and a metal semiconductor compound layer is formed on the surface of the semiconductor substrate by making the first metal and the semiconductor substrate react each other by a first heat treatment. Ions having a mass equal to or larger than atomic weight of Si are implanted into the metal semiconductor compound layer. A second metal is deposited on the metal semiconductor compound layer. An interface layer is formed by making the second metal segregated at an interface between the metal semiconductor compound layer and the semiconductor substrate by diffusing the second metal through the metal semiconductor compound layer by a second heat treatment.
摘要翻译：这里描述的是通过降低电极的接触电阻来制造实现更高性能的半导体器件的方法。在该方法中，在半导体衬底上形成栅极绝缘膜，栅电极。第一金属是沉积衬底，并且通过使第一金属和半导体衬底通过第一热处理而彼此反应，在半导体衬底的表面上形成金属半导体化合物层。将具有等于或大于Si原子量的质量的离子注入到金属半导体化合物层中。第二金属沉积在金属半导体化合物层上。通过使第二金属通过第二热处理使金属半导体化合物层扩散而使第二金属在金属半导体化合物层和半导体基板之间的界面分离而形成界面层。

24. 发明授权

US08994034B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08994034B2
公开(公告)日：2015-03-31
申请号：US13404411
申请日：2012-02-24
申请人： Tatsuo Shimizu , Yoshinori Tsuchiya , Takashi Shinohe
发明人： Tatsuo Shimizu , Yoshinori Tsuchiya , Takashi Shinohe
IPC分类号： H01L29/16 , H01L21/04 , H01L29/739 , H01L29/45 , H01L29/66 , H01L29/78 , H01L21/265 , H01L29/08
CPC分类号： H01L29/7802 , H01L21/0485 , H01L21/049 , H01L21/26506 , H01L29/0878 , H01L29/1608 , H01L29/45 , H01L29/66068 , H01L29/7395 , H01L29/7813
摘要： Disclosed is a semiconductor device including: a first electrode formed of a conductive material; a p-type first silicon carbide (SiC) semiconductor section and an n-type second SiC semiconductor section 230, connected to the first electrode, containing carbon (C) such that a surface density distribution has a peak at a first interface with the first electrode.
摘要翻译：公开了一种半导体器件，包括：由导电材料形成的第一电极; 连接到第一电极的含有碳（C）的p型第一碳化硅（SiC）半导体部分和n型第二SiC半导体部分230，使得表面密度分布在第一界面处具有与第一电极。

25. 发明授权

US08766334B2 Semiconductor device with low resistance gate electrode and method of manufacturing the same 失效
标题翻译：具有低电阻栅电极的半导体器件及其制造方法
公开(公告)号：US08766334B2
公开(公告)日：2014-07-01
申请号：US13602704
申请日：2012-09-04
申请人： Yoshinori Tsuchiya
发明人： Yoshinori Tsuchiya
IPC分类号： H01L29/76 , H01L29/94 , H01L27/01 , H01L27/12 , H01L27/088 , H01L21/336 , H01L21/8222
CPC分类号： H01L29/78 , H01L21/049 , H01L21/28008 , H01L21/28273 , H01L21/32155 , H01L29/1608 , H01L29/4933 , H01L29/4966 , H01L29/66068 , H01L29/7395 , H01L29/7802
摘要： A semiconductor device of an embodiment includes: a substrate formed of a single-crystal first semiconductor; a gate insulating film on the substrate; a gate electrode including a layered structure of a semiconductor layer formed of a polycrystalline second semiconductor and a metal semiconductor compound layer formed of a first metal semiconductor compound that is a reaction product of a metal and the second semiconductor; and electrodes formed of a second metal semiconductor compound that is a reaction product of the metal and the first semiconductor, and formed on the substrate with the gate electrode interposed therebetween, and an aggregation temperature of the first metal semiconductor compound on the polycrystalline second semiconductor is lower than an aggregation temperature of the second metal semiconductor compound on the single-crystal first semiconductor, and a cluster-state high carbon concentration region is included in an interface between the semiconductor layer and the metal semiconductor compound layer.
摘要翻译：实施例的半导体器件包括：由单晶体第一半导体形成的衬底; 基板上的栅极绝缘膜; 包括由多晶第二半导体形成的半导体层的层叠结构的栅电极和由作为金属与第二半导体的反应产物的第一金属半导体化合物形成的金属半导体化合物层; 以及由金属和第一半导体的反应产物形成的第二金属半导体化合物形成的电极，并且在基板上形成有栅极电极，多晶二次半导体上的第一金属半导体化合物的聚集温度为低于单晶体第一半导体上的第二金属半导体化合物的聚集温度，并且在半导体层和金属半导体化合物层之间的界面中包含簇状态的高碳浓度区域。

26. 发明申请

US20120049281A1 SEMICONDUCTOR DEVICE WITH EFFECTIVE WORK FUNCTION CONTROLLED METAL GATE 审中-公开
标题翻译：具有有效工作功能的半导体器件控制金属栅
公开(公告)号：US20120049281A1
公开(公告)日：2012-03-01
申请号：US12870011
申请日：2010-08-27
申请人： Yoshinori Tsuchiya , Ryosuke Iijima , Atsushi Yagishita
发明人： Yoshinori Tsuchiya , Ryosuke Iijima , Atsushi Yagishita
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L29/785 , H01L29/66795
摘要： According to one embodiment, gate electrodes of a multi-gate field effect transistors and methods of making a gate electrode of a multi-gate field effect transistor are provided. The gate electrode can contain a semiconductor substrate; a dielectric layer over the semiconductor substrate; a fin over the dielectric layer; a gate insulating layer over the side surfaces of the fin; a gate electrode layer over the fin; and a polysilicon layer over the fin. The gate electrode does not contain a gate insulating layer over the upper surface of the dielectric layer except portions of the upper surface of the dielectric layer that contact with the side surfaces of the gate insulating layer formed over the side surface of the fin. In another embodiment, the gate electrode can contain an oxygen diffusion barrier layer or a first oxygen diffusion layer over the upper surface of the dielectric layer.
摘要翻译：根据一个实施例，提供了多栅极场效应晶体管的栅极和制造多栅极场效应晶体管的栅电极的方法。栅电极可以包含半导体衬底; 半导体衬底上的电介质层; 电介质层上的翅片; 在翅片的侧表面上的栅极绝缘层; 翅片上的栅极电极层; 和鳍上的多晶硅层。栅电极除电介质层上表面的与栅极侧表面上形成的栅极绝缘层的侧面接触的部分以外，在电介质层的上表面上不包含栅极绝缘层。在另一个实施例中，栅电极可以在电介质层的上表面上包含氧扩散阻挡层或第一氧扩散层。

27. 发明授权

US08053300B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08053300B2
公开(公告)日：2011-11-08
申请号：US11841817
申请日：2007-08-20
申请人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分的第一电介质面向第一金属栅电极。

28. 发明申请

US20100171184A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20100171184A1
公开(公告)日：2010-07-08
申请号：US12654490
申请日：2009-12-22
申请人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
发明人： Reika Ichihara , Yoshinori Tsuchiya , Masato Koyama , Akira Nishiyama
IPC分类号： H01L27/092
CPC分类号： H01L21/823857 , H01L21/823462
摘要： A semiconductor device includes a semiconductor substrate, an nMISFET formed on the substrate, the nMISFET including a first dielectric formed on the substrate and a first metal gate electrode formed on the first dielectric and formed of one metal element selected from Ti, Zr, Hf, Ta, Sc, Y, a lanthanoide and actinide series and of one selected from boride, silicide and germanide compounds of the one metal element, and a pMISFET formed on the substrate, the pMISFET including a second dielectric formed on the substrate and a second metal gate electrode formed on the second dielectric and made of the same material as that of the first metal gate electrode, at least a portion of the second dielectric facing the second metal gate electrode being made of an insulating material different from that of at least a portion of the first dielectric facing the first metal gate electrode.
摘要翻译：半导体器件包括半导体衬底，形成在衬底上的nMISFET，nMISFET包括形成在衬底上的第一电介质和形成在第一电介质上的第一金属栅极，并由选自Ti，Zr，Hf， Ta，Sc，Y，镧系元素和锕系和选自所述一种金属元素的硼化物，硅化物和锗化合物的一种，以及形成在所述衬底上的pMISFET，所述pMISFET包括形成在所述衬底上的第二电介质和第二金属栅电极形成在第二电介质上并由与第一金属栅电极相同的材料制成，第二电介质面向第二金属栅电极的至少一部分由绝缘材料制成，绝缘材料与至少一部分的第一电介质面向第一金属栅电极。

29. 发明授权

US07745888B2 Method of making p-channel and n-channel MIS transistors using single film formation of TaC 有权
标题翻译：使用TaC单膜形成制造p沟道和n沟道MIS晶体管的方法
公开(公告)号：US07745888B2
公开(公告)日：2010-06-29
申请号：US12232078
申请日：2008-09-10
申请人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
发明人： Masato Koyama , Reika Ichihara , Yoshinori Tsuchiya , Yuuichi Kamimuta , Akira Nishiyama
IPC分类号： H01L29/76
CPC分类号： H01L21/823842
摘要： A semiconductor device includes a substrate, a p-channel MIS transistor formed on an n-type well on the substrate, having a first gate dielectric and a first gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 80% or more, and an n-channel MIS transistor formed on a p-type well on the substrate, having a second gate dielectric and a second gate electrode formed thereon and formed of a Ta—C alloy wherein a crystal orientation ratio of a TaC (111) face in a film thickness direction [TaC (111) face/{TaC (111) face+TaC (200) face}] is 60% or less.
摘要翻译：半导体器件包括衬底，形成在衬底上的n型阱上的p沟道MIS晶体管，具有形成在其上并由Ta-C合金形成的第一栅极电介质和第一栅电极，其中晶体取向比例膜厚方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]的TaC（111）面为80％以上，n型沟道MIS晶体管形成在p- 在基板上良好地形成具有形成在其上的第二栅极电介质和第二栅电极，并且由TaC（111）在膜厚度方向[TaC（111）面/ {TaC（111）面+ TaC（200）面}]为60％以下。

30. 发明授权

US07718521B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07718521B2
公开(公告)日：2010-05-18
申请号：US12133605
申请日：2008-06-05
申请人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
发明人： Masato Koyama , Akira Nishiyama , Yoshinori Tsuchiya , Reika Ichihara
IPC分类号： H01L21/3205
CPC分类号： H01L21/823842 , H01L21/28079 , H01L21/28088 , H01L29/495 , H01L29/4966 , H01L29/517
摘要： There is disclosed a semiconductor device comprising a P-channel MIS transistor which includes an N-type semiconductor layer, a first gate insulating layer formed on the N-type semiconductor layer and containing a carbon compound of a metal, and an N-channel MIS transistor which includes a P-type semiconductor layer, a second gate insulating layer formed on the P-type semiconductor layer, and a second gate electrode formed on the second gate insulating layer.
摘要翻译：公开了一种包括P沟道MIS晶体管的半导体器件，其包括N型半导体层，形成在N型半导体层上并含有金属的碳化合物的第一栅极绝缘层和N沟道MIS 晶体管，其包括P型半导体层，形成在P型半导体层上的第二栅极绝缘层和形成在第二栅极绝缘层上的第二栅电极。

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