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    • 22. 发明申请
    • Plasma cutter, and plasma cutter power supply system
    • 等离子切割机和等离子切割机供电系统
    • US20080093347A1
    • 2008-04-24
    • US11907838
    • 2007-10-18
    • Yoshihiro YamaguchiTakahiro Iriyama
    • Yoshihiro YamaguchiTakahiro Iriyama
    • H05H1/36B23K9/10H05H1/26
    • H05H1/36
    • In a main circuit 11 of the plasma cutter power supply device 6, a plurality of DC power units 14-1, . . . 14-n of low capacity are connected in parallel on their DC output sides, and are connected to a plasma torch 20. Each power unit 14-1, . . . 14-n can operate asynchronously and independently from each other. The power supply control device 6 controls the number of power units to be operated, and the intensity of output electrical current at which each of them is to be operated, according to the cutting conditions (the nature of the material to be cut, its thickness, and the cutting speed) and according to the number of power units which can be operated. If some of the power units are faulty, the power supply control device 6 controls the cutting conditions which can be accepted, according to the number of normal power units.
    • 在等离子切割器电源装置6的主电路11中,多个直流电力单元14-1, 。 。 14 -n的低容量在其直流输出侧并联连接,并连接到等离子体焰炬20。 每个电源单元14-1,。 。 。 14 -n可以彼此异步和独立地操作。 电源控制装置6根据切割条件(待切割材料的性质,其厚度等)来控制要操作的功率单元的数量和要各自操作的输出电流的强度 ,切割速度)以及可以操作的动力单元的数量。 如果一些动力单元有故障,则电源控制装置6根据正常功率单元的数量来控制可以接受的切割条件。
    • 24. 发明授权
    • Pressed-contact type semiconductor device
    • 压接式半导体器件
    • US07301178B2
    • 2007-11-27
    • US11212602
    • 2005-08-29
    • Yoshihiro YamaguchiKenji Oota
    • Yoshihiro YamaguchiKenji Oota
    • H01L29/74
    • H01L29/0661H01L24/72H01L29/0615H01L29/0657H01L29/32H01L29/74H01L2924/0102H01L2924/1301H01L2924/00
    • A P++-type first diffusion layer is formed by diffusing P-type impurities on a front side of an N−-type semiconductor substrate, and an N-type fourth diffusion layer which is shallower than the first diffusion layer is formed by diffusing N-type impurities on the front side, and a P-type second diffusion layer is locally formed in a ring-shape so as to be exposed on the lateral side by diffusing P-type impurities on the back side, and P-type impurities are diffused on the back side of the substrate and a P+-type third diffusion layer is locally formed so as to be distributed inward from the second diffusion layer and not to be exposed to the lateral side, and the P-type second diffusion layer and the P+-type third diffusion layer are formed in the two-stage structure, thereby various characteristics can be improved.
    • AP ++类型的第一扩散层是通过在N +型半导体衬底的正面扩散P型杂质形成的,N型第四扩散层 通过在前侧扩散N型杂质而形成比第一扩散层浅的层,并且P型第二扩散层局部形成为环状,以便通过扩散P而暴露在侧面 型杂质,P型杂质扩散到基板的背面,局部地形成P +型第三扩散层,以从第二层向内分布 扩散层并且不暴露于侧面,并且P型第二扩散层和P + +型第三扩散层形成在两级结构中,因此可以有各种特性 改进。
    • 25. 发明申请
    • SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING
    • 半导体器件及其制造方法
    • US20070262410A1
    • 2007-11-15
    • US11742133
    • 2007-04-30
    • Syotaro OnoYusuke KawaguchiYoshihiro YamaguchiMiwako Akiyama
    • Syotaro OnoYusuke KawaguchiYoshihiro YamaguchiMiwako Akiyama
    • H01L29/00
    • H01L29/872H01L27/0727H01L29/66143H01L29/8725
    • A semiconductor device includes: a semiconductor layer of a first conductivity type, a plurality of trenches provided on a major surface side of the semiconductor layer, an insulating film provided on an inner wall surface and on top of the trench, a conductive material surrounded by the insulating film and filling the trench, a first semiconductor region of a second conductivity type provided between the trenches, a second semiconductor region of the first conductivity type provided in a surface portion of the first semiconductor region, a mesa of the semiconductor layer provided between the trenches of a Schottky barrier diode region adjacent to a transistor region including the first semiconductor region and the second semiconductor region, a control electrode connected to the conductive material filling the trench of the transistor region and a main electrode provided in contact with a surface of the first semiconductor region, the second semiconductor region, a surface of the mesa and a part of the conductive material filling the trench of the Schottky barrier diode region. The part is exposed through the insulating film.
    • 半导体器件包括:第一导电类型的半导体层,设置在半导体层的主表面侧的多个沟槽,设置在内壁表面上和沟槽顶部上的绝缘膜,由 绝缘膜并填充沟槽,设置在沟槽之间的第二导电类型的第一半导体区域,设置在第一半导体区域的表面部分中的第一导电类型的第二半导体区域,设置在第一半导体区域之间的半导体层的台面 与包括第一半导体区域和第二半导体区域的晶体管区域相邻的肖特基势垒二极管区域的沟槽,连接到填充晶体管区域的沟槽的导电材料的控制电极和与第一半导体区域和第二半导体区域的表面接触的主电极 第一半导体区域,第二半导体区域,台面的表面 以及填充肖特基势垒二极管区域的沟槽的导电材料的一部分。 该部件通过绝缘膜曝光。
    • 28. 发明申请
    • Trench-gate semiconductor device and manufacturing method of trench-gate semiconductor device
    • 沟槽栅半导体器件及沟槽栅极半导体器件的制造方法
    • US20070023793A1
    • 2007-02-01
    • US11484664
    • 2006-07-12
    • Yoshihiro YamaguchiYusuke KawaguchiSyotaro Ono
    • Yoshihiro YamaguchiYusuke KawaguchiSyotaro Ono
    • H01L29/76H01L21/336
    • H01L29/7813H01L29/0696H01L29/1095H01L29/66734
    • Disclosed is a trench-gate semiconductor device including: a trench gate structure; a source layer having a first conductivity type, facing a gate electrode via a gate insulating film, and having a top plane; a base layer having a second conductivity type, being adjacent to the source layer, and facing the gate electrode via the gate insulating film; a semiconductor layer having the first conductivity type, being adjacent to the base layer, and facing the gate electrode via the gate insulating film without contacting the source layer; and a contact layer having the second conductivity type, contacting the source layer and base layer, having a top plane continuing with the top plane of the source layer, and having two or more peaks in an impurity concentration value profile in a depth direction from the top plane thereof, the peaks being positioned shallower than a formed depth of the source layer.
    • 公开了一种沟槽栅半导体器件,包括:沟槽栅极结构; 具有第一导电类型的源极层,经由栅极绝缘膜面对栅电极,并具有顶面; 具有第二导电类型的基底层,与源极层相邻,并且经由栅极绝缘膜面对栅电极; 具有第一导电类型的半导体层,与基底层相邻,并且经由栅极绝缘膜面对栅电极而不接触源极层; 以及具有第二导电类型的接触层,与源极层和基极层接触,具有与源极层的顶部平面连续的顶面,并且具有两个或更多个沿着深度方向的杂质浓度值分布中的峰 峰位于比源层的形成深度浅的位置。
    • 30. 发明授权
    • Wireless communication RF circuit and communication apparatus including the same
    • 无线通信RF电路和包括其的通信设备
    • US07133641B2
    • 2006-11-07
    • US10497513
    • 2003-04-23
    • Tsutomi IekiYoshihiro Yamaguchi
    • Tsutomi IekiYoshihiro Yamaguchi
    • H04B7/00H04B1/40H04Q5/22
    • G06K19/0723H04B1/44H04B1/48
    • A wireless communication RF circuit includes a transmitting-and-receiving antenna, a modulator circuit, an SPST switching circuit, and a demodulator circuit, which are arranged in a sequence. Upon signal reception, the SPST switching circuit is switched ON, and the demodulator circuit extracts a signal wave from a signal received by the antenna and outputs the signal wave to a control circuit. Upon signal transmission, the SPST switching circuit is switched OFF, and the modulator circuit mixes transmission data supplied from the control circuit with a carrier and outputs the carrier to the antenna. Only a single antenna is required. Upon signal reception, the influence of the modulator circuit is negligible. Upon signal transmission, the SPST switching circuit is switched OFF, thus the effect of the demodulator circuit is negligible, which greatly reduces loss.
    • 无线通信RF电路包括按顺序排列的发送和接收天线,调制器电路,SPST切换电路和解调器电路。 信号接收后,SPST切换电路接通,解调电路从天线接收的信号中提取信号波,并将信号波输出到控制电路。 信号传输时,SPST切换电路切换为OFF,调制电路将从控制电路提供的发送数据与载波混合,并将载波输出到天线。 只需要一根天线。 在信号接收时,调制器电路的影响可以忽略不计。 在信号传输时,SPST切换电路关闭,解调电路的影响可以忽略不计,大大降低了损耗。