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    • 24. 发明授权
    • System for power facility navigation
    • 电力设施导航系统
    • US08473203B2
    • 2013-06-25
    • US12341768
    • 2008-12-22
    • Jin Ho ShinYoung Il KimBong Jae LeeJae Ju Song
    • Jin Ho ShinYoung Il KimBong Jae LeeJae Ju Song
    • G01C21/30G06Q50/06
    • G01C21/3605G01C21/30G06Q10/047
    • A system for power facility navigation is disclosed. For rapid dispatch in the field service including power failure recovery and maintenance, the destination location can be set using various items such as pole numbers, computerization codes, customer names, trade names, equipment numbers and GIS coordinates. Destination location setting and path finding can be performed in order of priorities assigned to these items and in consideration of characteristics of field service activities. Location coordinates are received through a GPS receiver, coordinate conversion is performed according to a facility GIS coordinate system, and map matching is processed when GPS coordinates do not match facility GIS coordinates. The road network database is composed of linear array structures and the structure of a link is configured to include information regarding all other links connected to the start node and end node in a manner that link information and node attributes are integrated together.
    • 公开了电力设施导航系统。 为了快速派遣现场服务,包括停电恢复和维护,可以使用诸如极数,计算机代码,客户名称,商品名称,设备编号和GIS坐标等各种项目设置目的地位置。 可以按照分配给这些项目的优先次序并考虑现场服务活动的特点来执行目的地位置设置和路径查找。 通过GPS接收机接收位置坐标,根据设备GIS坐标系进行坐标转换,GPS坐标与设备GIS坐标不匹配时处理地图匹配。 道路网络数据库由线性阵列结构组成,并且链路的结构被配置为以链接信息和节点属性集成在一起的方式包括关于连接到起始节点和结束节点的所有其他链路的信息。
    • 25. 发明授权
    • Conversion and processing of deep color video in a single clock domain
    • 在单个时钟域内转换和处理深色视频
    • US08379145B2
    • 2013-02-19
    • US13217138
    • 2011-08-24
    • Hoon ChoiDaekyeung KimWooseung YangYoung Il Kim
    • Hoon ChoiDaekyeung KimWooseung YangYoung Il Kim
    • H04N7/01H04N11/20H04N9/76
    • G09G5/006G09G3/2096G09G5/02G09G5/12G09G2340/04G09G2340/0428G09G2340/10G09G2360/02
    • Embodiments of the invention are generally directed to conversion and processing of deep color video in a single clock domain. An embodiment of a method includes receiving one or more video data streams, the one or more video data streams including a first video data stream, the first video data stream being clocked at a frequency of a link clock signal. The method further includes converting the first video data stream into a converted video data stream having a modified data format, wherein the modified data format includes transfer of a single pixel of data in one cycle of the link clock signal and the insertion of null data to fill empty cycles of the converted video data stream, and generation of a valid data signal to distinguish between valid video data and the null data in the converted video data stream. The method further includes processing the converted video data stream according to the frequency of the link clock signal to generate a processed data stream from the converted video data stream, wherein processing includes using the valid data signal to identify valid video data.
    • 本发明的实施例一般涉及在单个时钟域中的深色视频的转换和处理。 一种方法的实施例包括接收一个或多个视频数据流,所述一个或多个视频数据流包括第一视频数据流,所述第一视频数据流以链路时钟信号的频率被计时。 该方法还包括将第一视频数据流转换成具有修改的数据格式的转换的视频数据流,其中修改的数据格式包括在链路时钟信号的一个周期中传输单个像素的数据,并将空数据插入到 填充经转换的视频数据流的空循环,以及生成有效数据信号以区分转换后的视频数据流中的有效视频数据和空数据。 该方法还包括根据链路时钟信号的频率处理转换后的视频数据流,以从经转换的视频数据流生成经处理的数据流,其中处理包括使用有效数据信号来识别有效视频数据。
    • 30. 发明授权
    • Apparatus and method for intermodular communications using system bus
controllers
    • 使用系统总线控制器进行模块间通信的装置和方法
    • US5856921A
    • 1999-01-05
    • US482396
    • 1995-06-07
    • Young Il KimKi B. KangYoung C. CheonJong Ky Lee
    • Young Il KimKi B. KangYoung C. CheonJong Ky Lee
    • G06F13/38G06F13/36G06F15/17H04L12/403G05B15/00
    • H04L12/403G06F15/17
    • A system bus architecture for intermodular communications is disclosed. The system bus architecture comprises a backplane bus with associated memory and a plurality of control registers. A master system processor module is coupled to the backplane bus via a master bus controller. The master system processor module contains a central processing unit in selective communication the master bus controller. A plurality of slave modules are also coupled to the backplane bus via respective slave bus controllers. Each of the slave modules has a slave central processing unit in selective communication the slave bus controller. The master and slave bus controllers are in selective communication with the bus memory, the plurality of control registers, and the respective central processing units, to transmit and receive data through the backplane bus.
    • 公开了一种用于模块间通信的系统总线架构。 系统总线架构包括具有相关存储器的背板总线和多个控制寄存器。 主系统处理器模块通过主总线控制器耦合到背板总线。 主系统处理器模块包含一个选择性通信主总线控制器的中央处理单元。 多个从模块还经由相应的从属总线控制器耦合到背板总线。 每个从模块具有从属中央处理单元,用于选择性地通信从总线控制器。 主从总线控制器与总线存储器,多个控制寄存器和各个中央处理单元选择性地通信,以通过背板总线发送和接收数据。