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21. 发明申请

US20130028142A1 RESILIENCY-AWARE HYBRID DESIGN OF CONTROLLER-SWITCH CONNECTIVITY IN A SPLIT-ARCHITECTURE SYSTEM 有权
标题翻译：分体式结构系统中控制器 - 开关连接的可靠性混合设计
公开(公告)号：US20130028142A1
公开(公告)日：2013-01-31
申请号：US13347592
申请日：2012-01-10
申请人： Neda Beheshti-Zavareh , Ying Zhang
发明人： Neda Beheshti-Zavareh , Ying Zhang
IPC分类号： H04L12/28
CPC分类号： H04L45/48 , H04L45/12 , H04L45/22 , H04L45/24 , H04L45/28
摘要： A method and apparatus for optimizing the resilience of a network using a combination of in-band and out-of-band signaling is disclosed. The metric used in the embodiment's algorithm to determine resilience is the maximum number of protected neighbors. Nodes closer to the controller are assigned a higher weight than those further from the controller because if their connection to the network is interrupted, all their downstream nodes will be affected and disconnected. Therefore, when determining a path to the controller, switches with alternate paths to the controller are preferred. Dedicated connections using out-of-band signaling are assigned to convert unprotected nodes to protected nodes thus improving the resilience of the network.
摘要翻译：公开了一种使用带内和带外信令的组合优化网络的弹性的方法和装置。用于确定弹性的实施例算法中使用的度量是受保护邻居的最大数量。更靠近控制器的节点的分配权重比控制器更多，因为如果它们与网络的连接中断，则所有下游节点都将受到影响和断开。因此，当确定到控制器的路径时，具有到控制器的备用路径的交换机是优选的。分配使用带外信令的专用连接将未受保护的节点转换为受保护节点，从而提高网络的弹性。

22. 发明申请

US20130012009A1 METHOD FOR SELF ALIGNED METAL GATE CMOS 审中-公开
标题翻译：自对准金属栅CMOS的方法
公开(公告)号：US20130012009A1
公开(公告)日：2013-01-10
申请号：US13617528
申请日：2012-09-14
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L21/283
CPC分类号： H01L21/823842 , H01L29/66545 , H01L29/7833 , H01L29/7843 , H01L2924/13085 , H01L2924/13092
摘要： A semiconductor device is formed by first providing a dual gate semiconductor device structure having FET pair precursors, which includes an nFET precursor and a pFET precursor, wherein each of the nFET precursor and the pFET precursor includes a dummy gate structure. At least one protective layer is deposited across the FET pair precursors, leaving the dummy gate structures exposed. The dummy gate structure is removed from one of the nFET precursor and the pFET precursor to create therein one of an nFET gate hole and a pFET gate hole, respectively. A fill is deposited into the formed one of the nFET gate hole and the pFET gate.
摘要翻译：半导体器件通过首先提供具有FET对前体的双栅极半导体器件结构形成，其包括nFET前体和pFET前体，其中nFET前体和pFET前体中的每一个包括伪栅极结构。至少一个保护层沉积在FET对前体之间，留下伪栅极结构。从nFET前体和pFET前体之一去除伪栅极结构，以在其中分别形成nFET栅极孔和pFET栅极孔中的一个。填充物沉积在形成的nFET栅极孔和pFET栅极之一中。

23. 发明申请

US20130001702A1 ENHANCING MOSFET PERFORMANCE BY OPTIMIZING STRESS PROPERTIES 审中-公开
标题翻译：通过优化应力特性提高MOSFET的性能
公开(公告)号：US20130001702A1
公开(公告)日：2013-01-03
申请号：US13613081
申请日：2012-09-13
申请人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ying Zhang
IPC分类号： H01L27/092
CPC分类号： H01L29/7843 , H01L21/26586 , H01L21/31155 , H01L21/823807 , H01L21/823864 , H01L29/6659 , H01L29/7833
摘要： A device and method for improving performance of a transistor includes gate structures formed on a substrate having a spacing therebetween. The gate structures are formed in an operative relationship with active areas formed in the substrate. A stress liner is formed on the gate structures. An angled ion implantation is applied to the stress liner such that ions are directed at vertical surfaces of the stress liner wherein portions of the stress liner in contact with the active areas are shielded from the ions due to a shadowing effect provided by a height and spacing between adjacent structures.
摘要翻译：用于提高晶体管性能的器件和方法包括形成在其间具有间隔的衬底上的栅极结构。栅极结构形成在与衬底中形成的有源区域的操作关系中。在栅极结构上形成应力衬垫。角度离子注入施加到应力衬垫上，使得离子被引导到应力衬垫的垂直表面，其中应力衬垫与有源区域接触的部分由于由高度和间隔提供的阴影效应而被屏蔽离子相邻结构之间。

24. 发明申请

US20120277124A1 High Performance Drilling Fluids with Submicron-Size Particles as the Weighting Agent 审中-公开
标题翻译：具有亚微米粒子作为加重剂的高性能钻井液
公开(公告)号：US20120277124A1
公开(公告)日：2012-11-01
申请号：US13545123
申请日：2012-07-10
申请人： Ying Zhang
发明人： Ying Zhang
IPC分类号： C09K8/04 , C09K8/32
CPC分类号： C09K8/36 , C09K8/032 , C09K2208/10 , C09K2208/18
摘要： Methods and compositions utilizing a drilling fluid comprising sub-micron precipitated barite having a weight average particle diameter below about 1 micron. Methods include a method comprising circulating a drilling fluid in a well bore, wherein the drilling fluid comprises: a carrier fluid; and a weighting agent that comprises sub-micron precipitated barite having a weight average particle diameter below about 1 micron are disclosed. In some embodiments, the drilling fluid may comprise an invert emulsion. In some embodiments, the sub-micron precipitated barite has a particle size distribution such that at least 10% of particles in the sub-micron precipitated barite have a diameter below about 0.2 micron, at least 50% of the particles in the of the sub-micron precipitated barite have a diameter below about 0.3 micron and at least 90% of the particles in the sub-micron precipitated barite have a diameter below about 0.5 micron.
摘要翻译：利用包含重均粒径低于约1微米的亚微米沉淀重晶石的钻井液的方法和组合物。方法包括一种方法，包括使钻井液在井眼中循环，其中钻井流体包括：载体流体; 并且公开了包含重均粒径低于约1微米的亚微米沉淀重晶石的加重剂。在一些实施例中，钻井液可以包括反相乳液。在一些实施方案中，亚微米沉淀重晶石具有粒度分布，使得亚微米沉淀重晶石中的至少10％的颗粒具有低于约0.2微米的直径，子层中的至少50％的颗粒 - 微量沉淀重晶石的直径低于约0.3微米，并且亚微米沉淀重晶石中的至少90％的颗粒具有低于约0.5微米的直径。

25. 发明授权

US08298881B2 Nanowire FET with trapezoid gate structure 有权
标题翻译：具有梯形栅极结构的纳米线FET
公开(公告)号：US08298881B2
公开(公告)日：2012-10-30
申请号：US12824293
申请日：2010-06-28
申请人： Jeffrey W. Sleight , Sarunya Bangsaruntip , Sebastian U. Engelmann , Ying Zhang
发明人： Jeffrey W. Sleight , Sarunya Bangsaruntip , Sebastian U. Engelmann , Ying Zhang
IPC分类号： H01L21/00 , H01L21/84
CPC分类号： H01L29/775 , B82Y10/00 , H01L29/4232 , H01L29/513 , H01L29/66439
摘要： In one embodiment, a method of providing a nanowire semiconductor device is provided, in which the gate structure to the nanowire semiconductor device has a trapezoid shape. The method may include forming a trapezoid gate structure surrounding at least a portion of a circumference of a nanowire. The first portion of the trapezoid gate structure that is in direct contact with an upper surface of the nanowire has a first width and a second portion of the trapezoid gate structure that is in direct contact with a lower surface of the nanowire has a second width. The second width of the trapezoid gate structure is greater than the first width of the trapezoid gate structure. The exposed portions of the nanowire that are adjacent to the portion of the nanowire that the trapezoid gate structure is surrounding are then doped to provide source and drain regions.
摘要翻译：在一个实施例中，提供了一种提供纳米线半导体器件的方法，其中对纳米线半导体器件的栅极结构具有梯形形状。该方法可以包括形成围绕纳米线的圆周的至少一部分的梯形栅极结构。与纳米线的上表面直接接触的梯形栅极结构的第一部分具有与纳米线的下表面直接接触的梯形栅极结构的第一宽度和第二部分具有第二宽度。梯形栅极结构的第二宽度大于梯形栅极结构的第一宽度。然后，与梯形栅极结构所围绕的部分纳米线相邻的纳米线的暴露部分被掺杂以提供源区和漏区。

26. 发明授权

US08268729B2 Smooth and vertical semiconductor fin structure 有权
标题翻译：平滑和垂直的半导体鳍结构
公开(公告)号：US08268729B2
公开(公告)日：2012-09-18
申请号：US12195691
申请日：2008-08-21
申请人： Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Johnathan E. Faltermeier , Ying Zhang
IPC分类号： H01L21/302 , H01L21/324
CPC分类号： H01L21/30608 , H01L29/045 , H01L29/66795
摘要： A method for processing a semiconductor fin structure is disclosed. The method includes thermal annealing a fin structure in an ambient containing an isotope of hydrogen. Following the thermal annealing step, the fin structure is etched in a crystal-orientation dependent, self-limiting, manner. The crystal-orientation dependent etch may be selected to be an aqueous solution containing ammonium hydroxide (NH4OH). The completed fin structure has smooth sidewalls and a uniform thickness profile. The fin structure sidewalls are {110} planes.
摘要翻译：公开了一种半导体鳍片结构的处理方法。该方法包括在含有氢同位素的环境中对翅片结构进行热退火。在热退火步骤之后，鳍结构被蚀刻成晶体取向的自限制的方式。取决于晶体取向的蚀刻可以选择为含有氢氧化铵（NH 4 OH）的水溶液。完成的翅片结构具有平滑的侧壁和均匀的厚度轮廓。翅片结构侧壁是{110}平面。

27. 发明申请

US20120195491A1 System And Method For Real-Time Mapping Of An Indoor Environment Using Mobile Robots With Limited Sensing 审中-公开
标题翻译：使用有限感知的移动机器人实时映射室内环境的系统和方法
公开(公告)号：US20120195491A1
公开(公告)日：2012-08-02
申请号：US12841065
申请日：2010-07-21
申请人： Ying Zhang , Juan Liu , Gabriel Hoffmann
发明人： Ying Zhang , Juan Liu , Gabriel Hoffmann
IPC分类号： G06K9/00
CPC分类号： G05D1/0274 , G05D1/0227 , G05D1/0272
摘要： A system and method for real-time mapping of an indoor environment using mobile robots with limited sensing are provided. Raw trajectory data comprising a plurality of trajectory points is received from wall-following. Trace segmentation is applied to the raw trajectory data to generate line segments. The line segments are rectified to one another. A map is generated from the rectified line segments.
摘要翻译：提供了一种使用有限感测的移动机器人实时映射室内环境的系统和方法。从墙跟踪接收包括多个轨迹点的原始轨迹数据。跟踪分割应用于原始轨迹数据以生成线段。线段彼此纠正。从整改的线段生成地图。

28. 发明申请

US20120193715A1 STRUCTURE WITH ISOTROPIC SILICON RECESS PROFILE IN NANOSCALE DIMENSIONS 审中-公开
标题翻译：结构与纳米尺度尺寸上的等温硅吸收型材
公开(公告)号：US20120193715A1
公开(公告)日：2012-08-02
申请号：US13442008
申请日：2012-04-09
申请人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
发明人： Sebastian Ulrich Engelmann , Nicholas C.M. Fuller , Eric Andrew Joseph , Isaac Lauer , Ryan M. Martin , James Vichiconti , Ying Zhang
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/0237 , H01L21/02639 , H01L21/3065 , H01L21/3083 , H01L29/165 , H01L29/66636 , H01L29/78 , Y10S438/938
摘要： A trench is formed by an anisotropic etch in a semiconductor material layer employing a masking layer, which can be gate spacers. In one embodiment, an adsorbed fluorine layer is provided at a cryogenic temperature only on vertical sidewalls of the semiconductor structure including the sidewalls of the trench. The adsorbed fluorine layer removes a controlled amount of the underlying semiconductor material once the temperature is raised above the cryogenic temperature. The trench can be filled with another semiconductor material to generate stress in the semiconductor material layer. In another embodiment, the semiconductor material is laterally etched by a plasma-based etch at a controlled rate while a horizontal portion of a contiguous oxide liner prevents etch of the semiconductor material from the bottom surface of the trench.
摘要翻译：通过使用可以是栅极间隔物的掩模层的半导体材料层中的各向异性蚀刻形成沟槽。在一个实施例中，仅在包括沟槽的侧壁的半导体结构的垂直侧壁处在低温温度下提供吸附的氟层。一旦温度升高到低于低温的温度，吸附的氟层就可去除受控量的底层半导体材料。沟槽可以用另一种半导体材料填充以在半导体材料层中产生应力。在另一个实施例中，通过基于等离子体的蚀刻以受控的速率横向蚀刻半导体材料，而邻接的氧化物衬垫的水平部分防止半导体材料从沟槽的底表面蚀刻。

29. 发明授权

US08206766B2 Method for using bamboo leaf extract as acrylamide inhibitor for heat processing food 有权
标题翻译：竹叶提取物作为热处理食品的丙烯酰胺抑制剂的方法
公开(公告)号：US08206766B2
公开(公告)日：2012-06-26
申请号：US11909265
申请日：2006-03-20
申请人： Ying Zhang , Xiaoqin Wu , Yu Zhang , Genyi Zhang , Dingding Luo , Yi Dong
发明人： Ying Zhang , Xiaoqin Wu , Yu Zhang , Genyi Zhang , Dingding Luo , Yi Dong
IPC分类号： A23L3/34
CPC分类号： A23L3/3472 , A23B4/10 , A23B4/18 , A23B7/154 , A23B7/16 , A23F5/14 , A23L3/3463 , A23L5/27 , A23L7/10 , A23L11/34 , A23L19/18 , A23L33/105 , A24B15/302
摘要： A method for using a bamboo leaf extract as an acrylamide inhibitor for heat processing food, includes adding to the bamboo leaf extract at least one selected from a group consisting of ginkgo extract, tea extract, rosemary extract, apple polyphenol extract, haw extract, onion extract, licorice extract, root of kudzuvine extract, grape seed extract and leech extract; and preparing a composition, in which the bamboo leaf extract takes up 34-95% of the total weight of the composition. The bamboo leaf extract used as the acrylamide inhibitor in food systems has an inhibiting rate to acrylamide formation of up to 15-98%.
摘要翻译：使用竹叶提取物作为加热食品的丙烯酰胺抑制剂的方法包括向竹叶提取物中加入至少一种选自银杏提取物，茶提取物，迷迭香提取物，苹果多酚提取物，葫芦提取物，洋葱提取物，甘草提取物，葛根提取物，葡萄籽提取物和水蛭提取物; 并制备竹叶提取物占组合物总重量的34-95％的组合物。用作食品体系中丙烯酰胺抑制剂的竹叶提取物对丙烯酰胺的形成抑制率高达15-98％。

30. 发明授权

US08202780B2 Method for manufacturing a FinFET device comprising a mask to define a gate perimeter and another mask to define fin regions 有权
标题翻译：用于制造FinFET器件的方法，其包括用于限定栅极周界的掩模和用于限定鳍片区域的另一个掩模
公开(公告)号：US08202780B2
公开(公告)日：2012-06-19
申请号：US12533389
申请日：2009-07-31
申请人： Zhibin Ren , Xinhui Wang , Kevin K. Chan , Ying Zhang
发明人： Zhibin Ren , Xinhui Wang , Kevin K. Chan , Ying Zhang
IPC分类号： H01L21/336
CPC分类号： H01L29/66795 , H01L29/785
摘要： A method for manufacturing a FinFET device includes: providing a substrate having a mask disposed thereon; covering portions of the mask to define a perimeter of a gate region; removing uncovered portions of the mask to expose the substrate; covering a part of the exposed substrate with another mask to define at least one fin region; forming the at least one fin and the gate region through both masks and the substrate, the gate region having side walls; disposing insulating layers around the at least one fin and onto the side walls; disposing a conductive material into the gate region and onto the insulating layers to form a gate electrode, and then forming source and drain regions.
摘要翻译：一种制造FinFET器件的方法包括：提供其上设置有掩模的衬底; 覆盖掩模的部分以限定栅极区域的周边; 去除所述掩模的未覆盖部分以暴露所述基底; 用另一掩模覆盖暴露的基底的一部分以限定至少一个鳍片区域; 通过所述掩模和所述基板形成所述至少一个翅片和所述栅极区域，所述栅极区域具有侧壁; 将所述至少一个翅片周围的绝缘层设置在所述侧壁上; 将导电材料设置在栅极区域和绝缘层上以形成栅电极，然后形成源极和漏极区域。

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