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21. 发明授权

US08642477B2 Method for clearing native oxide 有权
标题翻译：清除天然氧化物的方法
公开(公告)号：US08642477B2
公开(公告)日：2014-02-04
申请号：US12129978
申请日：2008-05-30
申请人： Yen-Chu Chen , Teng-Chun Tsai , Chien-Chung Huang , Keng-Jen Liu
发明人： Yen-Chu Chen , Teng-Chun Tsai , Chien-Chung Huang , Keng-Jen Liu
IPC分类号： H01L21/302 , C23F1/00
CPC分类号： H01L21/3065 , H01L21/02057 , H01L21/02063
摘要： A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.
摘要翻译：描述了清除天然氧化物的方法。提供了一种衬底，包括其中形成有自然氧化物层的暴露部分。使用三氟化氮（NF 3）和氨（NH 3）作为反应气体对基板进行清除处理，其中NF 3的体积流量大于NH 3的体积流量。

22. 发明申请

US20120146225A1 DAMASCENE STRUCTURE 有权
标题翻译：大田结构
公开(公告)号：US20120146225A1
公开(公告)日：2012-06-14
申请号：US13397833
申请日：2012-02-16
申请人： Yu-Ru YANG , Chien-Chung Huang
发明人： Yu-Ru YANG , Chien-Chung Huang
IPC分类号： H01L23/532
CPC分类号： H01L21/2855 , H01L21/76844 , H01L21/76846
摘要： A damascene structure includes a conductive layer, a first dielectric layer, a first barrier metal layer, a barrier layer, and a second barrier metal layer sequentially formed on the conductive layer. The first dielectric layer having a via therein. The barrier layer is comprised of a material different with that of the first barrier metal layer. A bottom of the barrier layer disposed on the via bottom is not punched through. The accomplished barrier layers will have lower resistivity on the via bottom in the first dielectric layer and they are capable of preventing copper atoms from diffusing into the dielectric layer.
摘要翻译：镶嵌结构包括依次形成在导电层上的导电层，第一介电层，第一阻挡金属层，阻挡层和第二阻挡金属层。第一电介质层中具有通孔。阻挡层由与第一阻挡金属层不同的材料构成。设置在通孔底部上的阻挡层的底部不穿孔。完成的阻挡层在第一介电层中的通孔底部具有较低的电阻率，并且它们能够防止铜原子扩散到电介质层中。

23. 发明授权

US08092861B2 Method of fabricating an ultra dielectric constant (K) dielectric layer 有权
标题翻译：制造超介电常数（K）介电层的方法
公开(公告)号：US08092861B2
公开(公告)日：2012-01-10
申请号：US11850466
申请日：2007-09-05
申请人： Mei-Ling Chen , Su-Jen Sung , Chien-Chung Huang
发明人： Mei-Ling Chen , Su-Jen Sung , Chien-Chung Huang
IPC分类号： C23C16/30
CPC分类号： C23C16/401 , C23C16/45557 , C23C16/46 , H01L21/02126 , H01L21/02203 , H01L21/02216 , H01L21/02274 , H01L21/02304 , H01L21/02362 , H01L21/31695 , Y10T428/249953
摘要： A fabrication method of an ultra low-k dielectric layer is provided. A deposition process is performed, under the control of a temperature varying program or a pressure varying program, by reacting a dielectric matrix to form porous low-k dielectric layers with a gradient density on a barrier layer over a substrate.
摘要翻译：提供了一种超低k电介质层的制造方法。在温度变化程序或压力变化程序的控制下，通过使介电基质反应以在衬底上的阻挡层上形成具有梯度密度的多孔低k电介质层来进行沉积工艺。

24. 发明申请

US20100261323A1 METHOD OF FORMING METAL-OXIDE-SEMICONDUCTOR TRANSISTOR 有权
标题翻译：形成金属氧化物半导体晶体管的方法
公开(公告)号：US20100261323A1
公开(公告)日：2010-10-14
申请号：US12819229
申请日：2010-06-21
申请人： Neng-Kuo Chen , Chien-Chung Huang
发明人： Neng-Kuo Chen , Chien-Chung Huang
IPC分类号： H01L21/8238 , H01L21/316
CPC分类号： H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has agate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention.
摘要翻译：公开了一种形成金属氧化物半导体（MOS）晶体管器件的方法。首先制备半导体衬底，并且半导体衬底具有玛瑙结构，源极区和漏极区。接着，在半导体基板上形成应力缓冲层，覆盖栅极结构，源极区域和漏极区域。此后，在应力缓冲层上形成应力覆盖层，并且应力覆盖层的拉伸应力值高于应力缓冲层的拉伸应力值。由于应力缓冲层可以防止应力覆盖层破裂，所以在本发明中，MOS晶体管器件可以被具有非常高的拉伸应力值的应力覆盖层覆盖。

25. 发明授权

US07777284B2 Metal-oxide-semiconductor transistor and method of forming the same 有权
标题翻译：金属氧化物半导体晶体管及其形成方法
公开(公告)号：US07777284B2
公开(公告)日：2010-08-17
申请号：US11754362
申请日：2007-05-28
申请人： Neng-Kuo Chen , Chien-Chung Huang
发明人： Neng-Kuo Chen , Chien-Chung Huang
IPC分类号： H01L29/82 , H01L21/00
CPC分类号： H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has a gate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention.
摘要翻译：公开了一种形成金属氧化物半导体（MOS）晶体管器件的方法。首先制备半导体衬底，并且半导体衬底具有栅极结构，源极区和漏极区。接着，在半导体基板上形成应力缓冲层，覆盖栅极结构，源极区域和漏极区域。此后，在应力缓冲层上形成应力覆盖层，并且应力覆盖层的拉伸应力值高于应力缓冲层的拉伸应力值。由于应力缓冲层可以防止应力覆盖层破裂，所以在本发明中，MOS晶体管器件可以被具有非常高的拉伸应力值的应力覆盖层覆盖。

26. 发明授权

US07662730B2 Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof 有权
标题翻译：制造超高拉伸应力膜及其应变硅晶体管的方法
公开(公告)号：US07662730B2
公开(公告)日：2010-02-16
申请号：US11164488
申请日：2005-11-24
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang , Tsai-Fu Chen , Wen-Han Hung
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang , Tsai-Fu Chen , Wen-Han Hung
IPC分类号： H01L21/471
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/56 , H01L21/02274 , H01L21/02348 , H01L21/3185 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method for fabricating an ultra-high tensile-stressed nitride film is disclosed. A PECVD process is first performed to deposit a transitional silicon nitride film over a substrate. The transitional silicon nitride film has a first concentration of hydrogen atoms. The transitional silicon nitride film is subjected to UV curing process for reducing the first concentration of hydrogen atoms to a second concentration of hydrogen atoms.
摘要翻译：公开了一种用于制造超高拉伸应力氮化物膜的方法。首先执行PECVD处理以在衬底上沉积过渡氮化硅膜。过渡氮化硅膜具有第一浓度的氢原子。将过渡氮化硅膜进行UV固化，将氢原子的第一浓度降低至第二浓度的氢原子。

27. 发明授权

US07655987B2 Method for fabricating ultra-high tensile-stressed film and strained-silicon transistors thereof 有权
标题翻译：制造超高拉伸应力膜及其应变硅晶体管的方法
公开(公告)号：US07655987B2
公开(公告)日：2010-02-02
申请号：US12013482
申请日：2008-01-14
申请人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang , Tsai-Fu Chen , Wen-Han Hung
发明人： Neng-Kuo Chen , Teng-Chun Tsai , Chien-Chung Huang , Tsai-Fu Chen , Wen-Han Hung
IPC分类号： H01L29/772
CPC分类号： H01L21/0217 , C23C16/345 , C23C16/56 , H01L21/02274 , H01L21/02348 , H01L21/3185 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A metal-oxide-semiconductor (MOS) transistor device is disclosed. The MOS transistor device comprises a semiconductor substrate; a gate structure on the semiconductor substrate; source/drain regions on the semiconductor substrate adjacent to the gate structure; an ultra-high tensile-stressed nitride film having a hydrogen concentration of less than 1E22 atoms/cm3 covering the gate structure and the source/drain regions; and an inter-layer dielectric (ILD) film over the ultra-high tensile-stressed nitride film.
摘要翻译：公开了金属氧化物半导体（MOS）晶体管器件。 MOS晶体管器件包括半导体衬底; 半导体衬底上的栅极结构; 与栅极结构相邻的半导体衬底上的源/漏区; 覆盖栅极结构和源极/漏极区域的具有小于1E22原子/ cm3的氢浓度的超高拉伸应力氮化物膜; 和超高拉伸应力氮化物膜上的层间电介质（ILD）膜。

28. 发明申请

US20090257184A1 DRAM MODULE WITH SOLID STATE DISK 有权
标题翻译：具有固态盘的DRAM模块
公开(公告)号：US20090257184A1
公开(公告)日：2009-10-15
申请号：US12100023
申请日：2008-04-09
申请人： Jiunn-Chung LEE , Chien-Chung Huang
发明人： Jiunn-Chung LEE , Chien-Chung Huang
IPC分类号： H05K7/00 , H05K1/11 , H05K1/14
CPC分类号： H05K1/181 , G11C5/00 , H05K2201/09254 , H05K2201/10159 , H05K2201/10189 , Y02P70/611
摘要： A dynamic radon access memory (DRAM) module includes a printed circuit board, a number of DRAM units, a number of flash memory units, a number connecting pins and an interface controller. The DRAM units and the flash memory units are distributed on the printed circuit board. The connecting pins are formed at an edge of the printed circuit board. The interface controller is electrically connected to the flash memory units and a portion of the connecting pins, wherein each of the interface controller provides at least one serial interface between the flash memory units and the portion of connecting pins thereby enabling data transmission through the portion of connecting pins in at least one serial mode. The flash memory units integrally constitute a flash disk drive in the DRAM module. Therefore, frequently installation and uninstallation of the flash memory drive can be avoided. A motherboard assembly including the aforementioned DRAM module can be developed.
摘要翻译：动态氡存取存储器（DRAM）模块包括印刷电路板，多个DRAM单元，多个闪存单元，数字连接引脚和接口控制器。 DRAM单元和闪存单元分布在印刷电路板上。连接销形成在印刷电路板的边缘。接口控制器电连接到闪存单元和连接引脚的一部分，其中每个接口控制器在闪存单元和连接引脚的部分之间提供至少一个串行接口，从而使数据可以通过在至少一个串行模式下连接引脚。闪存单元一体地构成DRAM模块中的闪存盘驱动器。因此，可以避免闪存驱动器的频繁安装和卸载。可以开发包括上述DRAM模块的主板组件。

29. 发明申请

US20080296631A1 METAL-OXIDE-SEMICONDUCTOR TRANSISTOR AND METHOD OF FORMING THE SAME 有权
标题翻译：金属氧化物半导体晶体管及其形成方法
公开(公告)号：US20080296631A1
公开(公告)日：2008-12-04
申请号：US11754362
申请日：2007-05-28
申请人： Neng-Kuo Chen , Chien-Chung Huang
发明人： Neng-Kuo Chen , Chien-Chung Huang
IPC分类号： H01L21/336 , H01L29/84
CPC分类号： H01L21/823807 , H01L29/665 , H01L29/7843
摘要： A method of forming a metal-oxide-semiconductor (MOS) transistor device is disclosed. A semiconductor substrate is prepared first, and the semiconductor substrate has a gate structure, a source region and a drain region. Subsequently, a stress buffer layer is formed on the semiconductor substrate, and covers the gate structure, the source region and the drain region. Thereafter, a stressed cap layer is formed on the stress buffer layer, and a tensile stress value of the stressed cap layer is higher than a tensile stress value of the stress buffer layer. Since the stress buffer layer can prevent the stressed cap layer from breaking, the MOS transistor device can be covered by a stressed cap layer having an extremely high tensile stress value in the present invention.
摘要翻译：公开了一种形成金属氧化物半导体（MOS）晶体管器件的方法。首先制备半导体衬底，并且半导体衬底具有栅极结构，源极区和漏极区。接着，在半导体基板上形成应力缓冲层，覆盖栅极结构，源极区域和漏极区域。此后，在应力缓冲层上形成应力覆盖层，并且应力覆盖层的拉伸应力值高于应力缓冲层的拉伸应力值。由于应力缓冲层可以防止应力覆盖层破裂，所以在本发明中，MOS晶体管器件可以被具有非常高的拉伸应力值的应力覆盖层覆盖。

30. 发明申请

US20080225525A1 LIGHT SOURCE MODULE 审中-公开
标题翻译：光源模块
公开(公告)号：US20080225525A1
公开(公告)日：2008-09-18
申请号：US11838897
申请日：2007-08-15
申请人： Shen-Huei Wang , Chien-Chiu Hsueh , Nien-Hui Hsu , Chien-Chung Huang
发明人： Shen-Huei Wang , Chien-Chiu Hsueh , Nien-Hui Hsu , Chien-Chung Huang
IPC分类号： F21V29/02
CPC分类号： G03B21/16 , G03B21/2026
摘要： A light source module for a projection apparatus including a light source unit, a fan, a temperature sensor and a temperature controller is provided. The fan is disposed towards the light source unit and is capable of cooling the light source unit. The temperature sensor is disposed adjacent to the light source unit and is capable of sensing an operating temperature of the light source unit. The temperature controller is electrically coupled to the fan and the temperature sensor, and is capable of adjusting a rotation speed of the fan according to the operating temperature of the light source unit. The invention is capable of keeping the operating temperature of the light source unit at or close to the predetermined operating temperature thereof by adjusting the rotation speed of the fan.
摘要翻译：提供一种用于包括光源单元，风扇，温度传感器和温度控制器的投影设备的光源模块。风扇朝向光源单元设置，并且能够冷却光源单元。温度传感器设置在光源单元附近并且能够感测光源单元的工作温度。温度控制器电耦合到风扇和温度传感器，并且能够根据光源单元的工作温度来调节风扇的转速。本发明能够通过调节风扇的转速来将光源单元的工作温度保持在或接近其预定工作温度。

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