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21. 发明申请

US20130200451A1 NANO MOSFET WITH TRENCH BOTTOM OXIDE SHIELDED AND THIRD DIMENSIONAL P-BODY CONTACT 有权
标题翻译： NANO MOSFET，带有TRENCH BOTTOM OXIDE SILIELDED和第三维P-BODY接触
公开(公告)号：US20130200451A1
公开(公告)日：2013-08-08
申请号：US13364948
申请日：2012-02-02
申请人： Hamza Yilmaz , Daniel Ng , Daniel Calafut , Madhur Bobde , Anup Bhalla , Ji Pan , Yeeheng Lee , Jongoh Kim
发明人： Hamza Yilmaz , Daniel Ng , Daniel Calafut , Madhur Bobde , Anup Bhalla , Ji Pan , Yeeheng Lee , Jongoh Kim
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L27/088 , H01L29/0623 , H01L29/0626 , H01L29/086 , H01L29/0865 , H01L29/0869 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A semiconductor power device may include a lightly doped layer formed on a heavily doped layer. One or more devices are formed in the lightly doped layer. Each device may include a body region, a source region, and one or more gate electrodes formed in corresponding trenches in the lightly doped region. Each of the trenches has a depth in a first dimension, a width in a second dimension and a length in a third dimension. The body region is of opposite conductivity type to the lightly and heavily doped layers. The source region is formed proximate the upper surface. One or more deep contacts are formed at one or more locations along the third dimension proximate one or more of the trenches. The contacts extend in the first direction from the upper surface into the lightly doped layer and are in electrical contact with the source region.
摘要翻译：半导体功率器件可以包括在重掺杂层上形成的轻掺杂层。在轻掺杂层中形成一个或多个器件。每个器件可以包括主体区域，源极区域和形成在轻掺杂区域中的对应沟槽中的一个或多个栅电极。每个沟槽具有第一维度的深度，第二维度中的宽度和第三维度中的长度。体区与轻掺杂层和重掺杂层具有相反的导电类型。源区域靠近上表面形成。在靠近一个或多个沟槽的第三维度的一个或多个位置处形成一个或多个深触点。触点在第一方向上从上表面延伸到轻掺杂层中并与源区电接触。

22. 发明申请

US20160372542A9 TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS 审中-公开
公开(公告)号：US20160372542A9
公开(公告)日：2016-12-22
申请号：US14329936
申请日：2014-07-12
申请人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
发明人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
IPC分类号： H01L29/06 , H01L21/761 , H01L29/78
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/0619 , H01L29/404 , H01L29/407 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/7823
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.

23. 发明申请

US20160013267A1 TERMINATION OF HIGH VOLTAGE (HV) DEVICES WITH NEW CONFIGURATIONS AND METHODS 审中-公开
标题翻译：具有新配置和方法的高压（HV）器件的终止
公开(公告)号：US20160013267A1
公开(公告)日：2016-01-14
申请号：US14329936
申请日：2014-07-12
申请人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
发明人： Yeeheng Lee , Madhur Bobde , Yongping Ding , Jongoh Kim , Anup Bhalla
IPC分类号： H01L29/06 , H01L21/761 , H01L29/78
CPC分类号： H01L29/0623 , H01L21/761 , H01L29/0619 , H01L29/404 , H01L29/407 , H01L29/66734 , H01L29/7811 , H01L29/7813 , H01L29/7823
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a heavily doped region formed on a lightly doped region and having an active cell area and an edge termination area. The edge termination area comprises a plurality of termination trenches formed in the heavily doped region with the termination trenches lined with a dielectric layer and filled with a conductive material therein. The edge termination further includes a plurality of buried guard rings formed as doped regions in the lightly doped region of the semiconductor substrate immediately adjacent to the termination trenches.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在轻掺杂区域上并具有有源电池区域和边缘端接区域的重掺杂区域。边缘终止区域包括形成在重掺杂区域中的多个端接沟槽，其中端接沟槽衬有介电层并在其中填充有导电材料。边缘终端还包括多个掩埋保护环，其形成为紧邻端接沟槽的半导体衬底的轻掺杂区域中的掺杂区域。

24. 发明授权

US08247297B2 Method of filling large deep trench with high quality oxide for semiconductor devices 有权
标题翻译：为半导体器件填充高质量氧化物的大型深沟槽的方法
公开(公告)号：US08247297B2
公开(公告)日：2012-08-21
申请号：US12637988
申请日：2009-12-15
申请人： Xiaobin Wang , Anup Bhalla , Yeeheng Lee
发明人： Xiaobin Wang , Anup Bhalla , Yeeheng Lee
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L29/0657 , H01L21/76202 , H01L21/76224 , H01L21/76227 , H01L29/407 , H01L29/872 , H01L2924/0002 , H01L2924/00
摘要： A method is disclosed for creating a semiconductor device structure with an oxide-filled large deep trench (OFLDT) portion having trench size TCS and trench depth TCD. A bulk semiconductor layer (BSL) is provided with a thickness BSLT>TCD. A large trench top area (LTTA) is mapped out atop BSL with its geometry equal to OFLDT. The LTTA is partitioned into interspersed, complementary interim areas ITA-A and ITA-B. Numerous interim vertical trenches of depth TCD are created into the top BSL surface by removing bulk semiconductor materials corresponding to ITA-B. The remaining bulk semiconductor materials corresponding to ITA-A are converted into oxide. If any residual space is still left between the so-converted ITA-A, the residual space is filled up with oxide deposition. Importantly, the geometry of all ITA-A and ITA-B should be configured simple and small enough to facilitate fast and efficient processes of oxide conversion and oxide filling.
摘要翻译：公开了一种用于产生具有沟槽尺寸TCS和沟槽深度TCD的具有氧化物填充的大深沟槽（OFLDT）部分的半导体器件结构的方法。体积半导体层（BSL）设置有厚度BSLT> TCD。一个大的沟槽顶部区域（LTTA）映射到BSL顶部，其几何形状等于OFLDT。 LTTA被划分为散置的，互补的临时区域ITA-A和ITA-B。通过去除对应于ITA-B的散装半导体材料，在顶部BSL表面上形成了许多深度TCD的临时垂直沟槽。对应于ITA-A的剩余体积半导体材料被转化为氧化物。如果在经过转换的ITA-A之间仍然留有剩余空间，则剩余空间被氧化物沉积填满。重要的是，所有ITA-A和ITA-B的几何形状都应该被简单而小型化，以便于快速有效地进行氧化物转换和氧化物填充。

25. 发明申请

US20140175536A1 HIGH DENSITY TRENCH-BASED POWER MOSFETS WITH SELF-ALIGNED ACTIVE CONTACTS AND METHOD FOR MAKING SUCH DEVICES 有权
标题翻译：具有自对准主动联系人的高密度TRENCH基功率MOSFET及其制造方法
公开(公告)号：US20140175536A1
公开(公告)日：2014-06-26
申请号：US13724228
申请日：2012-12-21
申请人： Yeeheng Lee , Hong Chang , Jongoh Kim , Sik Liu , Hamza Yilmaz , Madhur Bobde , Daniel Calafut , John Chen
发明人： Yeeheng Lee , Hong Chang , Jongoh Kim , Sik Liu , Hamza Yilmaz , Madhur Bobde , Daniel Calafut , John Chen
IPC分类号： H01L21/8234 , H01L21/28 , H01L29/78 , H01L29/423 , H01L21/033 , H01L29/66
CPC分类号： H01L29/7813 , H01L21/28114 , H01L21/3081 , H01L21/823456 , H01L21/823462 , H01L21/823468 , H01L23/66 , H01L27/0248 , H01L27/0251 , H01L27/0292 , H01L29/0619 , H01L29/1095 , H01L29/42364 , H01L29/42376 , H01L29/6653 , H01L29/66553 , H01L29/6656 , H01L29/66719 , H01L29/66734 , H01L29/7803 , H01L29/7811 , H01L2924/0002 , H01L2924/00
摘要： Aspects of the present disclosure describe a high density trench-based power MOSFET with self-aligned source contacts. The source contacts are self-aligned with a first insulative spacer and a second insulative spacer, wherein the first spacer is resistant to an etching process that will selectively remove the material the second spacer is made from. Additionally, the active devices may have a two-step gate oxide, wherein a lower portion of the gate oxide has a thickness T2 that is larger than the thickness T1 of an upper portion of the gate oxide. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：本公开的方面描述了具有自对准源触点的高密度基于沟槽的功率MOSFET。源触点与第一绝缘间隔件和第二绝缘间隔件自对准，其中第一间隔件耐蚀刻工艺，该蚀刻工艺将选择性地去除由第二间隔件制成的材料。此外，有源器件可以具有两级栅极氧化物，其中栅极氧化物的下部具有大于栅极氧化物的上部的厚度T1的厚度T2。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

26. 发明授权

US08252647B2 Fabrication of trench DMOS device having thick bottom shielding oxide 有权
标题翻译：具有厚底层屏蔽氧化物的沟槽DMOS器件的制造
公开(公告)号：US08252647B2
公开(公告)日：2012-08-28
申请号：US12551417
申请日：2009-08-31
申请人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
发明人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/66719 , H01L29/66734
摘要： Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.
摘要翻译：公开了半导体器件制造方法和器件。可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分，使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻，以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。或者，可以在沟槽的侧壁和底部形成氧化物 - 氧化物（ONO）结构，并且可以在未被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

27. 发明申请

US20110049618A1 FABRICATION OF TRENCH DMOS DEVICE HAVING THICK BOTTOM SHIELDING OXIDE 有权
标题翻译：具有厚度底层氧化物的TRENCH DMOS器件的制造
公开(公告)号：US20110049618A1
公开(公告)日：2011-03-03
申请号：US12551417
申请日：2009-08-31
申请人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
发明人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/66719 , H01L29/66734
摘要： Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.
摘要翻译：公开了半导体器件制造方法和器件。可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分，使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻，以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。或者，可以在沟槽的侧壁和底部形成氧化物 - 氧化物（ONO）结构，并且可以在未被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

28. 发明授权

US09000514B2 Fabrication of trench DMOS device having thick bottom shielding oxide 有权
标题翻译：具有厚底层屏蔽氧化物的沟槽DMOS器件的制造
公开(公告)号：US09000514B2
公开(公告)日：2015-04-07
申请号：US13560247
申请日：2012-07-27
申请人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
发明人： Yeeheng Lee , Sung-Shan Tai , Hong Chang , John Chen
IPC分类号： H01L29/78 , H01L29/40 , H01L29/423 , H01L29/66 , H01L29/51
CPC分类号： H01L29/7813 , H01L29/407 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/513 , H01L29/66719 , H01L29/66734
摘要： Semiconductor device fabrication method and devices are disclosed. A device may be fabricated by forming in a semiconductor layer; filling the trench with an insulating material; removing selected portions of the insulating material leaving a portion of the insulating material in a bottom portion of the trench; forming one or more spacers on one or more sidewalls of a remaining portion of the trench; anisotropically etching the insulating material in the bottom portion of the trench using the spacers as a mask to form a trench in the insulator; removing the spacers; and filling the trench in the insulator with a conductive material. Alternatively, an oxide-nitride-oxide (ONO) structure may be formed on a sidewall and at a bottom of the trench and one or more conductive structures may be formed in a portion of the trench not occupied by the ONO structure.
摘要翻译：公开了半导体器件制造方法和器件。可以通过在半导体层中形成来制造器件; 用绝缘材料填充沟槽; 去除所述绝缘材料的选定部分，使所述绝缘材料的一部分留在所述沟槽的底部; 在所述沟槽的剩余部分的一个或多个侧壁上形成一个或多个间隔物; 使用间隔物作为掩模对沟槽的底部中的绝缘材料进行各向异性蚀刻，以在绝缘体中形成沟槽; 去除垫片; 并用导电材料填充绝缘体中的沟槽。或者，氧化物 - 氧化物 - 氧化物（ONO）结构可以形成在沟槽的侧壁和底部，并且可以在不被ONO结构占据的沟槽的一部分中形成一个或多个导电结构。

29. 发明申请

US20140252460A1 High Density MOSFET Array with Self-Aligned Contacts Delimited by Nitride-Capped Trench Gate Stacks and Method 有权
标题翻译：高密度MOSFET阵列，具有由氮化物覆盖的沟槽栅极分隔的自对准触点和方法
公开(公告)号：US20140252460A1
公开(公告)日：2014-09-11
申请号：US13794628
申请日：2013-03-11
申请人： Yeeheng Lee , Jongoh Kim , Hong Chang
发明人： Yeeheng Lee , Jongoh Kim , Hong Chang
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L27/088 , H01L23/53266 , H01L23/535 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/4916 , H01L29/66666 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.
摘要翻译：公开了一种高密度沟槽门控MOSFET阵列和方法。它包括分为MOSFET阵列区域和栅极拾取区域的半导体衬底; 外延区域，体区域和源区域; 许多精确间隔的活性氮化物封闭沟槽栅堆叠（ANCTGS）嵌入到外延区域。每个ANCTGS包括堆叠的多晶硅沟槽栅极，栅极氧化物层和覆盖多晶硅沟槽栅极顶部的氮化硅盖，并横向配向栅极氧化物壳。 ANCTGS与MOSFET阵列区域中的源极，主体，外延区域，MOSFET器件一起形成。在MOSFET阵列区域和栅极拾取区域上，MOSFET阵列顶部的图案化电介质区域和图案化电介质区域顶部的图案化金属层。因此，图案化的金属层与MOSFET阵列和栅极拾取区域形成自对准的源极和主体通过ANCTGS间隔而接触。

30. 发明授权

US09136377B2 High density MOSFET array with self-aligned contacts delimited by nitride-capped trench gate stacks and method 有权
标题翻译：具有由氮化物封闭的沟槽栅极叠层限定的自对准触点的高密度MOSFET阵列和方法
公开(公告)号：US09136377B2
公开(公告)日：2015-09-15
申请号：US13794628
申请日：2013-03-11
申请人： Yeeheng Lee , Jongoh Kim , Hong Chang
发明人： Yeeheng Lee , Jongoh Kim , Hong Chang
IPC分类号： H01L29/78 , H01L29/66
CPC分类号： H01L27/088 , H01L23/53266 , H01L23/535 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/456 , H01L29/4916 , H01L29/66666 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7813 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A high density trench-gated MOSFET array and method are disclosed. It comprises semiconductor substrate partitioned into MOSFET array area and gate pickup area; epitaxial region, body region and source region; numerous precisely spaced active nitride-capped trench gate stacks (ANCTGS) embedded till the epitaxial region. Each ANCTGS comprises a stack of polysilicon trench gate with gate oxide shell and silicon nitride cap covering top of polysilicon trench gate and laterally registered to gate oxide shell. The ANCTGS forms, together with the source, body, epitaxial region, a MOSFET device in the MOSFET array area. Over MOSFET array area and gate pickup area, a patterned dielectric region atop the MOSFET array and a patterned metal layer atop the patterned dielectric region. Thus, the patterned metal layer forms, with the MOSFET array and the gate pickup area, self-aligned source and body contacts through the inter-ANCTGS separations.
摘要翻译：公开了一种高密度沟槽门控MOSFET阵列和方法。它包括分为MOSFET阵列区域和栅极拾取区域的半导体衬底; 外延区域，体区域和源区域; 许多精确间隔的活性氮化物封闭沟槽栅堆叠（ANCTGS）嵌入到外延区域。每个ANCTGS包括堆叠的多晶硅沟槽栅极，栅极氧化物层和覆盖多晶硅沟槽栅极顶部的氮化硅盖，并横向配向栅极氧化物壳。 ANCTGS与源极，体，外延区域，MOSFET阵列区域中的MOSFET器件一起形成。在MOSFET阵列区域和栅极拾取区域上，MOSFET阵列顶部的图案化电介质区域和图案化电介质区域顶部的图案化金属层。因此，图案化的金属层与MOSFET阵列和栅极拾取区域形成自对准的源极和主体通过ANCTGS间隔而接触。

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