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21. 发明申请

US20130075855A1 Manufacturing methods for accurately aligned and self-balanced superjunction devices 有权
标题翻译：精确对准和自平衡超级结装置的制造方法
公开(公告)号：US20130075855A1
公开(公告)日：2013-03-28
申请号：US13200683
申请日：2011-09-27
申请人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
发明人： Lingpeng Guan , Madhur Bobde , Anup Bhalla , Yeeheng Lee , John Chen , Moses Ho
IPC分类号： H01L29/06 , H01L21/22
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/1095 , H01L29/66712
摘要： A method for manufacturing a semiconductor power device on a semiconductor substrate supporting a drift region composed of an epitaxial layer by growing a first epitaxial layer followed by forming a first hard mask layer on top of the epitaxial layer; applying a first implant mask to open a plurality of implant windows and applying a second implant mask for blocking some of the implant windows to implant a plurality of dopant regions of alternating conductivity types adjacent to each other in the first epitaxial layer; repeating the first step and the second step by applying the same first and second implant masks to form a plurality of epitaxial layers then carrying out a device manufacturing process on a top side of the epitaxial layer with a diffusion process to merge the dopant regions of the alternating conductivity types as doped columns in the epitaxial layers.
摘要翻译：一种在半导体基板上制造半导体功率器件的方法，该半导体衬底通过生长第一外延层，然后在外延层的顶部上形成第一硬掩模层，从而支撑由外延层组成的漂移区; 施加第一注入掩模以打开多个植入窗口并且施加第二注入掩模以阻挡所述植入物窗口中的一些以在所述第一外延层中相互邻近地注入交替导电类型的多个掺杂区域; 通过施加相同的第一和第二注入掩模来重复第一步骤和第二步骤，以形成多个外延层，然后利用扩散处理在外延层的顶侧上进行器件制造工艺，以将掺杂区域交替导电类型作为外延层中的掺杂列。

22. 发明申请

US20160013265A1 SEMICONDUCTOR DEVICE WITH FIELD THRESHOLD MOSFET FOR HIGH VOLTAGE TERMINATION 审中-公开
标题翻译：具有用于高电压终止的场阈MOSFET的半导体器件
公开(公告)号：US20160013265A1
公开(公告)日：2016-01-14
申请号：US14329938
申请日：2014-07-12
申请人： Hamza Yilmaz , Madhur Bobde
发明人： Hamza Yilmaz , Madhur Bobde
IPC分类号： H01L29/06 , H01L29/739 , H01L29/78
CPC分类号： H01L29/0623 , H01L27/0823 , H01L27/088 , H01L29/0619 , H01L29/0638 , H01L29/404 , H01L29/407 , H01L29/7393 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/7823
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在重掺杂层上并具有活性电池区域和边缘终止区域的轻掺杂层。边缘终止区域包括多个P沟道MOSFET。通过将栅极连接到漏电极，当施加的电压等于或大于P沟道MOSFET晶体管的阈值电压Vt时，在边缘终端上形成的P沟道MOSFET晶体管顺序导通，从而优化电压被每个地区封锁

23. 发明申请

US20160005809A1 CONFIGURATION AND METHOD TO GENERATE SADDLE JUNCTION ELECTRIC FIELD IN EDGE TERMINATION 审中-公开
公开(公告)号：US20160005809A1
公开(公告)日：2016-01-07
申请号：US14298537
申请日：2014-06-06
申请人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
发明人： Madhur Bobde , Lingpeng Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L29/06 , H01L21/761
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/6609 , H01L29/861
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

24. 发明授权

US09231050B1 Configuration and method to generate saddle junction electric field in edge termination 有权
公开(公告)号：US09231050B1
公开(公告)日：2016-01-05
申请号：US14298537
申请日：2014-06-06
申请人： Madhur Bobde , Lingping Guan , Anup Bhalla , Hamza Yilmaz
发明人： Madhur Bobde , Lingping Guan , Anup Bhalla , Hamza Yilmaz
IPC分类号： H01L27/088 , H01L29/06 , H01L21/761
CPC分类号： H01L29/0634 , H01L21/26513 , H01L21/761 , H01L29/0615 , H01L29/0619 , H01L29/6609 , H01L29/861
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate and having an active cell area and an edge termination area the edge termination area wherein the edge termination area comprises a superjunction structure having doped semiconductor columns of alternating conductivity types with a charge imbalance between the doped semiconductor columns to generate a saddle junction electric field in the edge termination.

25. 发明授权

US09048282B2 Dual-gate trench IGBT with buried floating P-type shield 有权
标题翻译：双栅极沟槽IGBT，埋入浮动P型屏蔽
公开(公告)号：US09048282B2
公开(公告)日：2015-06-02
申请号：US13831066
申请日：2013-03-14
申请人： Jun Hu , Madhur Bobde , Hamza Yilmaz
发明人： Jun Hu , Madhur Bobde , Hamza Yilmaz
IPC分类号： H01L29/66 , H01L29/739
CPC分类号： H01L29/7395 , H01L29/0623 , H01L29/0696 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/66333
摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
摘要翻译：一种制造绝缘栅双极晶体管（IGBT）器件的方法，包括：1）制备具有第一导电类型的外延层的半导体衬底，该半导体衬底支撑在第二导电类型的半导体衬底上; 2）施加栅极沟槽掩模以打开第一沟槽和第二沟槽，随后形成栅极绝缘层以衬垫沟槽并用多晶硅层填充沟槽以形成第一沟槽栅极和第二沟槽栅极; 3）注入第一导电类型的掺杂剂以在外延层中形成上重掺杂区; 以及4）在所述第一沟槽栅极的顶部上形成平面栅极，并且将注入掩模施加到植入物体掺杂剂和源掺杂剂以在所述半导体衬底的顶表面附近形成体区域和源极区域。

26. 发明授权

US08802529B2 Semiconductor device with field threshold MOSFET for high voltage termination 有权
标题翻译：具有用于高电压端接的场阈值MOSFET的半导体器件
公开(公告)号：US08802529B2
公开(公告)日：2014-08-12
申请号：US13135985
申请日：2011-07-19
申请人： Hamza Yilmaz , Madhur Bobde
发明人： Hamza Yilmaz , Madhur Bobde
IPC分类号： H01L27/088
CPC分类号： H01L29/7813 , H01L27/088 , H01L29/0619 , H01L29/0638 , H01L29/0878 , H01L29/404 , H01L29/7803 , H01L29/7811
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate comprising a lightly doped layer formed on a heavily doped layer and having an active cell area and an edge termination area. The edge termination area comprises a plurality P-channel MOSFETs. By connecting the gate to the drain electrode, the P-channel MOSFET transistors formed on the edge termination are sequentially turned on when the applied voltage is equal to or greater than the threshold voltage Vt of the P-channel MOSFET transistors, thereby optimizing the voltage blocked by each region.
摘要翻译：本发明公开了一种设置在半导体衬底中的半导体功率器件，包括形成在重掺杂层上并具有活性电池区域和边缘终止区域的轻掺杂层。边缘终止区域包括多个P沟道MOSFET。通过将栅极连接到漏电极，当施加的电压等于或大于P沟道MOSFET晶体管的阈值电压Vt时，在边缘终端上形成的P沟道MOSFET晶体管顺序导通，从而优化电压被每个地区封锁

27. 发明授权

US08753935B1 High frequency switching MOSFETs with low output capacitance using a depletable P-shield 有权
标题翻译：具有低输出电容的高频开关MOSFET，采用可消耗P型屏蔽
公开(公告)号：US08753935B1
公开(公告)日：2014-06-17
申请号：US13724093
申请日：2012-12-21
申请人： Madhur Bobde , Hamza Yilmaz , Sik Lui , Daniel Ng
发明人： Madhur Bobde , Hamza Yilmaz , Sik Lui , Daniel Ng
IPC分类号： H01L21/336 , H01L21/28 , H01L29/40 , H01L29/423
CPC分类号： H01L29/7813 , H01L21/2257 , H01L27/0251 , H01L27/04 , H01L29/0619 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/4238 , H01L29/456 , H01L29/47 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7806 , H01L29/7808 , H01L29/7811
摘要： Aspects of the present disclosure describe a high density trench-based power MOSFETs with self-aligned source contacts and methods for making such devices. The source contacts are self-aligned with spacers and the active devices may have a two-step gate oxide. A lower portion may have a thickness that is larger than the thickness of an upper portion of the gate oxide. The MOSFETS also may include a depletable shield in a lower portion of the substrate. The depletable shield may be configured such that during a high drain bias the shield substantially depletes. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：本公开的方面描述了具有自对准源触点的高密度沟槽基功率MOSFET和用于制造这种器件的方法。源触点与间隔物自对准，并且有源器件可以具有两步栅极氧化物。下部可以具有比栅极氧化物的上部的厚度大的厚度。 MOSFET也可以在衬底的下部包括可消除的屏蔽。可消除的屏蔽可以被配置成使得在高排水偏压期间，屏蔽件基本上消耗掉。要强调的是，提供这个摘要是为了符合要求摘要的规则，允许搜索者或其他读者快速确定技术公开内容的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

28. 发明授权

US08710585B1 High voltage fast recovery trench diode 有权
公开(公告)号：US08710585B1
公开(公告)日：2014-04-29
申请号：US13776497
申请日：2013-02-25
申请人： Jun Hu , Karthik Padmanabhan , Madhur Bobde , Hamza Yilmaz
发明人： Jun Hu , Karthik Padmanabhan , Madhur Bobde , Hamza Yilmaz
IPC分类号： H01L29/66
CPC分类号： H01L29/0615 , H01L21/02104 , H01L29/0692 , H01L29/36 , H01L29/66136 , H01L29/861
摘要： Aspects of the present disclosure describe high voltage fast recovery trench diodes and methods for make the same. The device may have trenches that extend at least through a top P-layer and an N-barrier layer. A conductive material may be disposed in the trenches with a dielectric material lining the trenches between the conductive material and sidewalls of the trenches. A highly doped P-pocket may be formed in an upper portion of the top P-layer between the trenches. A floating N-pocket may be formed directly underneath the P-pocket. The floating N-pocket may be as wide as or wider than the P-pocket. It is emphasized that this abstract is provided to comply with rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.

29. 发明授权

US10199455B2 Dual-gate trench IGBT with buried floating P-type shield 有权
公开(公告)号：US10199455B2
公开(公告)日：2019-02-05
申请号：US15600782
申请日：2017-05-21
申请人： Jun Hu , Madhur Bobde , Hamza Yilmaz
发明人： Jun Hu , Madhur Bobde , Hamza Yilmaz
IPC分类号： H01L29/739 , H01L29/06 , H01L29/66 , H01L29/423 , H01L29/10 , H01L29/40 , H01L21/265
摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

30. 发明申请

US20170271441A1 DUAL-GATE TRENCH IGBT WITH BURIED FLOATING P-TYPE SHIELD 审中-公开
公开(公告)号：US20170271441A1
公开(公告)日：2017-09-21
申请号：US15600782
申请日：2017-05-21
申请人： Jun Hu , Madhur Bobde , Hamza Yilmaz
发明人： Jun Hu , Madhur Bobde , Hamza Yilmaz
IPC分类号： H01L29/06 , H01L29/66 , H01L21/266 , H01L21/265 , H01L29/423 , H01L29/739 , H01L29/40
CPC分类号： H01L29/0623 , H01L21/265 , H01L29/0696 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/42364 , H01L29/42368 , H01L29/42376 , H01L29/4238 , H01L29/66 , H01L29/66333 , H01L29/66348 , H01L29/7395 , H01L29/7397
摘要： A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.

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