专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US06197662B1 Semiconductor processing method of forming field isolation oxide using a polybuffered mask which includes a base nitride layer on the substrate, and other semiconductor processing methods 失效
标题翻译：使用包括基板上的基底氮化物层的多重缓冲掩膜形成场隔离氧化物的半导体加工方法以及其他半导体加工方法
公开(公告)号：US06197662B1
公开(公告)日：2001-03-06
申请号：US09288881
申请日：1999-04-09
申请人： Hiang C. Chan
发明人： Hiang C. Chan
IPC分类号： H01L2176
CPC分类号： H01L21/28202 , H01L21/32 , H01L21/76202 , H01L29/513 , H01L29/518
摘要： A semiconductor processing method of forming field isolation oxide relative to a silicon substrate includes, i) rapid thermal nitridizing an exposed silicon substrate surface to form a base silicon nitride layer on the silicon substrate; ii) providing a silicon nitride masking layer over the nitride base layer, the base and masking silicon nitride layers comprising a composite of said layers of a combined thickness effective to restrict appreciable oxidation of silicon substrate thereunder when the substrate is exposed to LOCOS conditions; and iii) exposing the substrate to oxidizing conditions effective to form field isolation oxide on substrate areas not masked by the base and masking silicon nitride layers composite. Further, a semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate includes, a) masking a first portion of a semiconductor substrate with a composite comprising a first nitride layer, a polysilicon layer over the nitride layer, and a second nitride layer over the polysilicon layer; and leaving a second portion of the semiconductor substrate unmasked by said composite; and b) exposing the semiconductor substrate to oxidizing conditions effective to form field isolation oxide in the second substrate portion.
摘要翻译：相对于硅衬底形成场隔离氧化物的半导体处理方法包括：i）快速热氮化暴露的硅衬底表面以在硅衬底上形成基底氮化硅层; ii）在氮化物基底层上提供氮化硅掩蔽层，所述基底和掩模氮化硅层包括具有组合厚度的所述层的复合材料，当所述衬底暴露于LOCOS条件时，其有效地限制硅衬底的明显氧化; 以及iii）将衬底暴露于有效地在未被基底掩蔽的掩模和掩蔽氮化硅层复合材料的衬底区域上形成场隔离氧化物的氧化条件。此外，相对于半导体衬底形成场隔离氧化物的半导体处理方法包括：a）用包含第一氮化物层，氮化物层上的多晶硅层和第二氮化物层的复合材料掩蔽半导体衬底的第一部分多晶硅层; 并留下未被所述复合材料掩蔽的半导体衬底的第二部分; 以及b）将所述半导体衬底暴露于在所述第二衬底部分中有效形成场隔离氧化物的氧化条件。

22. 发明授权

US5358894A Oxidation enhancement in narrow masked field regions of a semiconductor wafer 失效
标题翻译：半导体晶片的窄掩模场区域的氧化增强
公开(公告)号：US5358894A
公开(公告)日：1994-10-25
申请号：US175481
申请日：1993-12-30
申请人： Pierre Fazan , Viju Mathews , Gurtej S. Sandhu , Mohammed Anjum , Hiang C. Chan
发明人： Pierre Fazan , Viju Mathews , Gurtej S. Sandhu , Mohammed Anjum , Hiang C. Chan
IPC分类号： H01L21/316 , H01L21/762 , H01L21/76
CPC分类号： H01L21/02238 , H01L21/02299 , H01L21/31662 , H01L21/76213 , Y10S148/116 , Y10S148/163
摘要： A LOCOS process is enhanced by enhancing the depth of field oxide in regions having a narrow field oxide width. Subsequent to forming a pattern of nitride to define the field oxide and active area, photoresist is applied to selected areas of the wafer. An impurity is then applied to the underlying semiconductor substrate in areas not protected by photoresist and nitride. The impurity results in an enhanced oxidation rate and therefore compensates for a thinning effect in selected field oxide areas, such as those having a narrow width. Subsequent formation of the field oxide results in the doped material being consumed by the oxide.
摘要翻译：通过在具有窄场氧化物宽度的区域中增强场氧化物来增强LOCOS工艺。在形成氮化物图案以限定场氧化物和有源区域之后，将光致抗蚀剂施加到晶片的选定区域。然后在不受光致抗蚀剂和氮化物保护的区域中将杂质施加到下面的半导体衬底。杂质导致增强的氧化速率，因此补偿了选择的场氧化物区域（例如具有窄宽度的区域）中的稀化效应。随后形成场氧化物导致掺杂材料被氧化物消耗。

23. 发明授权

US5137842A Stacked H-cell capacitor and process to fabricate same 失效
标题翻译：堆叠H电池电容器和工艺制造相同
公开(公告)号：US5137842A
公开(公告)日：1992-08-11
申请号：US699291
申请日：1991-05-10
申请人： Hiang C. Chan , Pierre Fazan
发明人： Hiang C. Chan , Pierre Fazan
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/87 , H01L28/91
摘要： An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked H-Cell (SHC). The SHC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SHC is made up of a polysilicon storage node structure having a H-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SHC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an H-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.
摘要翻译：修改现有的堆叠电容器制造工艺以构建称为堆叠H电池（SHC）的三维叠层电容器。 SHC设计定义了在本发明中用于DRAM处理的电容器存储单元。 SHC由具有H形横截面上部的多晶硅存储节点结构构成，下部向下延伸并通过埋入触点与有源区接触。多晶硅存储节点结构由多晶硅覆盖，电介质夹在其间以形成完整的SHC电容器。具有H形横截面的新颖的三维多晶硅储存节点板允许在存储节点处获得大于常规STC的电容器板表面积为200％或更大的电容器板表面积。

24. 发明授权

US5126280A Stacked multi-poly spacers with double cell plate capacitor 失效
标题翻译：堆叠多聚合间隔物与双电池板电容器
公开(公告)号：US5126280A
公开(公告)日：1992-06-30
申请号：US653035
申请日：1991-02-08
申请人： Hiang C. Chan , Pierre Fazan
发明人： Hiang C. Chan , Pierre Fazan
IPC分类号： H01L27/04 , H01L21/02 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10852 , H01L27/10817 , H01L28/91
摘要： A multi-poly spacer, double-plate, stacked capacitor or MDSC using a modified stacked capacitor storage cell fabrication process. The MDSC is made up of a rectangular boxed-shaped polysilicon storage node structure, having multiple poly post residing in a buried contact used to connect the MDSC to an active area. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed MDSC. Developing the MDSC from a planarized surface allows the capacitor to be fabricated with only 2 photomask steps. With the 3-dimensional shape and a texturized surface of a polysilicon storage node plate, substantial capacitor plate surface area of 100% or more is gained at the storage node.
摘要翻译：一种多层间隔物，双层板，叠层电容器或MDSC，采用改进的堆叠电容器存储单元制造工艺。 MDSC由矩形盒形多晶硅存储节点结构组成，具有多个聚位置，位于用于将MDSC连接到有源区的埋入触点中。多晶硅存储节点结构被多晶硅覆盖，其间夹有介质以形成完整的MDSC。从平坦化表面开发MDSC可以使电容器仅制作2个光掩模步骤。利用三维形状和多晶硅存储节点板的纹理化表面，在存储节点处获得基本上为100％或更大的电容器板表面积。

25. 发明授权

US5966621A Semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate 失效
标题翻译：相对于半导体衬底形成场隔离氧化物的半导体处理方法
公开(公告)号：US5966621A
公开(公告)日：1999-10-12
申请号：US748996
申请日：1996-11-14
申请人： Hiang C. Chan
发明人： Hiang C. Chan
IPC分类号： H01L21/28 , H01L21/32 , H01L21/762 , H01L29/51 , H01L21/76
CPC分类号： H01L21/28202 , H01L21/32 , H01L21/76202 , H01L29/513 , H01L29/518
摘要： A semiconductor processing method of forming field isolation oxide relative to a silicon substrate includes, i) rapid thermal nitridizing an exposed silicon substrate surface to form a base silicon nitride layer on the silicon substrate; ii) providing a silicon nitride masking layer over the nitride base layer, the base and masking silicon nitride layers comprising a composite of said layers of a combined thickness effective to restrict appreciable oxidation of silicon substrate thereunder when the substrate is exposed to LOCOS conditions; and iii) exposing the substrate to oxidizing conditions effective to form field isolation oxide on substrate areas not masked by the base and masking silicon nitride layers composite. Further, a semiconductor processing method of forming field isolation oxide relative to a semiconductor substrate includes, a) masking a first portion of a semiconductor substrate with a composite comprising a first nitride layer, a polysilicon layer over the nitride layer, and a second nitride layer over the polysilicon layer; and leaving a second portion of the semiconductor substrate unmasked by said composite; and b) exposing the semiconductor substrate to oxidizing conditions effective to form field isolation oxide in the second substrate portion.
摘要翻译：相对于硅衬底形成场隔离氧化物的半导体处理方法包括：i）快速热氮化暴露的硅衬底表面以在硅衬底上形成基底氮化硅层; ii）在氮化物基底层上提供氮化硅掩蔽层，所述基底和掩模氮化硅层包括组合厚度的所述层的复合材料，其有效地在基底暴露于LOCOS条件时限制硅衬底的明显氧化; 以及iii）将衬底暴露于有效地在未被基底掩蔽的掩模和掩蔽氮化硅层复合材料的衬底区域上形成场隔离氧化物的氧化条件。此外，相对于半导体衬底形成场隔离氧化物的半导体处理方法包括：a）用包含第一氮化物层，氮化物层上的多晶硅层和第二氮化物层的复合材料掩蔽半导体衬底的第一部分多晶硅层; 并留下未被所述复合材料掩蔽的半导体衬底的第二部分; 以及b）将所述半导体衬底暴露于在所述第二衬底部分中有效形成场隔离氧化物的氧化条件。

26. 发明授权

US5281549A Process for fabricating a stacked capacitor having an I-shaped cross-section in a dynamic random access memory array 失效
标题翻译：在动态随机存取存储器阵列中制造具有I形截面的层叠电容器的工艺
公开(公告)号：US5281549A
公开(公告)日：1994-01-25
申请号：US985973
申请日：1992-12-04
申请人： Pierre Fazan , Hiang C. Chan
发明人： Pierre Fazan , Hiang C. Chan
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70 , H01L27/00
CPC分类号： H01L27/10817
摘要： An existing stacked capacitor fabrication process is modified to construct a three-dimensional stacked capacitor, referred to as a Stacked I-Cell (SIC). The SIC design defines a capacitor storage cell that in the present invention is used in a DRAM process. The SIC is made up of a polysilicon storage node structure having a I-shaped cross-sectional upper portion with a lower portion extending downward and making contact to an active area via a buried contact. The polysilicon storage node structure is overlaid by polysilicon with a dielectric sandwiched in between to form a completed SIC capacitor. The novel 3-dimensional shaped polysilicon storage node plate having an adjustable I-shaped cross-section, allows substantial capacitor plate surface area of 200% or more to be gained at the storage node over that of a conventional STC.
摘要翻译：修改现有的堆叠电容器制造工艺以构建称为堆叠式I型电池（SIC）的三维叠层电容器。 SIC设计定义了在本发明中用于DRAM工艺的电容器存储单元。 SIC由具有I形截面上部的多晶硅存储节点结构构成，下部具有向下延伸并通过埋入触点与有源区接触。多晶硅存储节点结构被多晶硅覆盖，电介质夹在其间以形成完整的SIC电容器。具有可调整的I形横截面的新颖的三维多晶硅储存节点板允许在存储节点处获得大于常规STC的电容器板表面积大于等于200％的电容器板表面积。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式