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21. 发明申请

US20060172567A1 Semiconductor device 有权
公开(公告)号：US20060172567A1
公开(公告)日：2006-08-03
申请号：US11329101
申请日：2006-01-11
申请人： Takuya Futatsuyama
发明人： Takuya Futatsuyama
IPC分类号： H05K1/00
CPC分类号： H01L23/5226 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device comprises: a plurality of first wiring lines formed in a first layer with a first wiring width and a first wiring space; a plurality of second wiring lines formed in a second layer different from the above-described first layer with a second wiring width and a second wiring space larger than the above-described first wiring width and first wiring space; and a contact plug connecting the first wiring line and second wiring line. The above-described contact plug is formed over a plurality of adjacent ones of the above-described first wiring lines and has a pattern connecting the plurality of adjacent ones of the above-described first wiring lines and one of the above-described second wiring lines.

22. 发明申请

US20050058011A1 Non-volatile semiconductor memory device, electronic card and electronic device 有权
标题翻译：非易失性半导体存储器件，电子卡和电子器件
公开(公告)号：US20050058011A1
公开(公告)日：2005-03-17
申请号：US10973437
申请日：2004-10-27
申请人： Takuya Futatsuyama , Koji Hosono
发明人： Takuya Futatsuyama , Koji Hosono
IPC分类号： G11C16/06 , G11C8/00 , G11C16/04 , G11C16/10 , G11C16/12 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C16/0483
摘要： A non-volatile semiconductor memory device, comprising a memory cell array including a plurality of electrically erasable programmable non-volatile memory cells arrayed and divided into a plurality of blocks; a plurality of word lines arranged in each of said plurality of blocks and each commonly connected to memory cells on an identical row; a plurality of drive lines provided corresponding to said plurality of word lines and each arranged to supply a voltage to the corresponding word line; a plurality of transfer transistors each operative as a switch to connect the corresponding word line to the corresponding drive line among said plurality of word lines and said plurality of drive lines, wherein said plurality of word lines are classified into an arbitrary word line determined arbitrarily, secondary adjacent word lines located adjacent to both word lines adjacent to said arbitrary word line, and residual word lines other than said arbitrary word line and said secondary adjacent word lines, and wherein among said plurality of transfer transistors, transfer transistors for said residual word lines are arranged at both adjacent locations and an opposite location around a transfer transistor for said arbitrary word line.
摘要翻译：一种非易失性半导体存储器件，包括一个存储单元阵列，该存储单元阵列包括排列并分成多个块的多个电可擦除可编程非易失性存储单元; 多个字线布置在所述多个块中的每一个中并且各自共同地连接到同一行上的存储器单元; 多个驱动线，与所述多个字线相对应地设置，每个驱动线被布置成向相应的字线提供电压; 多个传输晶体管，各自用作开关，用于将对应的字线连接到所述多个字线和所述多个驱动线中的对应的驱动线，其中所述多个字线被分类为任意确定的任意字线，位于与所述任意字线相邻的两条字线相邻的次级相邻字线以及除所述任意字线和所述次级相邻字线之外的剩余字线，并且其中在所述多个转移晶体管中，用于所述剩余字线的转移晶体管布置在两个相邻位置处，并且在用于所述任意字线的转移晶体管周围的相对位置。

23. 发明申请

US20050041515A1 Non-volatile semiconductor memory device, method for sub-block erase and electric device with the same 失效
标题翻译：非易失性半导体存储器件，子块擦除方法和电子器件相同
公开(公告)号：US20050041515A1
公开(公告)日：2005-02-24
申请号：US10678179
申请日：2003-10-06
申请人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
发明人： Takuya Futatsuyama , Kenichi Imamiya , Koji Hosono , Noboru Shibata
IPC分类号： G11C16/02 , G11C16/04 , G11C16/16 , G11C16/34 , G11C8/02
CPC分类号： G11C16/3445 , G11C16/04 , G11C16/16 , G11C16/3436 , G11C16/3459 , G11C29/50004
摘要： After execution of sub-block erase (S2) for partly erasing a memory cell block, sub-block erase verify read is executed (S4). As a result of the sub-block erase verify read, if the sub-block erase is completed, then terminate the sub-block erase (S5). If otherwise the sub-block erase is not completed yet, then perform over-program verify read (S6) to thereby determine whether the cause of an event that a sub-block erase-verify result becomes “Fail” due to the deficiency of erase or the presence of an over-programmed cell or cells. If the result of such over-program verify read is “Pass,” then repeat execution of the sub-block erase verify read (S2). When the over-program verify read (S6) is “Fail,” output a Fail result and then complete the operation (S8).
摘要翻译：在执行用于部分擦除存储单元块的子块擦除（S2）之后，执行子块擦除验证读取（S4）。作为子块擦除验证读取的结果，如果子块擦除完成，则终止子块擦除（S5）。否则子块擦除尚未完成，则执行过程编程验证读取（S6），从而确定由于擦除不足导致子块擦除验证结果的事件的原因为“失败” 或存在过度编程的细胞或细胞。如果这种过程编程验证读取的结果是“通过”，则重复执行子块擦除验证读取（S2）。当过程程序验证读取（S6）为“失败”时，输出失败结果，然后完成操作（S8）。

24. 发明申请

US20050013168A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE, ELECTRONIC CARD AND ELECTRONIC DEVICE 有权
标题翻译：非易失性半导体存储器件，电子卡和电子器件
公开(公告)号：US20050013168A1
公开(公告)日：2005-01-20
申请号：US10692799
申请日：2003-10-27
申请人： Takuya Futatsuyama , Koji Hosono
发明人： Takuya Futatsuyama , Koji Hosono
IPC分类号： G11C16/06 , G11C8/00 , G11C16/04 , G11C16/10 , G11C16/12 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/10 , G11C16/0483
摘要： A non-volatile semiconductor memory device, comprising a memory cell array including a plurality of electrically erasable programmable non-volatile memory cells arrayed and divided into a plurality of blocks; a plurality of word lines arranged in each of said plurality of blocks and each commonly connected to memory cells on an identical row; a plurality of drive lines provided corresponding to said plurality of word lines and each arranged to supply a voltage to the corresponding word line; a plurality of transfer transistors each operative as a switch to connect the corresponding word line to the corresponding drive line among said plurality of word lines and said plurality of drive lines, wherein said plurality of word lines are classified into an arbitrary word line determined arbitrarily, secondary adjacent word lines located adjacent to both word lines adjacent to said arbitrary word line, and residual word lines other than said arbitrary word line and said secondary adjacent word lines, and wherein among said plurality of transfer transistors, transfer transistors for said residual word lines are arranged at both adjacent locations and an opposite location around a transfer transistor for said arbitrary word line.
摘要翻译：一种非易失性半导体存储器件，包括一个存储单元阵列，该存储单元阵列包括排列并分成多个块的多个电可擦除可编程非易失性存储单元; 多个字线布置在所述多个块中的每一个中并且各自共同地连接到同一行上的存储器单元; 多个驱动线，与所述多个字线相对应地设置，每个驱动线被布置成向相应的字线提供电压; 多个传输晶体管，各自用作开关，用于将对应的字线连接到所述多个字线和所述多个驱动线中的对应的驱动线，其中所述多个字线被分类为任意确定的任意字线，位于与所述任意字线相邻的两条字线相邻的次级相邻字线以及除所述任意字线和所述次级相邻字线之外的剩余字线，并且其中在所述多个转移晶体管中，用于所述剩余字线的转移晶体管布置在两个相邻位置处，并且在用于所述任意字线的转移晶体管周围的相对位置。

25. 发明授权

US08233325B2 NAND flash memory 有权
标题翻译： NAND闪存
公开(公告)号：US08233325B2
公开(公告)日：2012-07-31
申请号：US13108641
申请日：2011-05-16
申请人： Kiyofumi Sakurai , Takuya Futatsuyama
发明人： Kiyofumi Sakurai , Takuya Futatsuyama
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/08 , G11C8/08 , G11C16/0483
摘要： A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group.
摘要翻译：一种利用存储块控制闪速存储器编程的方法。该方法包括检查存储器块中的所选块是否属于第一组或第二组。该方法还包括当所选择的块属于第一组时从最小位地址执行编程。该方法还包括当所选择的块属于第二组时从大多数位地址执行编程。

26. 发明申请

US20110267867A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110267867A1
公开(公告)日：2011-11-03
申请号：US13183103
申请日：2011-07-14
申请人： Makoto SAKUMA , Takuya Futatsuyama
发明人： Makoto SAKUMA , Takuya Futatsuyama
IPC分类号： G11C5/06
CPC分类号： G11C5/063 , H01L27/0207 , H01L27/105
摘要： A semiconductor device includes a memory cell array area, a peripheral circuit area on a periphery of the memory cell array area, and a boundary area having a specific width between the memory cell array area and the peripheral circuit area, the memory cell array area including a cell area including nonvolatile semiconductor memory cells, linear wirings extending from inside of the cell area to an area outside the cell area, and lower layer wirings in a lower layer than the linear wirings in the boundary area and electrically connected to the linear wirings, and wiring widths of the lower layer wirings being larger than widths of the linear wirings, the peripheral circuit area including a patterns electrically connected to the linear wirings via the lower layer wirings, the boundary area failing to be provided with the linear wirings and a wiring in same layer as the linear wirings.
摘要翻译：半导体器件包括存储单元阵列区域，存储单元阵列区域的外围的外围电路区域和存储单元阵列区域与外围电路区域之间具有特定宽度的边界区域，存储单元阵列区域包括包括非易失性半导体存储单元的单元区域，从单元区域的内部延伸到单元区域外的线性布线，以及比边界区域中的线性布线更下层的布线，并且电连接到线性布线，并且下层布线的布线宽度大于线性布线的宽度，外围电路区域包括经由下层布线电连接到线性布线的图案，不能设置线性布线的边界区域和布线与线性配线相同。

27. 发明申请

US20110242892A1 NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20110242892A1
公开(公告)日：2011-10-06
申请号：US13161147
申请日：2011-06-15
申请人： Yuko NAMIKI , Takuya Futatsuyama , Yuui Shimizu
发明人： Yuko NAMIKI , Takuya Futatsuyama , Yuui Shimizu
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454
摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.
摘要翻译：一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。

28. 发明授权

US08023327B2 Non-volatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08023327B2
公开(公告)日：2011-09-20
申请号：US12499237
申请日：2009-07-08
申请人： Takuya Futatsuyama
发明人： Takuya Futatsuyama
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/344
摘要： A memory device including a NAND string with multiple memory cells connected in series, one end of the NAND string being coupled to a bit line via a first select gate transistor while the other end is coupled to a source line via a second select gate transistor, wherein the device has a data read mode performed under the bias condition of: a selected cell is applied with a read voltage; and unselected cells are applied with read pass voltages, and wherein in the data read mode, one of the unselected cells adjacent to one of the first and second select gate transistor is applied with a first read pass voltage while the other unselected cells are applied with a second read pass voltage lower than the first read pass voltage.
摘要翻译：一种存储器件，包括具有串联连接的多个存储器单元的NAND串，所述NAND串的一端经由第一选择栅极晶体管耦合到位线，而另一端经由第二选择栅极晶体管耦合到源极线，其中所述设备具有在偏置条件下执行的数据读取模式：所选择的单元被施加读取电压; 并且未选择的单元被施加读通道电压，并且其中在数据读取模式中，与第一和第二选择栅极晶体管中的一个相邻的未选择单元之一被施加第一读取通过电压，而另一个未选择的单元被施加第二读通过电压低于第一读通道电压。

29. 发明授权

US07916548B2 Non-volatile semiconductor storage device and memory system 有权
标题翻译：非易失性半导体存储器件和存储器系统
公开(公告)号：US07916548B2
公开(公告)日：2011-03-29
申请号：US12418215
申请日：2009-04-03
申请人： Takuya Futatsuyama
发明人： Takuya Futatsuyama
IPC分类号： G11C16/06
CPC分类号： G11C16/344
摘要： A non-volatile semiconductor storage device includes: a memory cell array including memory strings, each of the memory strings having: a first end; a second end; and a plurality of memory cells connected in series between the first end and the second end, the memory cells being categorized into memory cell groups; a first end that is one end of the memory string; and a second end that is the other end of the memory string; first selection transistors connected to the respective first ends of the memory strings; a plurality of second selection transistors connected to the respective second ends of the memory strings; bit lines connected to the respective second selection transistors; word lines connected to the memory cells; and a control circuit configured to apply different control voltages to the respective word lines.
摘要翻译：非挥发性半导体存储装置包括：包括存储器串的存储单元阵列，每个存储器串具有：第一端; 第二端以及在所述第一端和所述第二端之间串联连接的多个存储单元，所述存储单元被分类为存储单元组; 第一端是存储器字符串的一端; 和作为存储器串的另一端的第二端; 连接到存储器串的各个第一端的第一选择晶体管; 连接到存储器串的相应第二端的多个第二选择晶体管; 连接到相应的第二选择晶体管的位线; 连接到存储单元的字线; 以及控制电路，被配置为对各个字线施加不同的控制电压。

30. 发明申请

US20100264547A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING 审中-公开
标题翻译：半导体器件及其制造方法
公开(公告)号：US20100264547A1
公开(公告)日：2010-10-21
申请号：US12774160
申请日：2010-05-05
申请人： KOSUKE YANAGIDAIRA , Takuya Futatsuyama , Toshiya Kotani
发明人： KOSUKE YANAGIDAIRA , Takuya Futatsuyama , Toshiya Kotani
IPC分类号： H01L23/52 , H01L23/544
CPC分类号： G11C5/02 , G11C5/063 , H01L27/105 , H01L27/115 , H01L27/11573
摘要： A first region having a first metal wiring, the first metal wiring being buried into an insulation film with a first minimum dimension, and a second region having a second metal wiring, the second metal wiring being buried in the insulation film with a second minimum dimension which is larger than the first minimum dimension, the second region being arranged adjacent to the first region, wherein a thickness of the first metal wiring and a thickness of the second metal wiring are different.
摘要翻译：具有第一金属布线的第一区域，所述第一金属布线被掩埋在具有第一最小尺寸的绝缘膜中，所述第二区域具有第二金属布线，所述第二金属布线以第二最小尺寸被掩埋在所述绝缘膜中其大于第一最小尺寸，第二区域布置成与第一区域相邻，其中第一金属布线的厚度和第二金属布线的厚度不同。

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