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21. 发明授权

US08130552B2 Multi-pass programming for memory with reduced data storage requirement 有权
标题翻译：用于存储器的多通程序编程，减少了数据存储要求
公开(公告)号：US08130552B2
公开(公告)日：2012-03-06
申请号：US12344763
申请日：2008-12-29
申请人： Toru Miwa , Gerrit Jan Hemink
发明人： Toru Miwa , Gerrit Jan Hemink
IPC分类号： G11C16/06
CPC分类号： G11C11/5628 , G11C16/3418 , G11C2211/5621
摘要： Coupling effects between adjacent floating gates in a non-volatile storage device are reduced in a multi-pass programming operation, while reducing program data storage requirements. In one approach, storage elements are programmed in an out of sequence or zigzag word line order. A particular word line is programmed with a coarse program pass, after which another word line is programmed with a fine program pass, after which the particular word line is read. The particular word line is read before another word line is programmed with a coarse program pass which causes coupling interference to storage elements of the particular word line. The read data is subsequently used to perform a fine program pass for the particular word line. This avoids the need to store program data of multiple word lines concurrently, so that storage hardware can be reduced in size along with power consumption.
摘要翻译：在多通道编程操作中减少非易失性存储设备中的相邻浮动栅极之间的耦合效应，同时减少程序数据存储要求。在一种方法中，存储元件被编程为不按顺序或之字形字线顺序。一个特定的字线用一个粗略的程序通道进行编程，之后用一个精细的程序通道对另一个字线进行编程，然后读取特定的字线。在另一个字线被粗略编程通道编程之前读取特定字线，其导致对特定字线的存储元件的耦合干扰。读取的数据随后用于执行特定字线的精细节目通行。这避免了同时存储多个字线的程序数据的需要，使得存储硬件可以与功耗一起减小。

22. 发明授权

US08099652B1 Non-volatile memory and methods with reading soft bits in non uniform schemes 有权
标题翻译：非易失性存储器和在非均匀方案中读取软位的方法
公开(公告)号：US08099652B1
公开(公告)日：2012-01-17
申请号：US12978322
申请日：2010-12-23
申请人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Yee Lih Koh
发明人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Yee Lih Koh
IPC分类号： G11C29/00
CPC分类号： G11C16/26 , G06F11/1072 , G11C11/5642 , G11C29/00 , G11C2029/0411
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The reference thresholds of the second set are set up to be non-uniformly distributed on the threshold window so as to provide higher resolution at designated regions. At the same time they are conducive to be read in groups for soft bits to be read bit-by-bit systematically with a simple algorithm and read circuit and using a minimum of data latches. This is accomplished by relaxing the requirement that the first set of reference threshold is a subset of the second set and that the resulting soft bits are symmetrically distributed about the hard bits.
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。第二组的参考阈值被设置为在阈值窗口上不均匀地分布，以便在指定区域提供更高的分辨率。同时，它们有助于读取组中的软位，通过简单的算法和读取电路并使用最少的数据锁存器逐位读取。这是通过放宽第一组参考阈值是第二组的子集并且所得到的软比特关于硬比特对称分布的要求来实现的。

23. 发明申请

US20080137432A1 Program Time Adjustment as Function of Program Voltage For Improved Programming Speed in Memory System 有权
标题翻译：程序时间调整作为程序电压的功能，用于提高存储系统中的编程速度
公开(公告)号：US20080137432A1
公开(公告)日：2008-06-12
申请号：US12019422
申请日：2008-01-24
申请人： Shih-Chung Lee , Toru Miwa
发明人： Shih-Chung Lee , Toru Miwa
IPC分类号： G11C16/06
CPC分类号： G11C5/145 , G11C16/04 , G11C16/12 , G11C29/02 , G11C29/021 , G11C29/023 , G11C29/028
摘要： In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the required threshold voltage is reduced. For example, programming time period may be increased with an increase in the voltage level of the pump pulse required. This allows the programming time period of the program pulse to be increased to a value that compensates for the increased charge-up time that is required for the higher amplitude program pulses to reach the desired programming voltage.
摘要翻译：在非易失性存储器系统中，分配给编程脉冲的编程时间段被调整为所需泵脉冲的电压电平的函数，使得将电荷存储元件编程到所需阈值所需的泵浦脉冲的总数电压降低。例如，编程时间可以随着所需泵脉冲的电压电平的增加而增加。这允许将编程脉冲的编程时间段增加到补偿更高幅度编程脉冲达到所需编程电压所需的增加的充电时间的值。

24. 发明授权

US08842476B2 Erratic program detection for non-volatile storage 有权
标题翻译：用于非易失性存储的错误程序检测
公开(公告)号：US08842476B2
公开(公告)日：2014-09-23
申请号：US13292569
申请日：2011-11-09
申请人： Manabu Sakai , Toru Miwa
发明人： Manabu Sakai , Toru Miwa
IPC分类号： G11C11/34 , G11C16/04 , G11C16/08 , G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3454
摘要： Methods and non-volatile storage systems are provided for determining erratically programmed storage elements, including under-programmed and over-programmed storage elements. Techniques do not require any additional data latches. A set of data latches may be used to store program data for a given memory element. This program data may be maintained after the programming is over for use in erratic program detection. In one embodiment, lockout status is kept in a data latch that is used to serially receive program data to be programmed into the storage element. Therefore, no extra data latches are required to program the storage elements and to maintain the program data afterwards.
摘要翻译：提供方法和非易失性存储系统用于确定不规则编程的存储元件，包括欠编程和过程编程的存储元件。技术不需要任何额外的数据锁存器。一组数据锁存器可用于存储给定存储器元件的程序数据。该程序数据可以在编程结束之后保持，以用于不规则的程序检测。在一个实施例中，锁定状态保存在数据锁存器中，该数据锁存器用于串行地接收要编程到存储元件中的程序数据。因此，不需要额外的数据锁存器来对存储元件进行编程并且之后维护程序数据。

25. 发明申请

US20140063961A1 WRITE DATA PRESERVATION FOR NON-VOLATILE STORAGE 有权
标题翻译：写入数据保存非易失性存储
公开(公告)号：US20140063961A1
公开(公告)日：2014-03-06
申请号：US13605583
申请日：2012-09-06
申请人： Manabu Sakai , Toru Miwa , Tien-chien Kuo
发明人： Manabu Sakai , Toru Miwa , Tien-chien Kuo
IPC分类号： G11C16/10 , G11C16/04
CPC分类号： G11C11/5628 , G11C2211/5621
摘要： Methods and non-volatile storage systems are provided for recovering data during a programming of non-volatile storage. Program data that was originally stored in one set of latches may be preserved with a combination of two sets of latches. These two sets of latches may also be used to store verify status during programming of that program data. The original program data may be recovered by performing a logical operation on the data in the two sets of latches. For example, upper page data could be initially stored in one set of latches. While the upper page data is being programmed, that set of latches and another set of latches are used to store verify status with respect to the upper page data. If a program error occurs while the upper page data is being preserved, it may be recovered by performing a logical operation on the two sets of latches.
摘要翻译：提供方法和非易失性存储系统用于在非易失性存储器的编程期间恢复数据。最初存储在一组锁存器中的程序数据可以通过两组锁存器的组合来保存。这两组锁存器也可用于在该程序数据的编程期间存储验证状态。可以通过对两组锁存器中的数据执行逻辑运算来恢复原始程序数据。例如，上页数据可以最初存储在一组锁存器中。当上位数据被编程时，该组锁存器和另一组锁存器用于存储相对于上位数据的验证状态。如果在保留上位页数据时发生程序错误，则可以通过对两组锁存器执行逻辑运算来恢复程序错误。

26. 发明授权

US07675780B2 Program time adjustment as function of program voltage for improved programming speed in memory system 有权
标题翻译：程序时间调整作为程序电压的功能，以提高存储系统中的编程速度
公开(公告)号：US07675780B2
公开(公告)日：2010-03-09
申请号：US12019422
申请日：2008-01-24
申请人： Shih-Chung Lee , Toru Miwa
发明人： Shih-Chung Lee , Toru Miwa
IPC分类号： G11C16/12
CPC分类号： G11C5/145 , G11C16/04 , G11C16/12 , G11C29/02 , G11C29/021 , G11C29/023 , G11C29/028
摘要： In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the required threshold voltage is reduced. For example, programming time period may be increased with an increase in the voltage level of the pump pulse required. This allows the programming time period of the program pulse to be increased to a value that compensates for the increased charge-up time that is required for the higher amplitude program pulses to reach the desired programming voltage.
摘要翻译：在非易失性存储器系统中，分配给编程脉冲的编程时间段被调整为所需泵脉冲的电压电平的函数，使得将电荷存储元件编程到所需阈值所需的泵浦脉冲的总数电压降低。例如，编程时间可以随着所需泵脉冲的电压电平的增加而增加。这允许将编程脉冲的编程时间段增加到补偿更高幅度编程脉冲达到所需编程电压所需的增加的充电时间的值。

27. 发明授权

US08498152B2 Non-volatile memory and methods with soft-bit reads while reading hard bits with compensation for coupling 有权
标题翻译：非易失性存储器和具有软位读取的方法，同时读取具有补偿补偿的硬比特
公开(公告)号：US08498152B2
公开(公告)日：2013-07-30
申请号：US12978368
申请日：2010-12-23
申请人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Nima Mokhlesi
发明人： Idan Alrod , Eran Sharon , Toru Miwa , Gerrit Jan Hemink , Nima Mokhlesi
IPC分类号： G11C11/34
CPC分类号： G11C16/34 , G06F11/1072 , G11C11/5642 , G11C16/26 , G11C16/3422 , G11C16/3427 , G11C29/00
摘要： A non-volatile memory has its cells' thresholds programmed within any one of a first set of voltage bands partitioned by a first set of reference thresholds across a threshold window. Hard bits are obtained when read relative to the first set of reference thresholds. The cells are read at a higher resolution relative to a second set of reference thresholds so as to provide additional soft bits for error correction. The soft bits are generated by a combination of a first modulation of voltage on a current word line WLn and a second modulation of voltage on an adjacent word line WLn+1, as in a reading scheme known as “Direct-Lookahead (DLA)”.
摘要翻译：非易失性存储器的单元的阈值被编程在跨越阈值窗口的第一组参考阈值划分的第一组电压带的任一个中。当读取相对于第一组参考阈值时，获得硬比特。相对于第二组参考阈值以更高的分辨率读取单元，以便提供用于纠错的附加软比特。软位是通过对当前字线WLn上的电压的第一次调制和相邻字线WLn + 1上的电压的第二调制的组合产生的，如在称为“直读先锋（DLA）”的读取方案中。

28. 发明授权

US07672163B2 Control gate line architecture 有权
标题翻译：控制门线架构
公开(公告)号：US07672163B2
公开(公告)日：2010-03-02
申请号：US12060746
申请日：2008-04-01
申请人： Toru Miwa
发明人： Toru Miwa
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/08
摘要： A non-volatile storage system that includes less word line drivers than word lines by having a limited set of individually controllable drivers for a subset of unselected word lines requiring word line by word line control, and have the remaining word lines connected to a common source.
摘要翻译：一种非易失性存储系统，其包括比字线更少的字线驱动，通过对于需要字线逐字控制的未选择字线的子集具有有限的可单独控制的驱动器组，并且将剩余字线连接到公共源。

29. 发明授权

US07330373B2 Program time adjustment as function of program voltage for improved programming speed in memory system 有权
标题翻译：程序时间调整作为程序电压的功能，以提高存储系统中的编程速度
公开(公告)号：US07330373B2
公开(公告)日：2008-02-12
申请号：US11391811
申请日：2006-03-28
申请人： Shih-Chung Lee , Toru Miwa
发明人： Shih-Chung Lee , Toru Miwa
IPC分类号： G11C16/12
CPC分类号： G11C5/145 , G11C16/04 , G11C16/12 , G11C29/02 , G11C29/021 , G11C29/023 , G11C29/028
摘要： In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the required threshold voltage is reduced. For example, programming time period may be increased with an increase in the voltage level of the pump pulse required. This allows the programming time period of the program pulse to be increased to a value that compensates for the increased charge-up time that is required for the higher amplitude program pulses to reach the desired programming voltage.
摘要翻译：在非易失性存储器系统中，分配给编程脉冲的编程时间段被调整为所需泵脉冲的电压电平的函数，使得将电荷存储元件编程到所需阈值所需的泵浦脉冲的总数电压降低。例如，编程时间可以随着所需泵脉冲的电压电平的增加而增加。这允许将编程脉冲的编程时间段增加到补偿更高幅度编程脉冲达到所需编程电压所需的增加的充电时间的值。

30. 发明授权

US07327608B2 Program time adjustment as function of program voltage for improved programming speed in programming method 有权
标题翻译：程序时间调整作为编程电压的功能，可以提高编程方式的编程速度
公开(公告)号：US07327608B2
公开(公告)日：2008-02-05
申请号：US11392265
申请日：2006-03-28
申请人： Shih-Chung Lee , Toru Miwa
发明人： Shih-Chung Lee , Toru Miwa
IPC分类号： G11C16/12
CPC分类号： G11C16/3454 , G11C16/12 , G11C16/32
摘要： In a non-volatile memory system, the programming time period allocated for the program pulse is adjusted as a function of the voltage level of the pump pulse required so that the total number of pump pulses required to program the charge storage element to the required threshold voltage is reduced. For example, programming time period may be increased with an increase in the voltage level of the pump pulse required. This allows the programming time period of the program pulse to be increased to a value that compensates for the increased charge-up time that is required for the higher amplitude program pulses to reach the desired programming voltage.
摘要翻译：在非易失性存储器系统中，分配给编程脉冲的编程时间段被调整为所需泵脉冲的电压电平的函数，使得将电荷存储元件编程到所需阈值所需的泵浦脉冲的总数电压降低。例如，编程时间可以随着所需泵脉冲的电压电平的增加而增加。这允许将编程脉冲的编程时间段增加到补偿更高幅度编程脉冲达到所需编程电压所需的增加的充电时间的值。

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