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21. 发明申请

US20130151732A1 ELECTRONIC DEVICE AND PORT REDUCING METHOD 失效
标题翻译：电子设备和端口减少方法
公开(公告)号：US20130151732A1
公开(公告)日：2013-06-13
申请号：US13564734
申请日：2012-08-02
申请人： PO-CHUAN HSIEH , CHUN-NENG LIAO , SHIN-TING YEN
发明人： PO-CHUAN HSIEH , CHUN-NENG LIAO , SHIN-TING YEN
IPC分类号： G06F3/00
CPC分类号： G06F17/5036
摘要： An exemplary port reducing method is for removing unselected ports of an original S-parameter file and generating an optimized S-parameter file. The method controls a display unit to display a user interface to receive commands from a user in response to user operation; the commands comprise a calling command, a selecting command, and an executing command. The method obtains the original S-parameter file in response to the calling command Next, the method determines which of the ports of the original S-parameter file are unselected in response to the selecting command, and connects each unselected port to the ground through one terminal impedance. The method then generates an optimized S-parameter file that comprises only the selected ports in response to the executing command.
摘要翻译：示例性的端口减少方法用于去除原始S参数文件的未选择端口并生成优化的S参数文件。该方法控制显示单元以响应于用户操作显示用户界面以从用户接收命令; 命令包括调用命令，选择命令和执行命令。该方法响应于调用命令获得原始S参数文件Next，该方法根据选择命令确定原始S参数文件的哪些端口未被选择，并通过一个连接每个未选择的端口到地面端子阻抗。该方法然后响应于执行命令生成仅包括所选择的端口的优化的S参数文件。

22. 发明申请

US20130093530A1 MARCHAND BALUN CIRCUIT 失效
标题翻译： MARCHAND巴伦电路
公开(公告)号：US20130093530A1
公开(公告)日：2013-04-18
申请号：US13326226
申请日：2011-12-14
申请人： EN-SHUO CHANG , PO-CHUAN HSIEH , YING-TSO LAI
发明人： EN-SHUO CHANG , PO-CHUAN HSIEH , YING-TSO LAI
IPC分类号： H01P5/10
CPC分类号： H01P5/10
摘要： A Marchand balun circuit includes a Marchand balun, an unbalanced matching circuit, and a balanced matching circuit. The Marchand balun includes an unbalanced terminal, and two balanced terminals. The unbalanced matching circuit includes a first and the second impedances which are connected between the unbalanced terminal and ground in series, and a first resistor which is connected between ground and a connection node of the first and the second impedances. The balanced matching circuit includes a third and a fourth impedances which are connected between one balanced terminal and ground in series, a fifth and a sixth impedance which are connected between the other balanced terminal and ground in series, a second resistor which is connected between ground and a connection node of the third and the fourth impedances, and a third resistor which is connected between ground and a connection node of the fifth and the sixth impedances.
摘要翻译： Marchand平衡 - 不平衡变换器电路包括Marchand平衡 - 不平衡转换器，不平衡匹配电路和平衡匹配电路。 Marchand平衡 - 不平衡变压器包括不平衡端子和两个平衡端子。不平衡匹配电路包括串联连接在不平衡端子和地之间的第一和第二阻抗，以及连接在地和第一和第二阻抗的连接节点之间的第一电阻器。平衡匹配电路包括连接在一个平衡端子和串联的地之间的第三和第四阻抗，连接在另一个平衡端子和地串联之间的第五和第六阻抗，连接在地之间的第二电阻器以及第三和第四阻抗的连接节点，以及连接在地与第五和第六阻抗的连接节点之间的第三电阻器。

23. 发明申请

US20140060914A1 ENCLOSURE WITH SHIELD APPARATUS 失效
标题翻译：外壳与外壳设备
公开(公告)号：US20140060914A1
公开(公告)日：2014-03-06
申请号：US13602337
申请日：2012-09-04
申请人： CHENG-HSIU YANG , PO-CHUAN HSIEH
发明人： CHENG-HSIU YANG , PO-CHUAN HSIEH
IPC分类号： H05K9/00
CPC分类号： H05K9/0041
摘要： An enclosure includes a sidewall defining a number of first vents and a shield apparatus installed to the sidewall. The shield apparatus includes a shield plate spaced from the sidewall. A distance between the sidewall and the shield plate is greater than a size of the first vent. The shield plate defines a number of second vents respectively aligning with the first vents.
摘要翻译：外壳包括限定多个第一通风孔的侧壁和安装在侧壁上的屏蔽装置。屏蔽装置包括与侧壁间隔开的屏蔽板。侧壁和屏蔽板之间的距离大于第一通气口的尺寸。屏蔽板限定了与第一通风口对准的多个第二通风口。

24. 发明申请

US20120145448A1 PRINTED CIRCUIT BOARD WITH COMPOUND VIA 失效
标题翻译：印刷电路板与化合物通过
公开(公告)号：US20120145448A1
公开(公告)日：2012-06-14
申请号：US13031617
申请日：2011-02-22
申请人： YUNG-CHIEH CHEN , CHENG-HSIEN LEE , PO-CHUAN HSIEH , SHOU-KUO HSU , SHIN-TING YEN , DAN-CHEN WU , JIA-CHI CHEN
发明人： YUNG-CHIEH CHEN , CHENG-HSIEN LEE , PO-CHUAN HSIEH , SHOU-KUO HSU , SHIN-TING YEN , DAN-CHEN WU , JIA-CHI CHEN
IPC分类号： H05K1/11
CPC分类号： H05K1/0251 , H05K1/0225 , H05K1/0295 , H05K1/0298 , H05K1/113
摘要： A printed circuit board (PCB) with compound via includes a substrate and a pair of through holes passing through the substrate. The substrate includes a signal layer which is the top layer of the substrate, a first reference layer adjacent to the signal layer, and a second reference layer not adjacent to the signal layer. A first and a second pair of pads are mounted on the signal layer. Each of the through holes extends through the first pair of pads such that the through hole and the first pair of pads jointly form a compound via. A first reserved opening is formed on the first reference layer and corresponds to the first and the second pair of pads and the compound via. A second reserved opening is formed on the second reference layer and surrounds the through hole thereon.
摘要翻译：具有复合通孔的印刷电路板（PCB）包括基板和穿过基板的一对通孔。衬底包括作为衬底的顶层的信号层，与信号层相邻的第一参考层和不与信号层相邻的第二参考层。第一和第二对焊盘安装在信号层上。每个通孔延伸穿过第一对垫，使得通孔和第一对垫共同形成复合通孔。第一保留开口形成在第一参考层上，并且对应于第一和第二对焊盘和复合通孔。第二保留开口形成在第二参考层上并围绕其上的通孔。

25. 发明申请

US20130284508A1 PRINTED CIRCUIT BOARD 审中-公开
标题翻译：印刷电路板
公开(公告)号：US20130284508A1
公开(公告)日：2013-10-31
申请号：US13563856
申请日：2012-08-01
申请人： WEI-CHIEH CHOU , CHUN-JEN CHEN , DUEN-YI HO , TSUNG-SHENG HUANG , PO-CHUAN HSIEH , CHUN-NENG LIAO
发明人： WEI-CHIEH CHOU , CHUN-JEN CHEN , DUEN-YI HO , TSUNG-SHENG HUANG , PO-CHUAN HSIEH , CHUN-NENG LIAO
IPC分类号： H05K1/11
CPC分类号： H05K1/0216 , H05K2201/09618
摘要： A printed circuit board (PCB) includes a power layer and a signal layer. A signal line is arranged on the signal layer. A power via extends through the power layer and the signal layer, and is electrically connected to the power layer and the signal layer. A number of through holes is defined in the PCB, through the power layer and the signal layer, and arranged between the signal line and the power via. The through holes are insulated from the power via. The inside wall of the power via is made of conductive material.
摘要翻译：印刷电路板（PCB）包括功率层和信号层。信号线布置在信号层上。功率通孔延伸通过功率层和信号层，并且电连接到功率层和信号层。在PCB中通过功率层和信号层定义了多个通孔，并布置在信号线和电源通孔之间。通孔与电源通孔绝缘。电源通孔的内壁由导电材料制成。

26. 发明申请

US20130222082A1 EQUALIZER FOR MULTI-LEVEL EQUALIZATION 审中-公开
标题翻译：均衡化的多级均衡
公开(公告)号：US20130222082A1
公开(公告)日：2013-08-29
申请号：US13564768
申请日：2012-08-02
申请人： PO-CHUAN HSIEH , YING-TSO LAI , CHENG-HSIEN LEE
发明人： PO-CHUAN HSIEH , YING-TSO LAI , CHENG-HSIEN LEE
IPC分类号： H04B3/14
CPC分类号： H04B3/14
摘要： An equalizer includes a first delay module, a second delay module, a first amplitude module, a second amplitude module, and a combining unit. The first delay module receives a first signal and delays the first received signal for a preset period, and the first amplitude module transfers the first delayed signal to transmit a first weighted signal with a first peak amplitude. Similarly, the second delay module receives the first delayed signal and delays the second received signal for the preset period, and the second amplitude module transfers the second delayed signal to transmit a second weighted signal with a second peak amplitude. The combining unit combines an input signal and the first and the second weighted signals together to generate an equalized signal.
摘要翻译：均衡器包括第一延迟模块，第二延迟模块，第一振幅模块，第二振幅模块和组合单元。第一延迟模块接收第一信号并将第一接收信号延迟预设周期，并且第一幅度模块传送第一延迟信号以发送具有第一峰值幅度的第一加权信号。类似地，第二延迟模块接收第一延迟信号并将第二接收信号延迟预设周期，并且第二幅度模块传送第二延迟信号以发送具有第二峰值振幅的第二加权信号。组合单元将输入信号和第一和第二加权信号组合在一起以产生均衡的信号。

27. 发明申请

US20130006561A1 COMPUTING DEVICE, STORAGE MEDIUM, AND METHOD FOR ANALYZING SIGNAL GROUP DELAY OF PRINTED CIRCUIT BOARD 审中-公开
标题翻译：计算机设备，存储介质和分析印刷电路板信号组延迟的方法
公开(公告)号：US20130006561A1
公开(公告)日：2013-01-03
申请号：US13451433
申请日：2012-04-19
申请人： PO-CHUAN HSIEH , CHUN-JEN CHEN , YING-TSO LAI , EN-SHUO CHANG
发明人： PO-CHUAN HSIEH , CHUN-JEN CHEN , YING-TSO LAI , EN-SHUO CHANG
IPC分类号： G06F19/00
CPC分类号： G06F17/5036 , G06F17/5068 , G06F2217/62 , G06F2217/82
摘要： In a method for analyzing a signal group delay of a printed circuit board (PCB) using a computing device, the computing device connects to a signal measuring device that measures S-parameters from a pair of data signal line and clock signal line of the PCB. The method analyzes a differential loss coefficient of the data signal line and the clock signal line based on the S-parameters, and calculates a first signal delay of the data signal line and a second signal delay of the clock signal line according to the differential loss coefficient. The method further analyzes a signal group delay of the PCB according to the first signal delay and the second signal delay, and displays the signal group delay on a display device if the signal group delay does not satisfy a PCB design specification.
摘要翻译：在使用计算设备分析印刷电路板（PCB）的信号组延迟的方法中，计算设备连接到从PCB的一对数据信号线和时钟信号线测量S参数的信号测量装置。该方法基于S参数分析数据信号线和时钟信号线的差分损耗系数，并根据差分损耗计算数据信号线的第一信号延迟和时钟信号线的第二信号延迟系数。该方法还根据第一信号延迟和第二信号延迟分析PCB的信号组延迟，并且如果信号组延迟不满足PCB设计规范，则在显示装置上显示信号组延迟。

28. 发明申请

US20120125679A1 PRINTED CIRCUIT BOARD HAVING DIFFERENTIAL VIAS 审中-公开
标题翻译：印刷电路板有差异的VIAS
公开(公告)号：US20120125679A1
公开(公告)日：2012-05-24
申请号：US13032653
申请日：2011-02-23
申请人： YUNG-CHIEH CHEN , CHENG-HSIEN LEE , PO-CHUAN HSIEH , SHOU-KUO HSU , SHIN-TING YEN
发明人： YUNG-CHIEH CHEN , CHENG-HSIEN LEE , PO-CHUAN HSIEH , SHOU-KUO HSU , SHIN-TING YEN
IPC分类号： H05K1/11
CPC分类号： H05K1/0251 , H05K1/0245 , H05K1/116
摘要： A printed circuit board includes an insulating board, a pair of differential vias, and a number of wiring layers. A pair of via holes extends through opposite surfaces of the insulating board. The differential vias correspond to the pair of via holes. Each differential via includes a metal plated barrel and two via capture pads. The plated barrel is plated on the inner surface of the respective via hole, and terminates at each of the two opposite surfaces of the insulating board. The via capture pads are formed on the opposite surfaces of the insulating board around the openings of the via hole, and are electrically connected to the plated barrel. The wiring layers are arranged in the insulating board, and each define a clearance hole surrounding all of the via capture pads.
摘要翻译：印刷电路板包括绝缘板，一对差动通孔和多个布线层。一对通孔延伸穿过绝缘板的相对表面。差分过孔对应于一对通孔。每个差分通孔包括一个金属电镀桶和两个通孔捕获垫。电镀桶被镀在相应通孔的内表面上，并且终止于绝缘板的两个相对表面的每一个。通孔捕获垫形成在绝缘板的围绕通孔的开口的相对表面上，并且电连接到电镀桶。布线层布置在绝缘板中，并且每个限定围绕所有通孔捕获垫的间隙孔。

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