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21. 发明授权

US06677635B2 Stacked MIMCap between Cu dual damascene levels 有权
标题翻译： Cu双重镶嵌层之间堆叠MIMCap
公开(公告)号：US06677635B2
公开(公告)日：2004-01-13
申请号：US09870499
申请日：2001-06-01
申请人： Xian J. Ning , Yi Sheng Hsieh
发明人： Xian J. Ning , Yi Sheng Hsieh
IPC分类号： H01L27108
CPC分类号： H01L28/40 , H01L21/76807 , H01L21/76838
摘要： A semiconductor device includes a structure composed of a first inter-level-dielectric with an embedded first Cu dual damascene level. A dielectric is coated on a surface of the structure, and a patterned metal layer is coated on he dielectric. A patterned inter-level-dielectric is coated on the patterned metal layer, and a second Cu dual damascene level is embedded in the patterned inter-level-dielectric. The first Cu dual damascene level, second Cu dual damascene level, and patterned metal layer respectively define the bottom, top and middle plates of a stacked MIM capacitor.
摘要翻译：半导体器件包括由具有嵌入的第一Cu双镶嵌层的第一层间电介质构成的结构。电介质涂覆在结构的表面上，并且在其电介质上涂覆图案化的金属层。图案化的层间电介质涂覆在图案化的金属层上，并且第二Cu双镶嵌层被嵌入在图案化的层间电介质中。第一个Cu双镶嵌层，第二个Cu双镶嵌层和图案化金属层分别定义堆叠的MIM电容器的底部，顶部和中间板。

22. 发明授权

US6033984A Dual damascene with bond pads 失效
标题翻译：双镶嵌键盘
公开(公告)号：US6033984A
公开(公告)日：2000-03-07
申请号：US997682
申请日：1997-12-23
申请人： Rainer Florian Schnabel , Xian J. Ning , Bruno Spuler
发明人： Rainer Florian Schnabel , Xian J. Ning , Bruno Spuler
IPC分类号： H01L23/52 , H01L21/3205 , H01L21/60 , H01L21/768 , H01L23/485 , H01L21/4763
CPC分类号： H01L24/48 , H01L21/76804 , H01L21/76813 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/04042 , H01L2224/05546 , H01L2224/05556 , H01L2224/05557 , H01L2224/05559 , H01L2224/13099 , H01L2224/45124 , H01L2224/45147 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48699 , H01L2224/48799 , H01L2924/0001 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/05042 , H01L2924/10157 , H01L2924/10253 , H01L2924/1306 , H01L2924/14 , H01L2924/3025
摘要： An improved method of forming a bond pad (222) by performing a dual damascene etch through a layer stack (200) disposed above a substrate (204) using self aligned vias (216). The layer (200) stack includes an underlying conductive layer (208) and an insulating layer (202) disposed above the underlying conductive layer (208). The method includes the following operative steps. At least a via hole (216) is formed in the insulating layer (202) positioned over the underlying device layer (208) and extending to the underlying device layer (208) at the bottom of the via hole. A bond pad trench (218) is then formed that takes the form of the desired bond pad (222). A layer of conductive material (220) is then placed over the insulating layer (202) substantially simultaneously filling the via hole (216) and the bond pad trench (218). The bond pad (222) is then formed by removing the layer of conductive material (220) sufficient to expose the upper surface of the insulating layer (210).
摘要翻译：通过使用自对准通孔（216）通过设置在衬底（204）上方的层堆叠（200）执行双镶嵌蚀刻来形成接合焊盘（222）的改进方法。层（200）堆叠包括下面的导电层（208）和设置在下面的导电层（208）上方的绝缘层（202）。该方法包括以下操作步骤。在绝缘层（202）中形成至少一个通孔（216），所述绝缘层（202）位于下面的器件层（208）上并延伸到通孔底部的下面的器件层（208）。然后形成接合焊盘沟槽（218），其采用期望的接合焊盘（222）的形式。然后将一层导电材料（220）放置在绝缘层（202）上，基本上同时填充通孔（216）和接合焊盘沟槽（218）。然后通过去除足以暴露绝缘层（210）的上表面的导电材料层（220）来形成接合焊盘（222）。

23. 发明授权

US08106423B2 Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors 有权
标题翻译：使用用于应变硅MOS晶体管的栅极图案化的纯二氧化硅硬掩模的方法和结构
公开(公告)号：US08106423B2
公开(公告)日：2012-01-31
申请号：US12145268
申请日：2008-06-24
申请人： Hanming Wu , Jiang Zhang , John Chen , Xian J. Ning
发明人： Hanming Wu , Jiang Zhang , John Chen , Xian J. Ning
IPC分类号： H01L29/66
CPC分类号： H01L29/7848 , H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/66545 , H01L29/66636
摘要： A structure using pure silicon dioxide hard marsk for gate pattern. In an embodiment, the present invention provides a partially completed semiconductor integrated circuit device. The device has a semiconductor substrate and a dielectric layer overlying the semiconductor substrate. The device has a gate structure including edges and a substantially pure silicon dioxide mask structure overlying the gate structure. A thickness ranging from about 400 to about 600 Angstroms of the substantially pure silicon dioxide mask structure is included. The device has a dielectric layer forming sidewall spacers on the edges of the gate structure to protect the gate structure including the edges and an exposed portion of the pure silicon dioxide mask structure overlying the gate structure. The device has an epitaxially grown fill material in an etched source region and an etched drain region.
摘要翻译：一种使用纯二氧化硅硬马尔斯克进行栅极图案的结构。在一个实施例中，本发明提供了部分完成的半导体集成电路器件。该器件具有覆盖半导体衬底的半导体衬底和电介质层。该器件具有包括边缘的栅极结构和覆盖栅极结构的基本上纯的二氧化硅掩模结构。包括约400至约600埃基本上纯的二氧化硅掩模结构的厚度。器件具有在栅极结构的边缘上形成侧壁间隔物的电介质层，以保护包括边缘的栅极结构和覆盖栅极结构的纯二氧化硅掩模结构的暴露部分。该器件在蚀刻源区和蚀刻漏极区中具有外延生长的填充材料。

24. 发明授权

US06858441B2 MRAM MTJ stack to conductive line alignment method 失效
标题翻译： MRAM MTJ堆叠到导线对准方法
公开(公告)号：US06858441B2
公开(公告)日：2005-02-22
申请号：US10234864
申请日：2002-09-04
申请人： Joachim Nuetzel , Xian J. Ning , Kia-Seng Low , Gill Yong Lee , Rajiv M. Ranade , Ravikumar Ramachandran
发明人： Joachim Nuetzel , Xian J. Ning , Kia-Seng Low , Gill Yong Lee , Rajiv M. Ranade , Ravikumar Ramachandran
IPC分类号： H01L23/544 , H01L27/22 , H01L21/28
CPC分类号： H01L27/222 , H01L23/544 , H01L2223/54453 , H01L2924/0002 , Y10S438/975 , H01L2924/00
摘要： A method of manufacturing a resistive semiconductor memory device (100), comprising depositing an insulating layer (132) over a workpiece (30), and defining a pattern for a plurality of alignment marks (128) and a plurality of conductive lines (112) within the insulating layer (132). A conductive material is deposited over the wafer to fill the alignment mark (128) and conductive line (112) patterns. The insulating layer (132) top surface is chemically-mechanically polished to remove excess conductive material from the insulating layer (132) and form conductive lines (112), while leaving conductive material remaining within the alignment marks (128). A masking layer (140) is formed over the conductive lines (112), and at least a portion of the conductive material is removed from within the alignment marks (128). The alignment marks (128) are used for alignment of subsequently deposited layers of the resistive memory device (100).
摘要翻译：一种制造电阻半导体存储器件（100）的方法，包括在工件（30）上沉积绝缘层（132），并且限定用于多个对准标记（128）和多条导线（112）的图案，在绝缘层（132）内。导电材料沉积在晶片上以填充对准标记（128）和导线（112）图案。绝缘层（132）顶表面被化学机械抛光以从绝缘层（132）去除多余的导电材料并形成导电线（112），同时留下导电材料留在对准标记（128）内。掩模层（140）形成在导电线（112）之上，并且导电材料的至少一部分从对准标记（128）内移除。对准标记（128）用于电阻式存储器件（100）的后续沉积层的对准。

25. 发明授权

US06815248B2 Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed layer in MRAM processing 失效
标题翻译： MRAM处理中隧道结盖层，隧道结硬掩模和隧道结堆叠种子层的材料组合
公开(公告)号：US06815248B2
公开(公告)日：2004-11-09
申请号：US10124950
申请日：2002-04-18
申请人： Rainer Leuschner , George Stojakovic , Xian J. Ning
发明人： Rainer Leuschner , George Stojakovic , Xian J. Ning
IPC分类号： H01L2100
CPC分类号： H01L27/228 , B82Y25/00 , B82Y40/00 , G11C11/16 , H01F41/308 , H01L43/12
摘要： A resistive memory device (110) and method of manufacturing thereof comprising a cap layer (140) and hard mask layer (142) disposed over magnetic stacks (114), wherein either the cap layer (140) or hard mask layer (142) comprise WN. A seed layer (136) disposed beneath the magnetic stacks (114) may also be comprised of WN, The use of the material WN improves etch process selectivity during the manufacturing process.
摘要翻译：一种电阻式存储器件（110）及其制造方法，包括设置在磁性堆叠（114）上的盖层（140）和硬掩模层（142），其中盖层（140）或硬掩模层（142） WN。设置在磁性堆叠（114）下方的种子层（136）也可以由WN组成。在制造过程中使用材料WN提高了蚀刻工艺的选择性。

26. 发明授权

US06692898B2 Self-aligned conductive line for cross-point magnetic memory integrated circuits 有权
标题翻译：用于交叉磁存储集成电路的自对准导线
公开(公告)号：US06692898B2
公开(公告)日：2004-02-17
申请号：US09923266
申请日：2001-08-03
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： G03F700
CPC分类号： G11C11/16 , B82Y10/00 , G11C11/15 , H01L27/222
摘要： Method of forming a magnetic memory device are disclosed. In one embodiment, a first plurality of conductive lines are formed over a semiconductor workpiece. A plurality of magnetic material lines are formed over corresponding ones of the first plurality of conductive lines and a second plurality of conductive lines are formed over the semiconductor workpiece. The second plurality of conductive lines cross over the first conductive lines and the magnetic material lines. These second lines can be used as a mask to while the magnetic material lines are patterned.
摘要翻译：公开了形成磁存储器件的方法。在一个实施例中，在半导体工件上形成第一多个导电线。多个磁性材料线形成在第一多个导电线中的相应的导线上，并且在半导体工件上形成第二多个导电线。第二多个导电线在第一导电线和磁性材料线上交叉。当磁性材料线被图案化时，这些第二条线可以用作掩模。

27. 发明授权

US06620701B2 Method of fabricating a metal-insulator-metal (MIM) capacitor 有权
标题翻译：制造金属绝缘体金属（MIM）电容器的方法
公开(公告)号：US06620701B2
公开(公告)日：2003-09-16
申请号：US09977004
申请日：2001-10-12
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： H01L2120
CPC分类号： H01L28/90 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a metal-insulator-metal capacitor (MIMCap) (36) including first conductive lines (15), capacitor dielectric (26) and second conductive lines (28), the MIMCap (36) including horizontal capacitive portions (32) and vertical capacitive portions (34). The method includes forming first conductive lines (15) in a first insulating layer (14) of a wafer (10), depositing a second insulating layer (22), depositing a resist, removing portions of the resist, removing exposed portions of the second insulating layer (22) and portions of the first insulating layer (14), removing the remaining resist, and then depositing a capacitor dielectric (26) and second conductive lines (28).
摘要翻译：一种包括第一导电线（15），电容电介质（26）和第二导线（28）的金属 - 绝缘体 - 金属电容器（MIMCap）（36）的制造方法，所述MIMCap（36）包括水平电容部分（32）和垂直电容部分（34）。该方法包括在晶片（10）的第一绝缘层（14）中形成第一导线（15），沉积第二绝缘层（22），沉积抗蚀剂，去除抗蚀剂的部分，去除第二绝缘层绝缘层（22）和第一绝缘层（14）的部分，去除剩余的抗蚀剂，然后沉积电容器电介质（26）和第二导电线（28）。

28. 发明授权

US06611453B2 Self-aligned cross-point MRAM device with aluminum metallization layers 有权
公开(公告)号：US06611453B2
公开(公告)日：2003-08-26
申请号：US09797245
申请日：2001-03-01
申请人： Xian J. Ning
发明人： Xian J. Ning
IPC分类号： G11C1114
CPC分类号： G11C11/15 , B82Y10/00 , H01L27/222
摘要： An MRAM device (160) and manufacturing process thereof having aluminum conductive lines (134) and (152), with self-aligning cross-points. Conductive lines (134) and metal stack (138) are patterned in a single patterning step and etched. Conductive lines (152) positioned orthogonally to conductive lines (134) are patterned simultaneously with the patterning of metal stack (138) and are etched. The metal stack (138) serves as an anti-reflective coating for conductive lines (152) during the etching process. A multi-level MRAM device may be manufactured in accordance with an embodiment of the invention.

29. 发明授权

US06184134B2 Dry process for cleaning residues/polymers after metal etch 有权
标题翻译：金属蚀刻后清洁残留物/聚合物的干法
公开(公告)号：US06184134B2
公开(公告)日：2001-02-06
申请号：US09506892
申请日：2000-02-18
申请人： Nirmal Chaudhary , Xian J. Ning , George Stojakovic
发明人： Nirmal Chaudhary , Xian J. Ning , George Stojakovic
IPC分类号： H01L2144
CPC分类号： H01L21/02071 , Y10S438/906
摘要： An all dry, low temperature process, for complete removal of organics and inorganic residues after metal etch of a microelectronic device comprising: rinsing a microelectronic device having a metallization layer after metal etch with a solution of ammonium hydroxide and hydrogen peroxide; subjecting the rinsed metallization layer to a low temperature GaSonics cleaning by exposing photoresist residue surface of the metallization layer to a fluorine containing reactive gas to form volatile compounds in the presence of a radio frequency input followed by photoresist stripping in an oxygen plasma at low temperature; subjecting the low temperature GaSonics treated residue surface to a gaseous SO3 strip at low temperature to remove additional residue; and rinsing the SO3 stripped material with de-ionized water to remove any remaining resist and residue.
摘要翻译：全部干燥的低温过程，用于在微电子器件的金属蚀刻之后完全去除有机物和无机残留物，包括：在用氢氧化铵和过氧化氢溶液进行金属蚀刻之后，冲洗具有金属化层的微电子器件; 通过将金属化层的光致抗蚀剂残留物表面暴露于含氟反应性气体，在漂移的金属化层的存在下，在低频下在氧等离子体中进行光致抗蚀剂剥离，在射频输入的存在下进行低温GaSonics清洗; 将低温GaSonics处理的残余物表面在低温下经受气态SO 3条带以除去附加残余物; 并用去离子水冲洗SO3汽提材料，以除去任何残留的抗蚀剂和残留物。

30. 发明授权

US5903343A Method for detecting under-etched vias 失效
标题翻译：检测欠蚀孔的方法
公开(公告)号：US5903343A
公开(公告)日：1999-05-11
申请号：US997460
申请日：1997-12-23
申请人： Xian J. Ning , Rainer Florian Schnabel
发明人： Xian J. Ning , Rainer Florian Schnabel
IPC分类号： H01L21/3205 , G01N1/32 , G01N21/00 , G01N21/95 , G01N21/956 , G01Q80/00 , H01L21/306 , H01L21/66 , G01N21/84
CPC分类号： B82Y15/00 , G01N1/32 , G01N21/9501 , G01N21/95692
摘要： Methods for detecting under-etched vias, spaces, or under-polished portions in a wafer stack are disclosed. The wafer stack comprises a dielectric layer disposed on a metal layer. The dielectric layer has a plurality of vias etched therein. The wafer stack, including the plurality of vias, is exposed to an etchant which is configured to etch the metal layer at a substantially faster rate than the dielectric layer. As a result, cavities are formed in the metal layer below properly-etched vias. Then, the vias in the wafer stack are optically inspected to detect and identify under-etched vias, which reflect more light than the cavities etched into the metal layer.
摘要翻译：公开了用于检测晶片叠层中未经蚀刻的通路，间隔或欠抛光部分的方法。晶片堆叠包括设置在金属层上的电介质层。电介质层具有蚀刻在其中的多个通孔。包括多个通孔的晶片堆叠暴露于蚀刻剂，蚀刻剂被配置为以比介电层更快的速率蚀刻金属层。结果，在恰当蚀刻的通孔下面的金属层中形成空腔。然后，对晶片堆叠中的通孔进行光学检查，以检测和识别未被蚀刻到金属层中的空腔的较暗的反射光。

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