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21. 发明授权

US08000148B2 Methods of operating nonvolatile memory devices 有权
标题翻译：操作非易失性存储设备的方法
公开(公告)号：US08000148B2
公开(公告)日：2011-08-16
申请号：US12805501
申请日：2010-08-03
申请人： Won-joo Kim , Tae-hee Lee , Jae-woong Hyun , Yoon-dong Park
发明人： Won-joo Kim , Tae-hee Lee , Jae-woong Hyun , Yoon-dong Park
IPC分类号： G11C16/04
CPC分类号： G11C16/34
摘要： Methods of operating nonvolatile memory devices are provided. In a method of operating a nonvolatile memory device including a plurality of memory cells, recorded data is stabilized by inducing a boosting voltage on a channel of a memory cell in which the recorded data is recorded. The memory cell is selected from a plurality of memory cells and the boosting voltage on the channel of the selected memory cell is induced by a channel voltage of at least one memory cell connected to the selected memory cell.
摘要翻译：提供了非易失性存储器件的操作方法。在操作包括多个存储单元的非易失性存储器件的方法中，通过在其中记录有记录数据的存储单元的通道上感应升压电压来稳定记录数据。从多个存储单元中选择存储单元，并且所选存储单元的通道上的升压电压由连接到所选存储单元的至少一个存储单元的通道电压引起。

22. 发明申请

US20100133647A1 Semiconductor devices and semiconductor device manufacturing methods 审中-公开
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20100133647A1
公开(公告)日：2010-06-03
申请号：US12591718
申请日：2009-11-30
申请人： Won-joo Kim , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park
发明人： Won-joo Kim , Sang-moo Choi , Tae-hee Lee , Yoon-dong Park
IPC分类号： H01L27/12 , H01L21/762
CPC分类号： H01L27/1203 , H01L21/76224 , H01L21/84 , H01L27/108 , H01L27/10802 , H01L27/1207 , H01L29/7841
摘要： Semiconductor devices and semiconductor device manufacturing methods. The semiconductor device manufacturing methods may form a memory cell having a silicon on insulator (SOI) structure only in one or more localized regions of a bulk semiconductor substrate by use selective etching. Accordingly, a different bias voltage may be applied to a peripheral device than to a memory cell having the SOI structure.
摘要翻译：半导体器件和半导体器件制造方法。半导体器件制造方法可以通过使用选择性蚀刻在体半导体衬底的一个或多个局部区域中形成具有绝缘体上硅（SOI）结构的存储单元。因此，与具有SOI结构的存储单元相比，可以向外围设备施加不同的偏置电压。

23. 发明申请

US20090091975A1 Non-volatile memory device and operation method of the same 有权
标题翻译：非易失性存储器件及其操作方法相同
公开(公告)号：US20090091975A1
公开(公告)日：2009-04-09
申请号：US12081679
申请日：2008-04-18
申请人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
发明人： Tae-hee Lee , Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-eung Yoon
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , H01L27/11521 , H01L27/11568
摘要： Provided are a non-volatile memory device and an operation method of the same. The non-volatile memory device may include one or more main strings each of which may include first and second substrings which may separately include a plurality of memory cell transistors; and a charge supply line which may be configured to provide charges to or block charges from the first and second substrings of each of the main strings, wherein each of the main strings may include a first ground selection transistor which may be connected to the first substring; a first substring selection transistor which may be connected to the first ground selection transistor; a second ground selection transistor which may be connected to the second substring; and a second substring selection transistor which may be connected to the second ground selection transistor.
摘要翻译：提供了一种非易失性存储器件及其操作方法。非易失性存储器件可以包括一个或多个主串，每个主弦可以包括可以分别包括多个存储单元晶体管的第一和第二子串; 以及电荷供给线，其可以被配置为向每个主串的第一和第二子串提供电荷或阻止电荷，其中每个主串可以包括第一接地选择晶体管，其可以连接到第一子串 ; 可以连接到第一接地选择晶体管的第一子串选择晶体管; 可以连接到第二子串的第二接地选择晶体管; 以及可以连接到第二接地选择晶体管的第二子串选择晶体管。

24. 发明授权

US08385122B2 Non-volatile memory device having stacked structure, and memory card and electronic system including the same 有权
标题翻译：具有堆叠结构的非易失性存储器件，以及包括其的存储卡和电子系统
公开(公告)号：US08385122B2
公开(公告)日：2013-02-26
申请号：US12656043
申请日：2010-01-14
申请人： Won-joo Kim , Yoon-dong Park , Jung-hun Sung , Yong-koo Kyoung , Sang-moo Choi , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , Jung-hun Sung , Yong-koo Kyoung , Sang-moo Choi , Tae-hee Lee
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L27/11578 , G11C16/0483 , G11C16/08 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11556
摘要： Provided are a non-volatile memory devices having a stacked structure, and a memory card and a system including the same. A non-volatile memory device may include a substrate. A stacked NAND cell array may have at least one NAND set and each NAND set may include a plurality of NAND strings vertically stacked on the substrate. At least one signal line may be arranged on the substrate so as to be commonly coupled with the at least one NAND set.
摘要翻译：提供了具有堆叠结构的非易失性存储器件，以及存储卡和包括其的系统。非易失性存储器件可以包括衬底。堆叠的NAND单元阵列可以具有至少一个NAND组，并且每个NAND组可以包括垂直堆叠在衬底上的多个NAND串。至少一个信号线可以布置在衬底上，以便与至少一个NAND组共同耦合。

25. 发明授权

US07813180B2 Non-volatile memory devices and methods of operating the same 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US07813180B2
公开(公告)日：2010-10-12
申请号：US12005376
申请日：2007-12-27
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-hee Lee
IPC分类号： G11C7/00
CPC分类号： H01L29/7881 , G11C16/3418 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/66825
摘要： Example embodiment non-volatile memory devices may be capable of increased integration and reliability and may provide example methods of operating non-volatile memory devices. Example embodiment non-volatile memory devices may include a first control gate electrode on a semiconductor substrate. A first charge storing layer may be between the semiconductor substrate and the first control gate electrode. A source region may be defined in the semiconductor substrate at one side of the first control gate electrode. A first auxiliary gate electrode may be at the other side of the first control gate electrode and may be recessed into the semiconductor substrate. A first drain region may be defined in the semiconductor substrate at one side of the first auxiliary gate electrode opposite to the first control gate electrode. A bit line may be connected to the first drain region.
摘要翻译：示例性实施例非易失性存储器设备可能能够提高集成度和可靠性，并且可以提供操作非易失性存储器设备的示例性方法。示例性实施例非易失性存储器件可以包括半导体衬底上的第一控制栅电极。第一电荷存储层可以在半导体衬底和第一控制栅电极之间。源区域可以在第一控制栅电极的一侧的半导体衬底中限定。第一辅助栅电极可以在第一控制栅电极的另一侧，并且可以凹入到半导体衬底中。第一漏极区域可以在第一辅助栅电极的与第一控制栅电极相对的一侧的半导体衬底中限定。位线可以连接到第一漏区。

26. 发明申请

US20080175061A1 Non-volatile memory devices and methods of operating the same 失效
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20080175061A1
公开(公告)日：2008-07-24
申请号：US12005376
申请日：2007-12-27
申请人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-hee Lee
发明人： Won-joo Kim , Yoon-dong Park , June-mo Koo , Suk-pil Kim , Tae-hee Lee
IPC分类号： G11C16/06 , H01L29/788
CPC分类号： H01L29/7881 , G11C16/3418 , H01L27/115 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/66825
摘要： Example embodiment non-volatile memory devices may be capable of increased integration and reliability and may provide example methods of operating non-volatile memory devices. Example embodiment non-volatile memory devices may include a first control gate electrode on a semiconductor substrate. A first charge storing layer may be between the semiconductor substrate and the first control gate electrode. A source region may be defined in the semiconductor substrate at one side of the first control gate electrode. A first auxiliary gate electrode may be at the other side of the first control gate electrode and may be recessed into the semiconductor substrate. A first drain region may be defined in the semiconductor substrate at one side of the first auxiliary gate electrode opposite to the first control gate electrode. A bit line may be connected to the first drain region.
摘要翻译：示例性实施例非易失性存储器设备可能能够提高集成度和可靠性，并且可以提供操作非易失性存储器设备的示例性方法。示例性实施例非易失性存储器件可以包括半导体衬底上的第一控制栅电极。第一电荷存储层可以在半导体衬底和第一控制栅电极之间。源区域可以在第一控制栅电极的一侧的半导体衬底中限定。第一辅助栅电极可以在第一控制栅电极的另一侧，并且可以凹入到半导体衬底中。第一漏极区域可以在第一辅助栅电极的与第一控制栅电极相对的一侧的半导体衬底中限定。位线可以连接到第一漏区。

27. 发明授权

US08283711B2 Non-volatile memory devices having data storage layer 有权
标题翻译：具有数据存储层的非易失性存储器件
公开(公告)号：US08283711B2
公开(公告)日：2012-10-09
申请号：US12149209
申请日：2008-04-29
申请人： Young-gu Jin , Yoon-dong Park , Won-joo Kim , Seung-hoon Lee , Suk-pil Kim
发明人： Young-gu Jin , Yoon-dong Park , Won-joo Kim , Seung-hoon Lee , Suk-pil Kim
IPC分类号： H01L29/792
CPC分类号： G11C5/02 , G11C5/025 , H01L27/2409 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226 , H01L45/143 , H01L45/144 , H01L45/146
摘要： Provided are a non-volatile memory device, which may have a stacked structure and may be easily integrated at increased density, and a method of fabricating and using the non-volatile memory device. The non-volatile memory device may include at least one pair of first electrode lines. At least one second electrode line may be between the at least one pair of first electrode lines. At least one data storage layer may be between the at least one pair of first electrode lines and the at least one second electrode line and may locally store a resistance change.
摘要翻译：提供了一种非易失性存储器件，其可以具有堆叠结构并且可以容易地以增加的密度集成，以及制造和使用非易失性存储器件的方法。非易失性存储器件可以包括至少一对第一电极线。至少一个第二电极线可以在所述至少一对第一电极线之间。至少一个数据存储层可以在至少一对第一电极线和至少一个第二电极线之间，并且可以局部地存储电阻变化。

28. 发明授权

US08058701B2 Antifuse structures, antifuse array structures, methods of manufacturing the same 有权
标题翻译：防污结构，反熔丝阵列结构，制造方法
公开(公告)号：US08058701B2
公开(公告)日：2011-11-15
申请号：US12216094
申请日：2008-06-30
申请人： Deok-kee Kim , Yoon-dong Park , Seung-hoon Lee , I-hun Song , Won-joo Kim , Young-gu Jin , Hyuk-soon Choi , Suk-pil Kim
发明人： Deok-kee Kim , Yoon-dong Park , Seung-hoon Lee , I-hun Song , Won-joo Kim , Young-gu Jin , Hyuk-soon Choi , Suk-pil Kim
IPC分类号： H01L23/52
CPC分类号： H01L23/5252 , G11C17/16 , H01L27/1021 , H01L2924/0002 , H01L2924/00
摘要： Antifuse structures, antifuse arrays, methods of manufacturing, and methods of operating the same are provided. An antifuse structure includes bitlines formed as first diffusing regions within a semiconductor substrate, an insulation layer formed on the bitlines, and wordlines formed on the insulation layer. An antifuse array includes a plurality of antifuse structures arranged in an array.
摘要翻译：提供了防泡结构，反熔丝阵列，制造方法和操作方法。反熔丝结构包括在半导体衬底内形成为第一扩散区的位线，形成在位线上的绝缘层，以及形成在绝缘层上的字线。反熔丝阵列包括排列成阵列的多个反熔丝结构。

29. 发明授权

US08017477B2 Nonvolatile memory devices and methods of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US08017477B2
公开(公告)日：2011-09-13
申请号：US11704205
申请日：2007-02-09
申请人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park
发明人： Won-joo Kim , Suk-pil Kim , Yoon-dong Park
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42332 , H01L29/42336 , H01L29/42352 , H01L29/66621 , H01L29/7881 , H01L29/792
摘要： A nonvolatile memory device includes a plurality of first control gate electrodes, second control gate electrodes, first storage node films, and second storage node films. The first control gate electrodes are recessed into a semiconductor substrate. Each second control gate electrode is disposed between two adjacent first control gate electrodes. The second control gate electrodes are disposed on the semiconductor substrate over the first control gate electrodes. The first storage node films are disposed between the semiconductor substrate and the first control gate electrodes. The second storage node films are disposed between the semiconductor substrate and the second control gate electrodes. A method of fabricating the nonvolatile memory device includes forming the first storage node films, forming the first control gate electrodes, forming the second storage node films, and forming the second control gate electrodes.
摘要翻译：非易失性存储器件包括多个第一控制栅电极，第二控制栅电极，第一存储节点膜和第二存储节点膜。第一控制栅电极凹入半导体衬底。每个第二控制栅电极设置在两个相邻的第一控制栅电极之间。第二控制栅电极设置在第一控制栅电极上的半导体衬底上。第一存储节点膜设置在半导体衬底和第一控制栅电极之间。第二存储节点膜设置在半导体衬底和第二控制栅电极之间。一种制造非易失性存储器件的方法包括形成第一存储节点膜，形成第一控制栅电极，形成第二存储节点膜，以及形成第二控制栅电极。

30. 发明授权

US07833890B2 Semiconductor device having a pair of fins and method of manufacturing the same 失效
标题翻译：具有一对翅片的半导体器件及其制造方法
公开(公告)号：US07833890B2
公开(公告)日：2010-11-16
申请号：US12457366
申请日：2009-06-09
申请人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
发明人： Won-joo Kim , June-mo Koo , Seung-hwan Song , Suk-pil Kim , Yoon-dong Park , Jong-jin Lee
IPC分类号： H01L21/4763
CPC分类号： H01L21/28273 , H01L21/28282 , H01L29/66795 , H01L29/66825 , H01L29/66833 , H01L29/785 , H01L29/7881 , H01L29/792
摘要： Example embodiments relate to a semiconductor device and a method of manufacturing the same. A semiconductor device according to example embodiments may have reduced disturbances during reading operations and a reduced short channel effect. The semiconductor device may include a semiconductor substrate having a body and a pair of fins protruding from the body. Inner spacer insulating layers may be formed on an upper portion of an inner sidewall of the pair of fins so as to reduce the entrance to the region between the pair of fins. A gate electrode may cover a portion of the external sidewalls of the pair of fins and may extend across the inner spacer insulating layers so as to define a void between the pair of fins. Gate insulating layers may be interposed between the gate electrode and the pair of fins.
摘要翻译：示例性实施例涉及半导体器件及其制造方法。根据示例实施例的半导体器件可以在读取操作期间具有减小的干扰，并且减少短信道效应。半导体器件可以包括具有主体和从主体突出的一对鳍片的半导体衬底。可以在一对翅片的内侧壁的上部形成内隔离层绝缘层，以减少对一对翅片之间的区域的入口。栅极电极可以覆盖一对鳍片的外部侧壁的一部分，并且可以跨越内部间隔物绝缘层延伸，以便在一对鳍片之间限定空隙。栅绝缘层可以插入在栅电极和一对鳍之间。

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