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21. 发明申请

US20130274416A1 GRAFT MONOMER COMPOSITION FOR THERMOPLASTIC TRANSPARENT RESIN, COMPOSITION FOR THERMOPLASTIC TRANSPARENT RESIN USING THE SAME, AND THERMOPLASTIC TRANSPARENT RESIN HAVING GOOD TRANSPARENCY AND COLOR 有权
标题翻译：用于热塑性透明树脂的热成型单体组合物，使用该热塑性透明树脂的热塑性透明树脂的组合物和具有良好透明度和颜色的热塑性透明树脂
公开(公告)号：US20130274416A1
公开(公告)日：2013-10-17
申请号：US13996462
申请日：2011-12-23
申请人： Jeong-Su Choi , Keun-Hoon Yoo , Hyong-Min Bahn , Won-Seok Lee , Seok-Goo Jang
发明人： Jeong-Su Choi , Keun-Hoon Yoo , Hyong-Min Bahn , Won-Seok Lee , Seok-Goo Jang
IPC分类号： C08F279/02 , C08L51/04
CPC分类号： C08F279/02 , C08L51/04 , C08L53/02 , C08L55/02 , C08L33/10 , C08F212/10 , C08F220/18 , C08F220/06 , C08F2220/286
摘要： Disclosed is a graft monomer composition for thermoplastic transparent resins, a composition for thermoplastic transparent resins using the same and a thermoplastic transparent resin that exhibits superior transparency and color at low rubber contents. According to the graft monomer composition, the composition for thermoplastic transparent resins and the thermoplastic transparent resin, although the content of rubber in final products increases or the content of rubber in graft copolymers in the preparation of final products increases, the copolymer surrounds the surface of rubber well, thus reducing haze, considerably improving transparency and exhibiting excellent natural color.
摘要翻译：公开了用于热塑性透明树脂的接枝单体组合物，使用该树脂的热塑性透明树脂的组合物和在低橡胶含量下表现出优异的透明度和颜色的热塑性透明树脂。根据接枝单体组合物，用于热塑性透明树脂的组合物和热塑性透明树脂，尽管最终产品中橡胶的含量增加或接枝共聚物中的橡胶含量在最终产物的制备中增加，但共聚物包围表面橡胶井，从而减少雾度，显着提高透明度并表现出优异的自然色。

22. 发明申请

US20090164723A1 Memory card 失效
标题翻译：存储卡
公开(公告)号：US20090164723A1
公开(公告)日：2009-06-25
申请号：US12314600
申请日：2008-12-12
申请人： Won-Seok Lee
发明人： Won-Seok Lee
IPC分类号： G06F12/02 , G06K19/00 , G06F12/00
CPC分类号： H01L25/18 , H01L23/49855 , H01L25/0655 , H01L2224/16 , H01L2224/16145 , H05K1/111 , H05K1/181 , H05K2201/10159 , H05K2201/10515 , Y02P70/611
摘要： The memory card includes a memory controller covered by a main body, a first non-volatile memory, a memory interface configured to transfer a signal between the memory controller and the first non-volatile memory, and a cover coupled to the main body and removeably covering the first memory and the memory interface. Here, the memory interface includes a connection detector configured to generate a connection detector signal when sensing that a package including a second non-volatile memory is added.
摘要翻译：存储卡包括由主体覆盖的存储器控制器，第一非易失性存储器，被配置为在存储器控制器和第一非易失性存储器之间传送信号的存储器接口以及耦合到主体并可移除的盖子涵盖了第一个内存和内存接口。这里，存储器接口包括连接检测器，其被配置为当感测到包括第二非易失性存储器的包装被添加时产生连接检测器信号。

23. 发明申请

US20080109700A1 SEMICONDUCTOR MEMORY DEVICE AND DATA ERROR DETECTION AND CORRECTION METHOD OF THE SAME 失效
标题翻译：半导体存储器件及其数据错误检测及校正方法
公开(公告)号：US20080109700A1
公开(公告)日：2008-05-08
申请号：US11773214
申请日：2007-07-03
申请人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
发明人： Kwang-Jin Lee , Won-Seok Lee , Du-Eung Kim
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1076 , G11C8/04 , G11C8/12
摘要： A semiconductor memory device includes a memory cell array, a mode setting circuit, a parity data generation unit, and a data error detection and correction unit. The memory cell array has a plurality of first memory banks for storing normal data, and a predetermined number of second memory banks less than the number of the first memory banks for storing parity data according to control of a first flag signal. The mode setting circuit sets the first flag signal and a second flag signal controlling based on whether a separate memory bank is used to store the parity data in the second memory banks. The parity data generation unit receives normal write data during a write operation, generates parity data with respect to the normal write data in response to the second flag signal, and outputs the normal data and the parity data. The data error detection and correction unit receives normal read data and parity read data read from the memory cell array during a read operation, detects errors of the normal read data in response to the second flag signal, corrects the normal read data when the errors are detected, and outputs the corrected read data.
摘要翻译：半导体存储器件包括存储单元阵列，模式设置电路，奇偶校验数据生成单元和数据错误检测和校正单元。存储单元阵列具有用于存储正常数据的多个第一存储体和小于根据第一标志信号的控制存储奇偶校验数据的第一存储体的数量的预定数量的第二存储体。模式设置电路基于是否使用单独的存储体来存储第二存储体中的奇偶校验数据来设置第一标志信号和第二标志信号。奇偶校验数据生成单元在写入操作期间接收正常写入数据，响应于第二标志信号生成相对于正常写入数据的奇偶校验数据，并输出正常数据和奇偶校验数据。数据错误检测和校正单元在读取操作期间接收从存储单元阵列读取的正常读取数据和奇偶校验读取数据，响应于第二标志信号检测正常读取数据的错误，当错误为检测并输出校正的读取数据。

24. 发明授权

US07295464B2 Phase change memory device and method of programming the same 有权
公开(公告)号：US07295464B2
公开(公告)日：2007-11-13
申请号：US11319284
申请日：2005-12-29
申请人： Beak-Hyung Cho , Jong-Soo Seo , Won-Seok Lee
发明人： Beak-Hyung Cho , Jong-Soo Seo , Won-Seok Lee
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C2013/0078 , G11C2013/0092 , G11C2213/72 , G11C2213/79
摘要： A phase change memory device includes a memory cell having a phase change material, a write driver which supplies a step-down set current to the memory cell, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver.

25. 发明授权

US06657498B2 Variable gain low-noise amplifier for a wireless terminal 有权
公开(公告)号：US06657498B2
公开(公告)日：2003-12-02
申请号：US10196136
申请日：2002-07-17
申请人： Joonbae Park , Hoe-Sam Jeong , Seung-Wook Lee , Won-Seok Lee , Kyeongho Lee
发明人： Joonbae Park , Hoe-Sam Jeong , Seung-Wook Lee , Won-Seok Lee , Kyeongho Lee
IPC分类号： H03G310
CPC分类号： H03F1/223 , H03F3/195 , H03F3/72 , H03F2200/294 , H03F2200/378 , H03F2200/391 , H03F2200/451 , H03F2203/7236 , H03G1/0088
摘要： A variable gain, low noise amplifier is described, which is suitable as the input amplifier for a wireless terminal, or as the pre-amplifier stage of a wireless terminal transmitter. The amplifier may achieve variable gain by deploying a network of transistors in a parallel array, each independently selectable by a PMOS switch, and providing the variable resistance for the resonant circuit. Power dissipation can also be mitigated by using a network of driving transistors, each independently selectable by a PMOS switch. The resonant frequency of the amplifier may be made tunable by providing a selection of optional pull-up capacitors.

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