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21. 发明授权

US08390364B2 Internal voltage generation circuit for semiconductor apparatus 失效
标题翻译：半导体装置的内部电压产生电路
公开(公告)号：US08390364B2
公开(公告)日：2013-03-05
申请号：US12843995
申请日：2010-07-27
申请人： Ki Han Kim , Hyun Woo Lee , Won Joo Yun
发明人： Ki Han Kim , Hyun Woo Lee , Won Joo Yun
IPC分类号： G05F1/10
CPC分类号： G11C5/147
摘要： A semiconductor apparatus for generating an internal voltage includes a control code output block and an internal voltage generation block. The control code output block is configured to output a variable code having a code value corresponding to a voltage level of an internal voltage. The internal voltage generation block is configured to compare the variable code to a setting code and controls the voltage level of the internal voltage according to the comparison.
摘要翻译：用于产生内部电压的半导体装置包括控制代码输出块和内部电压产生块。控制代码输出块被配置为输出具有与内部电压的电压电平对应的代码值的可变代码。内部电压生成块被配置为将可变代码与设置代码进行比较，并且根据比较来控制内部电压的电压电平。

22. 发明授权

US07821310B2 DLL circuit having duty cycle correction and method of controlling the same 失效
标题翻译：具有占空比校正的DLL电路及其控制方法
公开(公告)号：US07821310B2
公开(公告)日：2010-10-26
申请号：US12345136
申请日：2008-12-29
申请人： Won Joo Yun , Hyun Woo Lee
发明人： Won Joo Yun , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/1565
摘要： A delay locked loop (DLL) circuit includes a duty cycle correcting unit configured to correct a duty cycle of a reference clock signal in response to a duty cycle correction signal and generate a correction clock signal. A feedback loop of the DLL circuit performs a delay lock operation on the correction clock signal and generates an output clock signal. A first duty cycle detecting unit detects a duty cycle of the correction clock signal and generates a first detection signal and a second duty cycle detecting unit detects a duty cycle of the output clock signal and generates a second detection signal. Finally, a duty cycle control unit generates the duty cycle correction signal in response to the first detection signal and the second detection signal to perform the duty cycle correction.
摘要翻译：延迟锁定环（DLL）电路包括占空比校正单元，其被配置为响应于占空比校正信号来校正参考时钟信号的占空比并产生校正时钟信号。 DLL电路的反馈回路对校正时钟信号执行延迟锁定操作，并产生输出时钟信号。第一占空比检测单元检测校正时钟信号的占空比并产生第一检测信号，第二占空比检测单元检测输出时钟信号的占空比并产生第二检测信号。最后，占空比控制单元响应于第一检测信号和第二检测信号产生占空比校正信号，以执行占空比校正。

23. 发明授权

US07791384B2 Phase synchronization apparatus 有权
标题翻译：相位同步装置
公开(公告)号：US07791384B2
公开(公告)日：2010-09-07
申请号：US12345149
申请日：2008-12-29
申请人： Hyun Woo Lee , Won Joo Yun
发明人： Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03L7/087 , H03L7/0891 , H03L7/0995 , H03L7/18 , H03L2207/06
摘要： A phase synchronization apparatus includes a bias control unit configured to sequentially delay an input clock signal to generate bias control signals having multiple bits, a bias generation unit configured to generate a pull-up bias voltage having a level that corresponds to logical values of the bias control signals, and to generate a pull-down bias voltage in response to a control signal; and a voltage controlled oscillator configured to include a plurality of delay cells respectively having a pull-up terminal and a pull-down terminal to generate an output clock signal in response to the control voltage, wherein the pull-up bias voltage is supplied to the pull-up terminals of the respective delay cells and the pull-down bias voltage is supplied to the pull-down terminals of the respective delay cells.
摘要翻译：相位同步装置包括：偏置控制单元，被配置为顺序地延迟输入时钟信号以产生具有多个位的偏置控制信号;偏置生成单元，被配置为产生具有与偏置的逻辑值对应的电平的上拉偏置电压控制信号，并且响应于控制信号产生下拉偏置电压; 以及压控振荡器，被配置为包括分别具有上拉端子和下拉端子的多个延迟单元，以响应于所述控制电压而产生输出时钟信号，其中所述上拉偏置电压被提供给各个延迟单元的上拉端子和下拉偏压被提供给各个延迟单元的下拉端子。

24. 发明申请

US20090206895A1 PHASE SYNCHRONIZATION APPARATUS 有权
标题翻译：相位同步装置
公开(公告)号：US20090206895A1
公开(公告)日：2009-08-20
申请号：US12333139
申请日：2008-12-11
申请人： Won Joo Yun , Hyun Woo Lee
发明人： Won Joo Yun , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0995 , H03L7/087 , H03L7/093 , H03L7/113
摘要： A phase synchronization apparatus includes an oscillator gain setting member configured to discriminate a frequency by sequentially delaying input clock signal after dividing the input clock signal at a predetermined division ratio and to generate an oscillator gain setting signal by using discriminated frequency information, and a phase locked loop (PLL) circuit configured to oscillates output clock signal having a frequency corresponding to the oscillator gain setting signal in response to the input clock signal.
摘要翻译：相位同步装置包括：振荡器增益设定部件，被配置为通过在以预定分频比对输入时钟信号进行分频之后顺序地延迟输入时钟信号来鉴别频率，并通过使用鉴别频率信息产生振荡器增益设置信号，并且锁相环路（PLL）电路被配置为响应于输入时钟信号而振荡具有与振荡器增益设置信号对应的频率的输出时钟信号。

25. 发明授权

US08138812B2 Device for generating clock in semiconductor integrated circuit 有权
标题翻译：用于在半导体集成电路中产生时钟的装置
公开(公告)号：US08138812B2
公开(公告)日：2012-03-20
申请号：US12646608
申请日：2009-12-23
申请人： Won Joo Yun , Hyun Woo Lee , Ki Han Kim
发明人： Won Joo Yun , Hyun Woo Lee , Ki Han Kim
IPC分类号： G06F1/04
CPC分类号： G06F1/06 , H03L7/0812 , H03L7/0995 , H03L7/16
摘要： Various embodiments of a semiconductor integrated circuit. According to one exemplary embodiment, a semiconductor integrated circuit includes a multi-phase clock generator that is configured to generate a multi-phase internal clock; a first edge combining unit that is configured to generate a first output clock having a first frequency by combining rising edges of clocks included in the internal clock, and transmit the first output clock to a first port; and a second edge combining unit that is configured to generate a second output clock having a second frequency by combining rising edges of clocks included in the internal clock, and transmit the output clock to a second port.
摘要翻译：半导体集成电路的各种实施例。根据一个示例性实施例，半导体集成电路包括被配置为产生多相内部时钟的多相时钟发生器; 第一边缘组合单元，被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第一频率的第一输出时钟，并将所述第一输出时钟发送到第一端口; 以及第二边缘组合单元，其被配置为通过组合包括在所述内部时钟中的时钟的上升沿来产生具有第二频率的第二输出时钟，并将所述输出时钟发送到第二端口。

26. 发明授权

US07928783B2 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US07928783B2
公开(公告)日：2011-04-19
申请号：US12493804
申请日：2009-06-29
申请人： Won Joo Yun , Hyun Woo Lee , Ki Han Kim
发明人： Won Joo Yun , Hyun Woo Lee , Ki Han Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03K5/04 , H03K5/1565
摘要： A semiconductor integrated circuit includes a frequency determining unit configured to determine an operational speed of the semiconductor integrated circuit and to generate a frequency region signal; a duty cycle control unit configured to detect a duty cycle of a DLL clock and to generate a duty cycle control signal; a duty cycle correcting unit configured to generate a corrected clock by correcting a duty cycle of an input clock in response to the frequency region signal and in response to the duty cycle control signal; and a DLL (Delay Locked Loop) circuit configured to generate the DLL clock by controlling a phase of the corrected clock.
摘要翻译：半导体集成电路包括：频率确定单元，被配置为确定半导体集成电路的操作速度并产生频率区域信号; 占空比控制单元，被配置为检测DLL时钟的占空比并产生占空比控制信号; 占空比校正单元，被配置为通过响应于频域信号校正输入时钟的占空比并响应于占空比控制信号来产生校正时钟; 以及被配置为通过控制校正时钟的相位来产生DLL时钟的DLL（延迟锁定环路）。

27. 发明授权

US07830186B2 Delay locked loop apparatus 有权
标题翻译：延迟锁定环路设备
公开(公告)号：US07830186B2
公开(公告)日：2010-11-09
申请号：US11677619
申请日：2007-02-22
申请人： Won Joo Yun , Hyun Woo Lee
发明人： Won Joo Yun , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0818 , H03L7/087
摘要： A delay locked loop (DLL) apparatus includes a first delay unit converting a reference clock into a rising clock. A second delay unit converts the reference clock into a falling clock, and a replica delay unit replica-delays the rising clock. A first phase detector compares the phases of the reference clock and the delayed rising clock to output a first detection signal corresponding to the compared phases. A controller synchronizes the rising edge of the rising clock with the rising edge of the reference clock according to the first detection signal of the first phase detector. A second phase detector compares the phases of the synchronized rising clock and the synchronization clock to output a second detection signal corresponding to the compared phases. The DLL apparatus compensates for a skew between an external clock and data and between external and internal clocks by employing a single replica delay unit.
摘要翻译：延迟锁定环（DLL）装置包括将参考时钟转换为上升时钟的第一延迟单元。第二延迟单元将参考时钟转换为下降时钟，复制延迟单元复制延迟上升时钟。第一相位检测器比较参考时钟和延迟上升时钟的相位，以输出对应于比较相位的第一检测信号。控制器根据第一相位检测器的第一检测信号，将上升时钟的上升沿与参考时钟的上升沿同步。第二相位检测器比较同步上升时钟和同步时钟的相位，以输出对应于比较相位的第二检测信号。 DLL装置通过采用单个复制延迟单元来补偿外部时钟和数据之间以及外部和内部时钟之间的偏差。

28. 发明申请

US20090179675A1 DLL CIRCUIT AND METHOD OF CONTROLLING THE SAME 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US20090179675A1
公开(公告)日：2009-07-16
申请号：US12173728
申请日：2008-07-15
申请人： Hyun Woo Lee , Won Joo Yun
发明人： Hyun Woo Lee , Won Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/0814
摘要： A delay locked loop (DLL) circuit includes a clock signal dividing unit that can divide a reference clock signal by a predetermined division ratio and generate a division clock signal, a feedback loop that can perform a delay locked operation on the division clock signal and generate a delay clock signal, a half period delay unit that can delay the delay clock signal by a half period of the reference clock signal and generate a half period delay clock signal, and an operation unit that can combine the delay clock signal and the half period delay clock signal and generate an output clock signal.
摘要翻译：延迟锁定环（DLL）电路包括时钟信号划分单元，其可以将预定分频比除以参考时钟信号并产生除法时钟信号，该反馈环可以对分频时钟信号执行延迟锁定操作并产生延迟时钟信号，半周期延迟单元，其可以将所述延迟时钟信号延迟所述基准时钟信号的半周期，并生成半周期延迟时钟信号;以及操作单元，其可以将所述延迟时钟信号和所述半周期延迟时钟信号并产生输出时钟信号。

29. 发明申请

US20080111600A1 Apparatus and method of setting operation mode in DLL circuit 失效
标题翻译：在DLL电路中设置操作模式的装置和方法
公开(公告)号：US20080111600A1
公开(公告)日：2008-05-15
申请号：US11822357
申请日：2007-07-05
申请人： Won Joo Yun , Hyun Woo Lee , Nak Kyu Park
发明人： Won Joo Yun , Hyun Woo Lee , Nak Kyu Park
IPC分类号： H03L7/06
CPC分类号： H03L7/095 , H03L7/0812
摘要： An apparatus for setting an operation mode in a DLL circuit generates a locking completion signal according to a level of a phase comparing signal obtained by comparing phases of a reference clock and a feedback clock. During three or more cycles of a pulse signal, it is determined whether a logic value of levels of the phase comparing signal is a specific combination, and the locking completion signal is selectively enabled.
摘要翻译：用于设置DLL电路中的操作模式的装置根据通过比较参考时钟和反馈时钟的相位而获得的相位比较信号的电平来产生锁定完成信号。在脉冲信号的三个或更多周期期间，确定相位比较信号的电平的逻辑值是否是特定组合，并且锁定完成信号被选择性地使能。

30. 发明授权

US08237478B2 DLL circuit having activation points 有权
标题翻译： DLL电路具有激活点
公开(公告)号：US08237478B2
公开(公告)日：2012-08-07
申请号：US13237083
申请日：2011-09-20
申请人： Won Joo Yun , Hyun Woo Lee
发明人： Won Joo Yun , Hyun Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0818
摘要： A delay locked loop (DLL) circuit includes a delay line configured to generate a delay clock signal by delaying a reference clock signal in response to a delay control signal, the delay line having two or more initial activation points, wherein the initial activation points are selected according to an initial value of the delay control signal; a delay compensating unit configured to generate a feedback clock signal by delaying the delay clock signal for a predetermined time; a phase detecting unit configured to generate a phase detection signal by comparing a phase of the reference clock signal to a phase of the feedback clock signal; and a delay control unit configured to generate the delay control signal in response to the phase detection signal.
摘要翻译：延迟锁定环路（DLL）电路包括延迟线，其被配置为通过响应于延迟控制信号延迟参考时钟信号来产生延迟时钟信号，该延迟线具有两个或多个初始激活点，其中初始激活点是根据延迟控制信号的初始值选择; 延迟补偿单元，被配置为通过将所述延迟时钟信号延迟预定时间来产生反馈时钟信号; 相位检测单元，被配置为通过将参考时钟信号的相位与反馈时钟信号的相位进行比较来产生相位检测信号; 以及延迟控制单元，被配置为响应于相位检测信号而产生延迟控制信号。

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