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21. 发明授权

US07733997B2 Signal adjustment receiver circuitry 有权
标题翻译：信号调节接收器电路
公开(公告)号：US07733997B2
公开(公告)日：2010-06-08
申请号：US11486581
申请日：2006-07-14
申请人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Simardeep Maangat
发明人： Tin H. Lai , Wilson Wong , Sergey Shumarayev , Simardeep Maangat
IPC分类号： H04B1/10
CPC分类号： H04B7/005 , H04L25/03006 , H04L25/061
摘要： Systems and methods for adjusting a signal received from a communication path are disclosed. A receiver can receive a signal from a communication path which attenuates at least some frequency components of the signal. The receiver can include an equalization block that adjusts at least some of the frequency content of the received signal, a signal normalization block that provides a normalized signal amplitude and/or a normalized edge slope, and a control block. In one embodiment, the control block controls frequency adjustment in the equalization block for high frequencies. For low frequency adjustment, user-programmable parameters control the normalized signal amplitude in the signal normalization block and the low frequency adjustment in the equalization block.
摘要翻译：公开了一种用于调整从通信路径接收的信号的系统和方法。接收机可以接收来自衰减信号的至少一些频率分量的通信路径的信号。接收机可以包括调整接收信号的频率内容中的至少一些的均衡块，提供归一化信号幅度和/或归一化边沿斜率的信号归一化块以及控制块。在一个实施例中，控制块控制用于高频的均衡块中的频率调整。对于低频调整，用户可编程参数控制信号归一化块中的归一化信号幅度和均衡块中的低频调整。

22. 发明申请

US20080069276A1 Digital adaptation circuitry and methods for programmable logic devices 有权
标题翻译：用于可编程逻辑器件的数字适配电路和方法
公开(公告)号：US20080069276A1
公开(公告)日：2008-03-20
申请号：US11522284
申请日：2006-09-14
申请人： Wilson Wong , Doris Po Ching Chan , Simardeep Maangat , Sergey Shumarayev , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
发明人： Wilson Wong , Doris Po Ching Chan , Simardeep Maangat , Sergey Shumarayev , Tim Tri Hoang , Tin H. Lai , Thungoc M. Tran
IPC分类号： H04B1/10
CPC分类号： H04L25/03885
摘要： Equalization of an incoming data signal can be controlled by sampling that signal at times when data values in that signal should be stable (“data samples”) and when that signal should be in transition between successive data values that are different (“transition samples”). A transition sample that has been taken between two successive differently valued data samples is compared to a reference value (which can be one of those two data samples). The result of this comparison can be used as part of a determination as to whether to increase or decrease equalization of the incoming data signal.
摘要翻译：输入数据信号的均衡可以通过在该信号中的数据值应当稳定（“数据采样”）的时候对该信号进行采样来控制，并且当该信号应该在不同的连续数据值（“转换样本” ）。将已经在两个连续的不同值数据样本之间拍摄的转换样本与参考值（可以是这两个数据样本之一）进行比较。该比较的结果可以用作关于是否增加或减少输入数据信号的均衡的确定的一部分。

23. 发明授权

US08787352B2 Heterogeneous transceiver architecture for wide range programmability of programmable logic devices 有权
标题翻译：异构收发器架构，用于可编程逻辑器件的广泛可编程性
公开(公告)号：US08787352B2
公开(公告)日：2014-07-22
申请号：US13103132
申请日：2011-05-09
申请人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
发明人： Sergey Shumarayev , Bill W. Bereza , Chong H. Lee , Rakesh H. Patel , Wilson Wong
IPC分类号： H04L12/28 , H04L5/14 , H04L27/00
CPC分类号： H04L5/14 , H03K19/17744 , H04L27/00
摘要： High-speed serial data transceiver circuitry on a programmable logic device (“PLD”) includes some channels that are able to operate at data rates up to a first, relatively low maximum data rate, and other channels that are able to operate at data rates up to a second, relatively high maximum data rate. The relatively low-speed channels are served by relatively low-speed phase locked loop (“PLL”) circuitry, and have other circuit components that are typically needed for handling data that is transmitted at relatively low data rates. The relatively high-speed channels are served by relatively high-speed PLLs, and have other circuit components that are typically needed for handling data that is transmitted at relatively high data rates.
摘要翻译：可编程逻辑器件（“PLD”）上的高速串行数据收发器电路包括一些能够以高达第一，相对较低的最大数据速率的数据速率工作的通道，以及能够以数据速率操作的其他通道达到第二个相对较高的最大数据速率。相对低速的通道由相对低速的锁相环（“PLL”）电路服务，并且具有通常用于处理以相对低的数据速率发送的数据所需的其他电路组件。相对高速的信道由相对高速的PLL服务，并且具有通常用于处理以相对高的数据速率传输的数据所需的其他电路部件。

24. 发明授权

US07728674B1 Voltage-controlled oscillator methods and apparatus 失效
标题翻译：压控振荡器的方法和装置
公开(公告)号：US07728674B1
公开(公告)日：2010-06-01
申请号：US11437558
申请日：2006-05-19
申请人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
发明人： Tim Tri Hoang , Wilson Wong , Kazi Asaduzzaman , Simardeep Maangat , Sergey Shumarayev , Rakesh H. Patel
IPC分类号： H03L7/00
CPC分类号： H03L7/0995 , H03K3/0322 , H03K3/35613 , H03K2005/00228 , H03K2005/00234
摘要： Methods and apparatus are provided for generating a clock signal with relatively high bandwidth and relatively low phase noise. A circuit of the invention can include a pair of transistors serially coupled between a signal of relatively high voltage and a source of relatively low voltage, where a voltage of the signal of relatively high voltage can vary according to a voltage of a variable control signal. A gate of one of the pair of transistors can be coupled to an input clock signal, and an output node between the pair of transistors can be coupled to an output clock signal. The circuit can also include a third transistor, whose drain and source are coupled to the output clock signal, and whose gate can be coupled to a gear input signal. This circuit can advantageously operate under at least two different gears, each with different bandwidth and phase noise characteristics.
摘要翻译：提供了用于产生具有相对较高带宽和相对较低相位噪声的时钟信号的方法和装置。本发明的电路可以包括串联耦合在相对高电压的信号和相对低电压的源之间的一对晶体管，其中相对高电压的信号的电压可以根据可变控制信号的电压而变化。一对晶体管中的一个的栅极可以耦合到输入时钟信号，并且该对晶体管之间的输出节点可以耦合到输出时钟信号。电路还可以包括第三晶体管，其漏极和源极耦合到输出时钟信号，并且其栅极可以耦合到齿轮输入信号。该电路可以有利地在至少两个不同的齿轮下运行，每个齿轮具有不同的带宽和相位噪声特性。

25. 发明申请

US20090122939A1 Wide range and dynamically reconfigurable clock data recovery architecture 有权
标题翻译：宽范围和动态可重构的时钟数据恢复架构
公开(公告)号：US20090122939A1
公开(公告)日：2009-05-14
申请号：US11329197
申请日：2006-01-09
申请人： Tim Tri Hoang , Sergey Shumarayev , Wilson Wong , Rakesh H. Patel
发明人： Tim Tri Hoang , Sergey Shumarayev , Wilson Wong , Rakesh H. Patel
IPC分类号： H04L7/00
CPC分类号： H03L7/087 , H03K19/17732 , H03K19/17744 , H03L7/10 , H04L7/0004 , H04L7/033
摘要： Wide range and dynamically reprogrammable CDR architecture recovers an embedded clock signal from serial input data with a wide range of operating frequencies. In order to support a wide range of data rates, the CDR architecture includes multiple operating parameters. These parameters include various pre/post divider settings, charge pump currents, loop-filter and bandwidth selections, and VCO gears. The parameters may be dynamically reprogrammed without powering down the circuitry or PLD. This allows the CDR circuitry to switch between various standards and protocols on-the-fly.
摘要翻译：宽范围和动态可重新编程的CDR架构从具有广泛工作频率的串行输入数据中恢复嵌入式时钟信号。为了支持广泛的数据速率，CDR架构包括多个操作参数。这些参数包括各种前/后分频器设置，电荷泵电流，环路滤波器和带宽选择以及VCO齿轮。可以在不关闭电路或PLD的情况下动态重新编程参数。这允许CDR电路在各种标准和协议之间进行即时切换。

26. 发明授权

US07368968B1 Signal offset cancellation 有权
标题翻译：信号偏移消除
公开(公告)号：US07368968B1
公开(公告)日：2008-05-06
申请号：US11323372
申请日：2005-12-29
申请人： Tin H. Lai , Wilson Wong
发明人： Tin H. Lai , Wilson Wong
IPC分类号： H03F3/45 , H03L5/00
CPC分类号： H03F3/45475 , H03F3/45192 , H03F3/45744 , H03F3/45968 , H03F2200/321 , H03F2203/45212 , H03F2203/45646 , H03F2203/45678 , H03F2203/45681 , H03F2203/45726
摘要： Techniques and circuitry are provided for programmably controlling signal offsets in integrated circuitry. In one embodiment, an integrated circuit includes a signal offset cancellation circuit that is programmably selected to control the offset of signals on either one input/output or another input/output of an amplifier circuit. In one embodiment, a logic circuit is used to selectively couple a bank of current sources to one input/output or another input/output of a differential amplifier through a switching circuit. The bank of current sources may employed to control the signal offset on either input/output, or may be decoupled from all of the inputs/outputs when signal offset cancellation is not required.
摘要翻译：提供技术和电路用于可编程地控制集成电路中的信号偏移。在一个实施例中，集成电路包括可编程地选择以控制放大器电路的一个输入/输出或另一个输入/输出上的信号的偏移的信号偏移消除电路。在一个实施例中，逻辑电路用于通过开关电路将一组电流源选择性地耦合到差分放大器的一个输入/输出或另一个输入/输出。可以采用电流源的组来控制输入/输出上的信号偏移，或者当不需要信号偏移消除时可以与所有的输入/输出去耦。

27. 发明授权

US07710180B1 Signal offset cancellation 失效
标题翻译：信号偏移消除
公开(公告)号：US07710180B1
公开(公告)日：2010-05-04
申请号：US12116059
申请日：2008-05-06
申请人： Tin H. Lai , Wilson Wong
发明人： Tin H. Lai , Wilson Wong
IPC分类号： H03F3/45 , H03L5/00
CPC分类号： H03F3/45475 , H03F3/45192 , H03F3/45744 , H03F3/45968 , H03F2200/321 , H03F2203/45212 , H03F2203/45646 , H03F2203/45678 , H03F2203/45681 , H03F2203/45726
摘要： Techniques and circuitry are provided for programmably controlling signal offsets in integrated circuitry. In one embodiment, an integrated circuit includes a signal offset cancellation circuit that is programmably selected to control the offset of signals on either one input/output or another input/output of an amplifier circuit. In one embodiment, a logic circuit is used to selectively couple a bank of current sources to one input/output or another input/output of a differential amplifier through a switching circuit. The bank of current sources may employed to control the signal offset on either input/output, or may be decoupled from all of the inputs/outputs when signal offset cancellation is not required.
摘要翻译：提供技术和电路用于可编程地控制集成电路中的信号偏移。在一个实施例中，集成电路包括可编程地选择以控制放大器电路的一个输入/输出或另一个输入/输出上的信号的偏移的信号偏移消除电路。在一个实施例中，逻辑电路用于通过开关电路将一组电流源选择性地耦合到差分放大器的一个输入/输出或另一个输入/输出。可以采用电流源的组来控制输入/输出上的信号偏移，或者当不需要信号偏移消除时可以与所有的输入/输出去耦。

28. 发明授权

US07336211B1 Resistance compensated DAC ladder 有权
标题翻译：电阻补偿DAC梯形图
公开(公告)号：US07336211B1
公开(公告)日：2008-02-26
申请号：US11336443
申请日：2006-01-20
申请人： Tin H. Lai , Wilson Wong
发明人： Tin H. Lai , Wilson Wong
IPC分类号： H03M1/78
CPC分类号： H03M1/06 , H03M1/785
摘要： Circuits, methods, and apparatus for inhibiting non-monotonic output voltage behavior in an R-2R ladder digital to analog converter (DAC). Resistance values of selected resistors of the R-2R ladder are designed to compensate for finite resistances of switches and for variances within the resistances of the resistors and of the switches. The compensating resistance values dampen or eliminate the non-monotonic behavior in the DAC.
摘要翻译：用于抑制R-2R梯形数模转换器（DAC）中的非单调输出电压特性的电路，方法和装置。 R-2R梯形电阻器的电阻值被设计为补偿开关的有限电阻和电阻器和开关电阻之间的差异。补偿电阻值抑制或消除DAC中的非单调行为。

29. 发明授权

US07898313B1 Signal offset cancellation 有权
标题翻译：信号偏移消除
公开(公告)号：US07898313B1
公开(公告)日：2011-03-01
申请号：US12723450
申请日：2010-03-12
申请人： Tin H. Lai , Wilson Wong
发明人： Tin H. Lai , Wilson Wong
IPC分类号： H03F3/45 , H03L5/00
CPC分类号： H03F3/45475 , H03F3/45192 , H03F3/45744 , H03F3/45968 , H03F2200/321 , H03F2203/45212 , H03F2203/45646 , H03F2203/45678 , H03F2203/45681 , H03F2203/45726
摘要： Techniques and circuitry are provided for programmably controlling signal offsets in integrated circuitry. In one embodiment, an integrated circuit includes a signal offset cancellation circuit that is programmably selected to control the offset of signals on either one input/output or another input/output of an amplifier circuit. In one embodiment, a logic circuit is used to selectively couple a bank of current sources to one input/output or another input/output of a differential amplifier through a switching circuit. The bank of current sources may employed to control the signal offset on either input/output, or may be decoupled from all of the inputs/outputs when signal offset cancellation is not required.
摘要翻译：提供技术和电路用于可编程地控制集成电路中的信号偏移。在一个实施例中，集成电路包括可编程地选择以控制放大器电路的一个输入/输出或另一个输入/输出上的信号的偏移的信号偏移消除电路。在一个实施例中，逻辑电路用于通过开关电路将一组电流源选择性地耦合到差分放大器的一个输入/输出或另一个输入/输出。可以采用电流源的组来控制输入/输出上的信号偏移，或者当不需要信号偏移消除时可以与所有的输入/输出去耦。

30. 发明授权

US07782935B1 Half-rate DFE with duplicate path for high data-rate operation 有权
标题翻译：具有高数据速率操作的重复路径的半速率DFE
公开(公告)号：US07782935B1
公开(公告)日：2010-08-24
申请号：US11514490
申请日：2006-08-31
申请人： Wilson Wong , Sergey Yuryevich Shumarayev , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
发明人： Wilson Wong , Sergey Yuryevich Shumarayev , Simardeep Maangat , Thungoc M. Tran , Tim Tri Hoang , Tin H. Lai
IPC分类号： H03H7/30
CPC分类号： H03H11/26 , H04L25/03878 , H04L2025/0349
摘要： Methods and circuits are presented for providing equalization, including decision feedback equalization (DFE), to high data-rate signals. Half-rate delay-chain circuitry produces delayed samples of an input signal using two or more delay-chain circuits operating at a fraction of the input signal data-rate. Two delay-chain circuits operating at one-half the input signal data-rate may be used. More generally, n delay-chain circuits operating at 1/n the input signal data-rate may be used. Multiplexer circuitry combines the outputs of the delay-chain circuits to produce an output signal including samples of the input signal at the input signal data-rate. Duplicate path DFE circuitry includes two paths used to provide DFE equalization while reducing the load of the DFE circuitry on the circuitry that precedes it. A first path produces delayed samples of a DFE signal, while a second path produces the DFE output signal from the delayed samples.
摘要翻译：提出了用于向高数据速率信号提供均衡的方法和电路，包括判决反馈均衡（DFE）。半速率延迟链电路使用以输入信号数据速率的一小部分工作的两个或多个延迟链电路产生输入信号的延迟采样。可以使用以输入信号数据速率的一半工作的两个延迟链电路。更一般地，可以使用以1 / n输入信号数据速率工作的n个延迟链电路。多路复用器电路组合延迟链电路的输出以产生包括输入信号数据速率的输入信号样本的输出信号。重复路径DFE电路包括用于提供DFE均衡的两个路径，同时减少DFE电路之前的电路上的DFE电路的负载。第一路径产生DFE信号的延迟采样，而第二路径产生来自延迟采样的DFE输出信号。

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