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21. 发明授权

US08539485B2 Polling using reservation mechanism 有权
标题翻译：轮询使用预约机制
公开(公告)号：US08539485B2
公开(公告)日：2013-09-17
申请号：US11942813
申请日：2007-11-20
申请人： Michael D. Snyder , Gary L. Whisenhunt
发明人： Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/46 , G06F12/00 , G06F13/00 , G06F3/00 , G06F13/22
CPC分类号： G06F9/3009 , G06F9/3004 , G06F9/30087 , G06F9/3834 , G06F9/3851
摘要： A first thread enters a polling loop to wait for a signal from a second thread before processing instructions dependent on the polling loop. When entering the polling loop, the first thread sets a reservation for a predetermined memory address. The first thread then executes a reservation-based instruction that can change the execution state of the first thread. Reservation circuitry of the processing device that was executing the first thread monitors the reservation. In the event that the reservation cleared, such as by the second thread modifying data at the predetermined memory address, the first thread is reinstated to its prior execution state. By using a hardware reservation mechanism to monitor for clearing of a set reservation, repeated memory accesses to the memory address by the first thread can be minimized or avoided while in the polling loop and other threads can be allowed to execute at the processing device with reduced interference from the waiting thread.
摘要翻译：在处理根据轮询循环的指令之前，第一线程进入轮询循环以等待来自第二线程的信号。当进入轮询循环时，第一线程为预定的存储器地址设置预留。然后，第一线程执行可以改变第一线程的执行状态的基于预约的指令。正在执行第一个线程的处理设备的预留电路监视预留。在保留清除的情况下，例如通过在预定存储器地址处修改数据的第二线程，第一线程被恢复到其先前的执行状态。通过使用硬件预留机制来监视设定的预约的清除，可以最小化或避免第一线程对存储器地址的重复存储器访问，而在轮询循环中，可以允许其他线程在处理设备处执行减少来自等待线程的干扰。

22. 发明授权

US08117618B2 Forward progress mechanism for a multithreaded processor 有权
标题翻译：多线程处理器的前进进程机制
公开(公告)号：US08117618B2
公开(公告)日：2012-02-14
申请号：US11871626
申请日：2007-10-12
申请人： David C. Holloway , Trinh H. Nguyen , Michael D. Snyder , Gary L. Whisenhunt
发明人： David C. Holloway , Trinh H. Nguyen , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.
摘要翻译：处理装置包括：存储部件，被配置为存储与多个线程的相应线程相关联的指令;以及执行单元，被配置为获取并执行指令。处理装置还包括周期定时器，其包括输出，以响应于周期定时器基于时钟信号达到预定值的计数值来提供指示符。处理装置还包括多个线程正向进行计数器组件，每个组件被配置成在正在执行对应的线程的指令的同时基于前进进度指示符的发生来调整相应的执行计数器值。所述处理装置还包括线程选择模块，所述线程选择模块被配置为基于所述周期定时器的状态和所述多个线程前进进程计数器组件中的每一个的状态来选择所述多个线程的线程以由所述执行单元执行。

23. 发明申请

US20080183943A1 METHOD AND SYSTEM FOR DATA TRANSFERS ACROSS DIFFERENT ADDRESS SPACES 有权
标题翻译：用于不同地址空间的数据传输的方法和系统
公开(公告)号：US20080183943A1
公开(公告)日：2008-07-31
申请号：US11669804
申请日：2007-01-31
申请人： Becky G. Bruce , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
发明人： Becky G. Bruce , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
IPC分类号： G06F12/02
CPC分类号： G06F12/0284
摘要： A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configured to store a third value associated with a third address space. The processing device further includes a memory management unit, which includes a first input configured to receive a first address value associated with a data transfer operation, a second input configured to receive an identifier associated with the data transfer operation, and an address space select module configured to identify a select value from the first value, the second value and the third value based on the identifier. The memory management module further includes an address modification module configured to generate a second address value based on the first address value and the select value.
摘要翻译：处理设备包括被配置为存储与第一地址空间相关联的第一值的第一存储位置，被配置为存储与第二地址空间相关联的第二值的第二存储位置以及被配置为存储与第二地址空间相关联的第三值的第三存储位置具有第三个地址空间。处理装置还包括存储器管理单元，其包括被配置为接收与数据传送操作相关联的第一地址值的第一输入，被配置为接收与数据传送操作相关联的标识符的第二输入以及地址空间选择模块被配置为基于所述标识符从所述第一值，所述第二值和所述第三值中识别选择值。存储器管理模块还包括地址修改模块，该地址修改模块被配置为基于第一地址值和选择值生成第二地址值。

24. 发明授权

US07702881B2 Method and system for data transfers across different address spaces 有权
标题翻译：跨不同地址空间进行数据传输的方法和系统
公开(公告)号：US07702881B2
公开(公告)日：2010-04-20
申请号：US11669804
申请日：2007-01-31
申请人： Becky G. Bruce , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
发明人： Becky G. Bruce , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
IPC分类号： G06F12/00
CPC分类号： G06F12/0284
摘要： A processing device includes a first storage location configured to store a first value associated with a first address space, a second storage location configured to store a second value associated with a second address space, and a third storage location configured to store a third value associated with a third address space. The processing device further includes a memory management unit, which includes a first input configured to receive a first address value associated with a data transfer operation, a second input configured to receive an identifier associated with the data transfer operation, and an address space select module configured to identify a select value from the first value, the second value and the third value based on the identifier. The memory management module further includes an address modification module configured to generate a second address value based on the first address value and the select value.
摘要翻译：处理设备包括被配置为存储与第一地址空间相关联的第一值的第一存储位置，被配置为存储与第二地址空间相关联的第二值的第二存储位置以及被配置为存储与第二地址空间相关联的第三值的第三存储位置具有第三个地址空间。处理装置还包括存储器管理单元，其包括被配置为接收与数据传送操作相关联的第一地址值的第一输入，被配置为接收与数据传送操作相关联的标识符的第二输入以及地址空间选择模块被配置为基于所述标识符从所述第一值，所述第二值和所述第三值中识别选择值。存储器管理模块还包括地址修改模块，该地址修改模块被配置为基于第一地址值和选择值生成第二地址值。

25. 发明申请

US20100095039A1 INTERRUPT ACKNOWLEDGMENT IN A DATA PROCESSING SYSTEM 有权
标题翻译：数据处理系统中的中断确认
公开(公告)号：US20100095039A1
公开(公告)日：2010-04-15
申请号：US12250682
申请日：2008-10-14
申请人： Bryan D. Marietta , Michael D. Snyder , Gary L. Whisenhunt , Daniel L. Bouvier
发明人： Bryan D. Marietta , Michael D. Snyder , Gary L. Whisenhunt , Daniel L. Bouvier
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： A data processing system has an interrupt controller which provides an interrupt request along with a corresponding interrupt identifier and a corresponding interrupt vector to a processor. If the processor accepts the interrupt, the processor returns the same interrupt identifier value by way of interrupt identifier, along with interrupt acknowledge, to the interrupt controller. An interrupt taken/not taken indicator may also be provided. The communications interface used to coordinate interrupt processing between the interrupt controller and the processor may be asynchronous.
摘要翻译：数据处理系统具有中断控制器，其向处理器提供中断请求以及对应的中断标识符和相应的中断向量。如果处理器接受中断，处理器将通过中断标识符和中断确认返回相同的中断标识符值给中断控制器。还可以提供中断/未采取的指示符。用于协调中断控制器和处理器之间的中断处理的通信接口可能是异步的。

26. 发明申请

US20090100432A1 FORWARD PROGRESS MECHANISM FOR A MULTITHREADED PROCESSOR 有权
标题翻译：多元化加工商的前进进展机制
公开(公告)号：US20090100432A1
公开(公告)日：2009-04-16
申请号：US11871626
申请日：2007-10-12
申请人： David C. Holloway , Trinh H. Nguyen , Michael D. Snyder , Gary L. Whisenhunt
发明人： David C. Holloway , Trinh H. Nguyen , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/46
CPC分类号： G06F9/4881
摘要： A processing device includes a storage component configured to store instructions associated with a corresponding thread of a plurality of threads, and an execution unit configured to fetch and execute instructions. The processing device further includes a period timer comprising an output to provide an indicator in response to a count value of the period timer reaching a predetermined value based on a clock signal. The processing device additionally includes a plurality of thread forward-progress counter components, each configured to adjust a corresponding execution counter value based on an occurrence of a forward-progress indicator while instructions of a corresponding thread are being executed. The processing device further includes a thread select module configured to select threads of the plurality of threads for execution by the execution unit based a state of the period timer and a state of each of the plurality of thread forward-progress counter components.
摘要翻译：处理装置包括：存储部件，被配置为存储与多个线程的相应线程相关联的指令;以及执行单元，被配置为获取并执行指令。处理装置还包括周期定时器，其包括输出，以响应于周期定时器基于时钟信号达到预定值的计数值来提供指示符。处理装置还包括多个线程正向进行计数器组件，每个组件被配置成在正在执行对应的线程的指令的同时基于前进进度指示符的发生来调整相应的执行计数器值。所述处理装置还包括线程选择模块，所述线程选择模块被配置为基于所述周期定时器的状态和所述多个线程前进进程计数器组件中的每一个的状态来选择所述多个线程的线程以由所述执行单元执行。

27. 发明申请

US20090037666A1 CACHE LOCKING DEVICE AND METHODS THEREOF 有权
标题翻译：缓存设备及其方法
公开(公告)号：US20090037666A1
公开(公告)日：2009-02-05
申请号：US11832797
申请日：2007-08-02
申请人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
发明人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/0846 , G06F12/0891
摘要： A method and device for locking a cache line of a cache is disclosed. The method includes automatically changing a state of a cache line from a valid locked state to an invalid locked state in response to receiving an indication that a memory location external to the cache and corresponding to the cache line is associated with an access request by a processor or other data access module. Thus, the locked state of a cache line is maintained even after data in the locked cache line is invalidated. By maintaining the invalid locked state, the cache line is not available for reallocation by the cache. This allows locked cache lines that become invalidated to remain locked without additional software overhead to periodically determine whether the lock has been lost due to invalidation of the cache line.
摘要翻译：公开了一种用于锁定高速缓存的高速缓存行的方法和设备。该方法包括响应于接收到高速缓存行外部的对应于高速缓存行的存储器位置与处理器的访问请求相关联的指示，自动将高速缓存行的状态从有效锁定状态改变为无效锁定状态或其他数据访问模块。因此，即使在锁定的高速缓存行中的数据无效之后，也保持高速缓存行的锁定状态。通过保持无效的锁定状态，高速缓存行不可用于高速缓存的重新分配。这允许被锁定的高速缓存行保持锁定，而不需要额外的软件开销来定期确定锁是否由于高速缓存行的无效而丢失。

28. 发明申请

US20080282251A1 THREAD DE-EMPHASIS INSTRUCTION FOR MULTITHREADED PROCESSOR 有权
标题翻译：螺纹加工器的螺纹切割指令
公开(公告)号：US20080282251A1
公开(公告)日：2008-11-13
申请号：US11746998
申请日：2007-05-10
申请人： Klas M. Bruce , Sergio Schuler , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
发明人： Klas M. Bruce , Sergio Schuler , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F9/46 , G06F9/50
CPC分类号： G06F9/485 , G06F9/3009 , G06F9/3013 , G06F9/3824 , G06F9/3834 , G06F9/3851
摘要： A technique for scheduling execution of threads at a processor is disclosed. The technique includes executing a thread de-emphasis instruction of a thread that de-emphasizes the thread until the number of pending memory transactions, such as cache misses, associated with the thread are at or below a threshold. While the thread is de-emphasized, other threads at the processor that have a higher priority can be executed or assigned system resources. Accordingly, the likelihood of a stall in the processor is reduced.
摘要翻译：公开了一种用于在处理器处调度线程执行的技术。该技术包括执行线程的线程去加重指令，该线程去加强线程，直到与线程相关联的等待存储器事务（例如高速缓存未命中）的数量处于或低于阈值。当该线程被去加强时，处理器中具有较高优先级的其他线程可以执行或分配系统资源。因此，处理器中失速的可能性降低。

29. 发明授权

US07827360B2 Cache locking device and methods thereof 有权
标题翻译：缓存锁定装置及其方法
公开(公告)号：US07827360B2
公开(公告)日：2010-11-02
申请号：US11832797
申请日：2007-08-02
申请人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
发明人： Syed R. Rahman , David F. Greenberg , Kathryn C. Stacer , Klas M. Bruce , Matt B. Smittle , Michael D. Snyder , Gary L. Whisenhunt
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0846 , G06F12/0891
摘要： A method and device for locking a cache line of a cache is disclosed. The method includes automatically changing a state of a cache line from a valid locked state to an invalid locked state in response to receiving an indication that a memory location external to the cache and corresponding to the cache line is associated with an access request by a processor or other data access module. Thus, the locked state of a cache line is maintained even after data in the locked cache line is invalidated. By maintaining the invalid locked state, the cache line is not available for reallocation by the cache. This allows locked cache lines that become invalidated to remain locked without additional software overhead to periodically determine whether the lock has been lost due to invalidation of the cache line.
摘要翻译：公开了一种用于锁定高速缓存的高速缓存行的方法和设备。该方法包括响应于接收到高速缓存行外部的对应于高速缓存行的存储器位置与处理器的访问请求相关联的指示，自动将高速缓存行的状态从有效锁定状态改变为无效锁定状态或其他数据访问模块。因此，即使在锁定的高速缓存行中的数据无效之后，也保持高速缓存行的锁定状态。通过保持无效的锁定状态，高速缓存行不可用于高速缓存的重新分配。这允许被锁定的高速缓存行保持锁定，而不需要额外的软件开销来定期确定锁是否由于高速缓存行的无效而丢失。

30. 发明申请

US20080222389A1 INTERPROCESSOR MESSAGE TRANSMISSION VIA COHERENCY-BASED INTERCONNECT 有权
标题翻译：通过基于互连的互联互通信息传输
公开(公告)号：US20080222389A1
公开(公告)日：2008-09-11
申请号：US11682867
申请日：2007-03-06
申请人： Becky G. Bruce , Sanjay R. Deshpande , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
发明人： Becky G. Bruce , Sanjay R. Deshpande , Michael D. Snyder , Gary L. Whisenhunt , Kumar Gala
IPC分类号： G06F15/76
CPC分类号： G06F15/16 , G06F9/546 , G06F12/0833
摘要： A method includes communicating a first message between processors of a multiprocessor system via a coherency interconnect, whereby the first message includes coherency information. The method further includes communicating a second message between processors of the multiprocessor system via the coherency interconnect, whereby the second message includes interprocessor message information. A system includes a coherency interconnect and a processor. The processor includes an interface configured to receive messages from the coherency interconnect, each message including one of coherency information or interprocessor message information. The processor further includes a coherency management module configured to process coherency information obtained from at least one of the messages and an interrupt controller configured to generate an interrupt based on interprocessor message information obtained from at least one of the messages.
摘要翻译：一种方法包括经由一致性互连在多处理器系统的处理器之间传送第一消息，由此第一消息包括一致性信息。该方法还包括经由一致性互连在多处理器系统的处理器之间传送第二消息，由此第二消息包括处理器间消息信息。系统包括一致性互连和处理器。处理器包括被配置为从一致性互连接收消息的接口，每个消息包括一致性信息或处理器间消息信息之一。该处理器还包括一个相关性管理模块，被配置为处理从至少一个消息获得的一致性信息，以及中断控制器，该中断控制器被配置为基于从至少一个消息获得的处理器间消息信息生成中断。

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