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21. 发明申请

US20130092986A1 SEMICONDUCOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130092986A1
公开(公告)日：2013-04-18
申请号：US13395608
申请日：2011-10-17
申请人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
发明人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/82345 , H01L21/28114 , H01L21/823468 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.
摘要翻译：一种半导体器件及其制造方法，所述方法包括：提供半导体衬底; 在所述基板上形成虚拟栅极区域，在所述栅极区域的侧壁上形成间隔物，以及在所述伪栅极区域的两侧形成所述半导体基板中的源极和漏极区域，所述伪栅极区域包括界面层和虚拟栅极电极 ; 在虚拟栅极区域和源极和漏极区域上形成电介质盖层; 使源极和漏极区域上的电介质盖层平坦化作为停止层; 进一步去除虚拟栅电极以露出界面层; 并在界面层上形成替换栅区。栅极沟槽的厚度可以通过电介质盖层的厚度来控制，并且可以根据需要进一步形成所需厚度和宽度的替换栅极。因此，栅极沟槽的纵横比减小，并且确保了足够的低栅极电阻。

22. 发明申请

US20120261803A1 HIGH-K GATE DIELECTRIC MATERIAL AND METHOD FOR PREPARING THE SAME 审中-公开
标题翻译：高K栅介质材料及其制备方法
公开(公告)号：US20120261803A1
公开(公告)日：2012-10-18
申请号：US13394935
申请日：2011-10-17
申请人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
发明人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
IPC分类号： H01L21/31 , H01L29/02
CPC分类号： C23C14/08 , C23C14/5806 , C23C16/401 , C23C16/56
摘要： The present invention forms Hf1-xSixOy having a cubic phase or a tetragonal phase by doping a specific amount of SiO2 component into the high-K gate dielectric material HfO2 in combination with an optimized thermal processing technique, to thereby acquire a high-K gate dielectric thin film material having a greater bandgap, a higher K value and high thermal stability. Besides, the high-K gate dielectric thin film and a preparation method thereof proposed in the present invention are helpful to solve the problem of crystallization of ultra-thin films.
摘要翻译：本发明通过与优化的热处理技术结合，将特定量的SiO 2成分掺入到高K栅介质材料HfO 2中，形成具有立方相或四方相的Hf1-xSixOy，从而获得高K栅极电介质具有较大带隙，较高K值和高热稳定性的薄膜材料。此外，本发明中提出的高K栅介质薄膜及其制备方法有助于解决超薄膜结晶的问题。

23. 发明授权

US08802518B2 Semiconducor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08802518B2
公开(公告)日：2014-08-12
申请号：US13395608
申请日：2011-10-17
申请人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
发明人： Wenwu Wang , Chao Zhao , Kai Han , Dapeng Chen
IPC分类号： H01L29/66 , H01L21/8238 , H01L21/28 , H01L29/49 , H01L21/8234 , H01L29/51 , H01L29/423
CPC分类号： H01L21/82345 , H01L21/28114 , H01L21/823468 , H01L21/823828 , H01L21/823842 , H01L21/823864 , H01L29/42376 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/6653 , H01L29/66545 , H01L29/6656
摘要： A semiconductor device and a method for manufacturing the same, the method comprising: providing a semiconductor substrate; forming a dummy gate area on the substrate, forming spacers on sidewalls of the gate area, and forming source and drain areas in the semiconductor substrate on both sides of the dummy gate area, the dummy gate area comprising an interface layer and a dummy gate electrode; forming a dielectric cap layer on the dummy gate area and source and drain areas; planarizing the device with the dielectric cap layer on the source and drain areas as a stop layer; further removing the dummy gate electrode to expose the interface layer; and forming replacement gate area on the interface layer. The thickness of the gate groove may be controlled by the thickness of the dielectric cap layer, and the replacement gates of desired thickness and width may be further formed upon requirements. Thus, the aspect ratio of the gate groove is reduced and a sufficient low gate resistance is ensured.
摘要翻译：一种半导体器件及其制造方法，所述方法包括：提供半导体衬底; 在所述基板上形成虚拟栅极区域，在所述栅极区域的侧壁上形成间隔物，以及在所述伪栅极区域的两侧形成所述半导体基板中的源极和漏极区域，所述伪栅极区域包括界面层和虚拟栅极电极 ; 在虚拟栅极区域和源极和漏极区域上形成电介质盖层; 使源极和漏极区域上的电介质盖层平坦化作为停止层; 进一步去除虚拟栅电极以露出界面层; 并在界面层上形成替换栅区。栅极沟槽的厚度可以通过电介质盖层的厚度来控制，并且可以根据需要进一步形成所需厚度和宽度的替换栅极。因此，栅极沟槽的纵横比减小，并且确保了足够的低栅极电阻。

24. 发明授权

US08415222B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08415222B2
公开(公告)日：2013-04-09
申请号：US13061655
申请日：2010-09-28
申请人： Wenwu Wang , Xueli Ma , Wen Ou , Dapeng Chen
发明人： Wenwu Wang , Xueli Ma , Wen Ou , Dapeng Chen
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/165 , H01L29/66636 , H01L29/7834 , H01L29/7848
摘要： The present invention provides a semiconductor device and a method for manufacturing the same. The method includes: providing a substrate; forming a gate stack on the substrate; forming an inter layer dielectric (ILD) to cover the device; etching the ILD at both sides of the gate stack and the substrate below the ILD, so as to form a groove of source and drain regions respectively; depositing a metal diffusion barrier layer in the groove; and filling the groove with a metal to form the source and drain regions. The semiconductor device includes: a substrate; a gate stack on the substrate; an inter layer dielectric (ILD) covering the device; a groove of source and drain regions formed in the ILD at both sides of the gate stack and the substrate below the ILD; and a metal diffusion barrier layer and a metal filler formed in the groove. According to the present invention, the S/D parasitic resistance in the MOS device is reduced, the S/D stress on the channel is increased, the process temperature is lowered, and the process compatibility between the high k gate dielectric layer and the metal gate is improved.
摘要翻译：本发明提供一种半导体器件及其制造方法。该方法包括：提供衬底; 在基板上形成栅叠层; 形成层间电介质（ILD）以覆盖该器件; 在栅极堆叠的两侧和ILD下面的衬底上蚀刻ILD，以分别形成源极和漏极区的沟槽; 在槽内沉积金属扩散阻挡层; 并用金属填充凹槽以形成源区和漏区。半导体器件包括：衬底; 衬底上的栅极堆叠; 覆盖该器件的层间电介质（ILD）; 源极和漏极区域的沟槽，形成在栅极堆叠的两侧的ILD和ILD下面的衬底; 以及形成在所述槽中的金属扩散阻挡层和金属填料。根据本发明，MOS器件中的S / D寄生电阻降低，沟道上的S / D应力增加，处理温度降低，并且高k栅介质层与金属之间的工艺相容性门改善。

25. 发明申请

US20110254063A1 SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
标题翻译：半导体器件结构及其制造方法
公开(公告)号：US20110254063A1
公开(公告)日：2011-10-20
申请号：US13063693
申请日：2010-09-27
申请人： Shijie Chen , Wenwu Wang , Xiaolei Wang , Kai Han
发明人： Shijie Chen , Wenwu Wang , Xiaolei Wang , Kai Han
IPC分类号： H01L29/78 , H01L21/321 , B82Y99/00 , B82Y40/00
CPC分类号： H01L21/28088 , H01L29/42372 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： The present invention provides a MOS device, which comprises: a substrate; an interface layer thin film formed on the substrate; a high k gate dielectric layer formed on the interface layer thin film; and a metal gate formed on the high k gate dielectric layer. The metal gate comprises, upwardly in order, a metal gate work function layer, an oxygen absorption element barrier layer, a metal gate oxygen absorbing layer, a metal gate barrier layer and a polysilicon layer. A metal gate oxygen absorbing layer is introduced into the metal gate for the purpose of preventing the outside oxygen from coming into the interface layer and absorbing the oxygen in the interface layer during a annealing process, such that the interface layer is reduced to be thinner and the EOT of MOS devices are effectively reduced; meanwhile, by adding an oxygen absorption element barrier layer, the “oxygen absorption element” is prevented from diffusing into the high k gate dielectric layer and giving rise to unfavorable impact thereon; in this way, the high k/metal gate system can be more easily integrated, and the performance of the device can be further improved accordingly.
摘要翻译：本发明提供一种MOS器件，其包括：衬底; 形成在基板上的界面层薄膜; 形成在界面层薄膜上的高k栅介质层; 以及形成在高k栅极电介质层上的金属栅极。金属栅极依次包括金属栅极功能层，氧吸收元件势垒层，金属栅极氧吸收层，金属栅极阻挡层和多晶硅层。为了防止外部氧气进入界面层并在退火过程中吸收界面层中的氧气，使得界面层减薄到较薄，并且金属栅极氧吸收层被引入金属栅极中 MOS器件的EOT有效减少; 同时通过添加氧吸收元件阻挡层，防止“氧吸收元件”扩散到高k栅介质层中并对其产生不利影响; 以这种方式，可以更容易地集成高k /金属栅极系统，并且可以相应地进一步改善器件的性能。

26. 发明申请

US20120146223A1 MOS DEVICE WITH MEMORY FUNCTION AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有记忆功能的MOS器件及其制造方法
公开(公告)号：US20120146223A1
公开(公告)日：2012-06-14
申请号：US13139063
申请日：2011-01-27
申请人： Chao Zhao , Wenwu Wang
发明人： Chao Zhao , Wenwu Wang
IPC分类号： H01L21/28 , H01L23/48
CPC分类号： H01L27/101 , H01L21/76814 , H01L21/76831 , H01L21/76843 , H01L21/76849 , H01L21/76855 , H01L21/76864 , H01L21/76873 , H01L23/53238 , H01L27/2436 , H01L29/78 , H01L45/085 , H01L45/1233 , H01L45/146 , H01L45/1633 , H01L2924/0002 , H01L2924/00
摘要： A manufacturing method of a MOS device with memory function is provided, which includes: providing a semiconductor substrate, a surface of the semiconductor substrate being covered by a first dielectric layer, a metal interconnect structure being formed in the first dielectric layer; forming a second dielectric layer overlying a surface of the first dielectric layer and the metal interconnect structure; forming an opening in the second dielectric layer, a bottom of the opening revealing the metal interconnect structure; forming an alloy layer at the bottom of the opening, material of the alloy layer containing copper and other metal; and performing a thermal treatment to the alloy layer and the metal interconnect structure to form, on the surface of the metal interconnect structure, a compound layer containing oxygen element. The compound layer containing oxygen element and the MOS device formed in the semiconductor substrate constitute a MOS device with memory function. The method provides a processing which has high controllability and improves the performance of devices.
摘要翻译：提供具有记忆功能的MOS器件的制造方法，其包括：提供半导体衬底，半导体衬底的表面被第一介电层覆盖，金属互连结构形成在第一介电层中; 形成覆盖在所述第一电介质层和所述金属互连结构的表面上的第二电介质层; 在所述第二介电层中形成开口，所述开口的底部露出所述金属互连结构; 在开口的底部形成合金层，含有铜等金属的合金层的材料; 对合金层和金属互连结构进行热处理，在金属互连结构的表面形成含有氧元素的化合物层。包含氧元素的化合物层和形成在半导体衬底中的MOS器件构成具有记忆功能的MOS器件。该方法提供了具有高可控性和提高设备性能的处理。

27. 发明申请

US20140015068A1 Gate Structure, Semiconductor Device and Methods for Forming the Same 审中-公开
标题翻译：门结构，半导体器件及其形成方法
公开(公告)号：US20140015068A1
公开(公告)日：2014-01-16
申请号：US13699731
申请日：2012-07-24
申请人： Hong Yang , Wenwu Wang , Huaxiang Yin , Jiang Yan , Xueli Ma
发明人： Hong Yang , Wenwu Wang , Huaxiang Yin , Jiang Yan , Xueli Ma
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L29/495 , H01L21/28008 , H01L21/28088 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： The disclosure relates to a gate structure, a semiconductor device and methods for forming the same. An embodiment of the disclosure provides a method for forming a gate structure, including: providing a substrate; forming an interface layer on the substrate; forming a gate dielectric layer on the interface layer; forming a gate dielectric capping layer on the gate dielectric layer; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming an oxygen scavenging element capping layer on the oxygen scavenging element layer; performing Post-Metallization Annealing; performing etching until the etching stop layer is exposed; forming a work function adjustment layer on the etching stop layer; and forming a gate layer on the work function adjustment layer.
摘要翻译：本公开涉及一种栅极结构，半导体器件及其形成方法。本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供基板; 在衬底上形成界面层; 在界面层上形成栅介电层; 在所述栅极电介质层上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成氧清除元件盖层; 执行金属后退火; 进行蚀刻，直到蚀刻停止层露出为止; 在所述蚀刻停止层上形成功函数调整层; 以及在所述功函数调整层上形成栅极层。

28. 发明申请

US20140015063A1 Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device 有权
标题翻译：形成栅极结构的方法，形成半导体器件的方法和半导体器件
公开(公告)号：US20140015063A1
公开(公告)日：2014-01-16
申请号：US13699734
申请日：2012-07-24
申请人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
发明人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/8238 , H01L21/823842 , H01L21/823857 , H01L27/092
摘要： A method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on the substrate; forming an etching stop layer on the gate dielectric capping layer; forming an oxygen scavenging element layer on the etching stop layer; forming a first work function adjustment layer on the oxygen scavenging element layer; etching the first work function adjustment layer above the nMOSFET area; forming a second work function adjustment layer on the surface of the substrate; metal layer depositing and annealing to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
摘要翻译：一种用于形成栅极结构的方法，包括：提供衬底，其中所述衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且每个栅极沟槽设置在底部具有栅极电介质层; 在所述衬底上形成栅介电覆盖层; 在所述栅极电介质覆盖层上形成蚀刻停止层; 在所述蚀刻停止层上形成氧清除元件层; 在除氧元件层上形成第一功函数调整层; 蚀刻nMOSFET区域上方的第一功函数调整层; 在所述基板的表面上形成第二功函数调整层; 金属层沉积和退火以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

29. 发明申请

US20140015062A1 Method for Forming Gate Structure, Method for Forming Semiconductor Device, and Semiconductor Device 审中-公开
标题翻译：形成栅极结构的方法，形成半导体器件的方法和半导体器件
公开(公告)号：US20140015062A1
公开(公告)日：2014-01-16
申请号：US13699732
申请日：2012-07-24
申请人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
发明人： Hong Yang , Xueli Ma , Wenwu Wang , Kai Han , Xiaolei Wang , Huaxiang Yin , Jiang Yan
IPC分类号： H01L21/8238 , H01L27/092
CPC分类号： H01L21/823857 , H01L21/823842 , H01L27/092
摘要： An embodiment of the present disclosure provides a method for forming a gate structure, comprising: providing a substrate, where the substrate includes a nMOSFET area and a pMOSFET area, each of the nMOSFET area and the pMOSFET area has a gate trench, and each of the gate trenches is provided at a bottom portion with a gate dielectric layer; forming a gate dielectric capping layer on a surface of the substrate; forming an oxygen scavenging element layer on the gate dielectric capping layer; forming an etching stop layer on the oxygen scavenging element layer; forming a work function adjustment layer on the etching stop layer; performing metal layer deposition and annealing process to fill the gate trenches with a metal layer; and removing the metal layer outside the gate trenches.
摘要翻译：本公开的实施例提供了一种用于形成栅极结构的方法，包括：提供衬底，其中衬底包括nMOSFET区域和pMOSFET区域，nMOSFET区域和pMOSFET区域中的每一个具有栅极沟槽，并且栅极沟槽在底部设置有栅极电介质层; 在所述衬底的表面上形成栅介电覆盖层; 在所述栅介质顶盖层上形成氧清除元件层; 在除氧元件层上形成蚀刻停止层; 在所述蚀刻停止层上形成功函数调整层; 执行金属层沉积和退火工艺以用金属层填充栅极沟槽; 以及去除栅极沟槽外的金属层。

30. 发明授权

US08030717B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08030717B2
公开(公告)日：2011-10-04
申请号：US12401772
申请日：2009-03-11
申请人： Koji Akiyama , Wenwu Wang
发明人： Koji Akiyama , Wenwu Wang
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/517 , H01L21/28194 , H01L29/495 , H01L29/513 , H01L29/78
摘要： A disclosed semiconductor device includes a gate insulation film formed on a silicon substrate and a metal gate electrode formed in the gate insulation film, wherein the gate insulation film includes a first insulation film, a second insulation film that is formed on the first insulation film and has a greater dielectric constant than the first insulation film, and a third insulation film formed on the second insulation film.
摘要翻译：所公开的半导体器件包括形成在硅衬底上的栅极绝缘膜和形成在栅极绝缘膜中的金属栅电极，其中栅极绝缘膜包括第一绝缘膜，形成在第一绝缘膜上的第二绝缘膜和具有比第一绝缘膜更大的介电常数和形成在第二绝缘膜上的第三绝缘膜。

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