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21. 发明授权

US07320897B2 Electroluminescence device with nanotip diodes 有权
标题翻译：具有纳米二极管的电致发光器件
公开(公告)号：US07320897B2
公开(公告)日：2008-01-22
申请号：US11090386
申请日：2005-03-23
申请人： Sheng Teng Hsu , Tingkai Li , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Tingkai Li , Wei-Wei Zhuang
IPC分类号： H01L21/66
CPC分类号： H01L33/08 , B82Y20/00 , H01L33/18 , H01L33/24 , H01L33/34 , H01L33/502 , Y10S977/834
摘要： A nanotip electroluminescence (EL) diode and a method are provided for fabricating said device. The method comprises: forming a plurality of Si nanotip diodes; forming a phosphor layer overlying the nanotip diode; and, forming a top electrode overlying the phosphor layer. The nanotip diodes are formed by: forming a Si substrate with a top surface; forming a Si p-well; forming an n+ layer of Si, having a thickness in the range of 30 to 300 nanometers (nm) overlying the Si p-well; forming a reactive ion etching (RIE)-induced polymer grass overlying the substrate top surface; using the RIE-induced polymer grass as a mask, etching areas of the substrate not covered by the mask; and, forming the nanotip diodes in areas of the substrate covered by the mask.
摘要翻译：提供了一种纳米末端电致发光（EL）二极管和一种用于制造所述器件的方法。该方法包括：形成多个Si纳米二极管; 形成覆盖所述纳米二极管的磷光体层; 并且形成覆盖磷光体层的顶部电极。纳米二极管通过以下方式形成：形成具有顶表面的Si衬底; 形成Si对孔; 形成层叠Si层的厚度为30〜300纳米（nm）的Si的n +层; 形成覆盖在衬底顶表面上的反应离子蚀刻（RIE）诱导的聚合物草; 使用RIE诱导的聚合物草作为掩模，蚀刻未被掩模覆盖的基底的区域; 以及在由掩模覆盖的衬底的区域中形成纳米二极管二极管。

22. 发明授权

US07029982B1 Method of affecting RRAM characteristics by doping PCMO thin films 有权
标题翻译：通过掺杂PCMO薄膜影响RRAM特性的方法
公开(公告)号：US07029982B1
公开(公告)日：2006-04-18
申请号：US10971387
申请日：2004-10-21
申请人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , David R. Evans , Fengyan Zhang , Sheng Teng Hsu
IPC分类号： H01L21/20
CPC分类号： H01L45/1608 , C23C18/1216 , C23C18/1225 , C23C18/1283 , C23C18/1295 , H01L21/31691 , H01L28/20 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A method of fabricating a doped-PCMO thin film layer includes preparing a PCMO precursor solution having a transition metal additive therein; and spin-coating the doped-PCMO spin-coating solution onto a wafer.
摘要翻译：制造掺杂PCMO薄膜层的方法包括制备其中具有过渡金属添加剂的PCMO前体溶液; 并将掺杂的PCMO旋涂溶液旋涂到晶片上。

23. 发明授权

US06905937B2 Methods of fabricating a cross-point resistor memory array 有权
标题翻译：制造交叉点电阻存储器阵列的方法
公开(公告)号：US06905937B2
公开(公告)日：2005-06-14
申请号：US10391292
申请日：2003-03-17
申请人： Sheng Teng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： G11C11/15 , G11C11/56 , G11C13/00 , H01L27/24 , H01L21/20
CPC分类号： G11C11/15 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/77 , H01L27/24
摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions. The resistive cross-point memory device is formed by doping lines within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.
摘要翻译：提供了电阻式交叉点存储器件，以及制造和使用方法。存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。在电阻性存储器材料和下电极之间的界面处形成二极管，其可以形成为掺杂区域。电阻性交叉点存储器件通过在衬底内掺杂一个极性而形成，然后将相反极性的线的掺杂区域形成二极管。然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

24. 发明授权

US06841833B2 1T1R resistive memory 有权
标题翻译： 1T1R电阻式存储器
公开(公告)号：US06841833B2
公开(公告)日：2005-01-11
申请号：US10453156
申请日：2003-06-03
申请人： Sheng Teng Hsu , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Wei-Wei Zhuang
IPC分类号： H01L39/00 , G06F12/00 , G11C13/00 , H01L21/8246 , H01L27/10 , H01L27/105 , H01L27/24 , H01L43/08 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/79 , H01L27/2436 , H01L27/2472 , H01L45/04 , H01L45/1233 , H01L45/147
摘要： A drain loaded 1T1R resistive memory device and 1T1R resistive memory array are provided. The resistive memory array comprises an array of drain loaded 1T1R resistive memory device structures. Word lines are connected across transistor gates, while a resistive elements are connected between transistor gates and bit lines. The resistive element comprises a material with a resistance that is changed electrically, for example using a sequence of electric pulses. The resistive element may comprise PCMO.
摘要翻译：提供漏极负载的1T1R电阻式存储器件和1T1R电阻式存储器阵列。电阻性存储器阵列包括漏极负载的1T1R电阻存储器件结构的阵列。字线连接在晶体管栅极之间，而电阻元件连接在晶体管栅极和位线之间。电阻元件包括具有电阻变化的材料，例如使用一系列电脉冲。电阻元件可以包括PCMO。

25. 发明授权

US06825058B2 Methods of fabricating trench isolated cross-point memory array 有权
标题翻译：制造沟槽隔离交叉点存储器阵列的方法
公开(公告)号：US06825058B2
公开(公告)日：2004-11-30
申请号：US10391290
申请日：2003-03-17
申请人： Sheng Teng Hsu , Wei Pan , Wei-Wei Zhuang
发明人： Sheng Teng Hsu , Wei Pan , Wei-Wei Zhuang
IPC分类号： H01L2100
CPC分类号： G11C11/15 , G11C11/5685 , G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/72 , G11C2213/77 , H01L27/24
摘要： Resistive cross-point memory devices are provided, along with methods of manufacture and use. The memory devices are comprised by an active layer of resistive memory material interposed between upper electrodes and lower electrodes. A bit region located within the resistive memory material at the cross-point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. A diode is formed between at the interface between the resistive memory material and the lower electrodes, which may be formed as doped regions, isolated from each other by shallow trench isolation. The resistive cross-point memory device is formed by doping lines, which are separated from each other by shallow trench isolation, within a substrate one polarity, and then doping regions of the lines the opposite polarity to form diodes. Bottom electrodes are then formed over the diodes with a layer of resistive memory material overlying the bottom electrodes. Top electrodes may then be added at an angled to form a cross-point array defined by the lines and the top electrodes.
摘要翻译：提供了电阻式交叉点存储器件，以及制造和使用方法。存储器件由介于上电极和下电极之间的电阻存储器材料的有源层组成。在上电极和下电极的交叉点处位于电阻性存储器材料内的位区域具有响应于施加一个或更多个电压脉冲而能够在一定范围内变化的电阻率。可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。在电阻性存储器材料和下部电极之间的界面处形成二极管，其可以形成为通过浅沟槽隔离彼此隔离的掺杂区域。电阻交叉点存储器件通过在衬底内通过浅沟槽隔离彼此分离的线路形成一个极性，然后将相反极性的线的掺杂区域形成二极管形成。然后在二极管上形成一层电阻记忆材料覆盖底部电极的底部电极。然后可以以倾斜的角度添加顶部电极以形成由线和顶部电极限定的交叉点阵列。

26. 发明授权

US06824814B2 Preparation of LCPMO thin films which have reversible resistance change properties 有权
标题翻译：制备具有可逆电阻变化特性的LCPMO薄膜
公开(公告)号：US06824814B2
公开(公告)日：2004-11-30
申请号：US10153841
申请日：2002-05-21
申请人： Wei-Wei Zhuang , Sheng Teng Hsu , Wei Pan , Masayuki Tajiri
发明人： Wei-Wei Zhuang , Sheng Teng Hsu , Wei Pan , Masayuki Tajiri
IPC分类号： B05D512
CPC分类号： C23C18/1216 , C23C18/1225 , C23C18/1283 , G11C13/0007 , G11C2213/31 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1608
摘要： A method of forming a perovskite thin film includes preparing a perovskite precursor solution; preparing a silicon substrate for deposition of a perovskite thin film, including forming a bottom electrode on the substrate; securing the substrate in a spin-coating apparatus and spinning the substrate at a predetermined spin rate; injecting a perovskite precursor solution into the spin-coating apparatus thereby coating the substrate with the perovskite precursor solution to form a coated substrate; baking the coated substrate at temperatures which increase incrementally from about 90° C. to 300° C.; and annealing the coated substrate at a temperature of between about 500° C. to 800° C. for between five minutes to fifteen minutes.
摘要翻译：形成钙钛矿薄膜的方法包括制备钙钛矿前体溶液; 制备用于沉积钙钛矿薄膜的硅衬底，包括在衬底上形成底电极; 将基材固定在旋涂装置中并以预定的旋转速率旋转基材; 将钙钛矿前体溶液注入到旋涂装置中，由此用钙钛矿前体溶液涂覆基材以形成涂布的基材; 在从约90℃增加到300℃的温度下烘烤涂覆的基材; 并在约500℃至800℃的温度下退火涂覆的基材5分钟至15分钟。

27. 发明授权

US06774004B1 Nano-scale resistance cross-point memory array 有权
标题翻译：纳米级电阻交叉点存储阵列
公开(公告)号：US06774004B1
公开(公告)日：2004-08-10
申请号：US10391357
申请日：2003-03-17
申请人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
发明人： Sheng Teng Hsu , Wei-Wei Zhuang , Wei Pan , Fengyan Zhang
IPC分类号： H01L2120
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/77 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1683
摘要： A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.
摘要翻译：制造纳米尺度电阻交叉点存储器阵列的方法包括制备硅衬底; 在衬底上沉积氧化硅至预定厚度; 在氧化硅中形成纳米尺度的沟槽; 在沟槽中沉积第一连接线; 在第一连接线上的沟槽中沉积记忆电阻层; 在所述存储器电阻层的沟槽中沉积第二连接线; 并完成内存阵列。交叉点存储器阵列包括硅衬底; 形成在所述基板上的第一连接线; 形成在第一连接线上的巨大的磁阻层; 形成在巨磁阻层的一部分上的氮化硅层; 以及与氮化硅层和巨磁阻层相邻形成的第二连接线。

28. 发明授权

US06654210B2 Solid-state inductor and method for same 失效
标题翻译：固态电感及其相同方法
公开(公告)号：US06654210B2
公开(公告)日：2003-11-25
申请号：US10131411
申请日：2002-04-22
申请人： Wei Pan , Sheng Teng Hsu , Wei-Wei Zhuang
发明人： Wei Pan , Sheng Teng Hsu , Wei-Wei Zhuang
IPC分类号： G11B5127
CPC分类号： G11C13/0007 , G11C2213/31 , H01F10/193 , H01F21/00 , H01F41/24 , H01L27/08 , H01L28/10 , Y10T29/4902
摘要： A solid-state inductor and a method for forming a solid-state inductor are provided. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) thin film overlying the bottom electrode; forming a top electrode overlying the CMR thin film; applying an electrical field treatment to the CMR thin film in the range of 0.4 to 1 megavolts per centimeter (MV/cm) with a pulse width in the range of 100 nanoseconds (ns) to 1 millisecond (ms); in response to the electrical field treatment, converting the CMR thin film into a CMR thin film inductor; applying a bias voltage between the top and bottom electrodes; and, in response to the applied bias voltage, creating an inductance between the top and bottom electrodes. When the applied bias voltage is varied, the inductance varies in response.
摘要翻译：提供固态电感器和形成固态电感器的方法。该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）薄膜; 形成覆盖CMR薄膜的顶部电极; 以0.1纳秒（ns）至1毫秒（ms）的脉冲宽度在0.4至1兆伏特/厘米（MV / cm）范围内对CMR薄膜进行电场处理; 响应于电场处理，将CMR薄膜转换成CMR薄膜电感器; 在顶部和底部电极之间施加偏置电压; 并且响应于施加的偏置电压，在顶部和底部电极之间产生电感。当施加的偏置电压变化时，电感响应变化。

29. 发明授权

US06190963B1 Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier and method for same 有权
$Composite iridium-metal-oxygen barrier structure with refractory metal companion barrier and method for same$
标题翻译：复合铱金属 - 氧阻隔结构与难熔金属伴侣屏障及其方法相同
公开(公告)号：US06190963B1
公开(公告)日：2001-02-20
申请号：US09316661
申请日：1999-05-21
申请人： Fengyan Zhang , Sheng Teng Hsu , Jer-shen Maa , Wei-Wei Zhuang
发明人： Fengyan Zhang , Sheng Teng Hsu , Jer-shen Maa , Wei-Wei Zhuang
IPC分类号： H01L218242
CPC分类号： H01L28/75 , H01L21/28568 , H01L28/55
摘要： An Ir—M—O composite film has been provided that is useful in forming an electrode of a ferroelectric capacitor, where M includes a variety of refractory metals. The Ir combination film is resistant to high temperature annealing in oxygen environments. When used with an underlying barrier layer made from the same variety of M transition metals, the resulting conductive barrier also suppresses to diffusion of Ir into any underlying Si substrates. As a result, Ir silicide products are not formed, which degrade the electrode interface characteristics. That is, the Ir combination film remains conductive, not peeling or forming hillocks, during high temperature annealing processes, even in oxygen. The Ir—M—O conductive electrode/barrier structures are useful in nonvolatile FeRAM devices, DRAMs, capacitors, pyroelectric infrared sensors, optical displays, optical switches, piezoelectric transducers, and surface acoustic wave devices. A method for forming an Ir—M—O composite film barrier layer and an Ir—M—O composite film ferroelectric electrode are also provided.
摘要翻译：已经提供了可用于形成铁电电容器的电极的Ir-M-O复合膜，其中M包括各种难熔金属。 Ir组合膜在氧气环境中耐高温退火。当与由相同种类的M过渡金属制成的底层阻挡层一起使用时，所得到的导电屏障还抑制Ir扩散到任何下面的Si衬底中。结果，不形成铱硅化物产物，这降低了电极界面的特性。也就是说，即使在氧气中，Ir组合膜在高温退火过程中仍保持导电性，不会剥离或形成小丘。 Ir-M-O导电电极/屏障结构可用于非易失性FeRAM器件，DRAM，电容器，热释电红外传感器，光学显示器，光开关，压电换能器和表面声波器件。还提供了形成Ir-M-O复合膜阻挡层和Ir-M-O复合膜铁电电极的方法。

30. 发明授权

US6015918A Allyl-derived precursor and synthesis method 有权
标题翻译：烯丙基衍生的前体和合成方法
公开(公告)号：US6015918A
公开(公告)日：2000-01-18
申请号：US281731
申请日：1999-03-30
申请人： Wei-Wei Zhuang , Tue Nguyen , Greg Michael Stecker , David Russell Evans , Sheng Teng Hsu
发明人： Wei-Wei Zhuang , Tue Nguyen , Greg Michael Stecker , David Russell Evans , Sheng Teng Hsu
IPC分类号： C07F1/00 , C07F1/08 , C07F7/08 , C23C16/18 , C07F1/10
CPC分类号： C23C16/18 , C07F1/08 , C07F7/082
摘要： A Cu(hfac) allyl-derived ligand precursor has been provided. The ligand includes group consisting of alkyl, phenyl, trialkylsilane, trialkoxylsilane, halodialkylsilane, dihaloalkylsilane, trihalosilane, triphenylsilane, alkoxyl, halogen, chloroformate, cynanide, cycloalkyl, cycloalkylamine, alkyl ether, isocyanate, and pentafluorobenzene. Examples of the allyl-derived ligand precursors have proved to be stable at room temperatures, and sufficiently volatile at higher temperatures. Copper deposited with this precursor has low resistivity and high adhesive characteristics. A synthesis method has been provided which produces a high yield of the above-described precursors, including a Cu(hfac)(allyltrimethylsilane) precursor.
摘要翻译：已经提供了一种Cu（hfac）烯丙基衍生的配体前体。配体包括由烷基，苯基，三烷基硅烷，三烷氧基硅烷，卤代烷基硅烷，二卤代烷基硅烷，三卤硅烷，三苯基硅烷，烷氧基，卤素，氯甲酸酯，环己烷，环烷基，环烷基胺，烷基醚，异氰酸酯和五氟苯组成的组。已经证明烯丙基衍生的配体前体的实例在室温下是稳定的，并且在较高温度下具有足够的挥发性。沉积有该前体的铜具有低电阻率和高粘合特性。已经提供了产生高产率的上述前体，包括Cu（hfac）（烯丙基三甲基硅烷）前体的合成方法。

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