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21. 发明申请

US20100216290A1 Method for forming semiconductor device 有权
公开(公告)号：US20100216290A1
公开(公告)日：2010-08-26
申请号：US12483237
申请日：2009-06-11
申请人： Li-Cheng Lin , Wei-Chieh Lin
发明人： Li-Cheng Lin , Wei-Chieh Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/4236 , H01L29/66621 , H01L29/78
摘要： A method for forming semiconductor device, which simultaneously forms a trench MOS transistor device, and an embedded schottky barrier diode (SBD) device in a semiconductor substrate. The embedded SBD device has lower forward voltage drop, which reduces power dissipation. In addition, the voltage bearing ability may be modified easily by virtue of altering the dopant concentration or the width of the voltage bearing dopant region, or the thickness of epitaxial silicon layer. Furthermore, extra cost of purchasing SBD diode may be saved.

22. 发明申请

US20120126328A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120126328A1
公开(公告)日：2012-05-24
申请号：US13025176
申请日：2011-02-11
申请人： Wei-Chieh Lin
发明人： Wei-Chieh Lin
IPC分类号： H01L27/088
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/1095
摘要： A semiconductor device includes an epitaxial layer having a first conductive type, and at least one first semiconductor layer and a second semiconductor layer having a second conductive type. The first semiconductor layer is disposed in the epitaxial layer of a peripheral region, and has an arc portion, and a first strip portion and a second strip portion extended from two ends of the arc portion. The first strip portion points to an active device region, and the second strip portion is perpendicular to the first strip portion The second semiconductor layer is disposed in the epitaxial layer of the peripheral region between the active device region and the second strip portion, and the second semiconductor has a sidewall facing and parallel to the first semiconductor layer.
摘要翻译：半导体器件包括具有第一导电类型的外延层和至少一个第一半导体层和具有第二导电类型的第二半导体层。第一半导体层设置在周边区域的外延层中，具有弧形部分，以及从弧形部分的两端延伸的第一条带部分和第二条带部分。第一条带部分指向有源器件区域，第二条带部分垂直于第一条带部分。第二半导体层设置在有源器件区域和第二条带部分之间的外围区域的外延层中，并且第二半导体具有面向并平行于第一半导体层的侧壁。

23. 发明申请

US20120056277A1 SEMICONDUCTOR DEVICE INTEGRATED WITH CONVERTER AND PACKAGE STRUCTURE THEREOF 有权
标题翻译：集成转换器的半导体器件及其封装结构
公开(公告)号：US20120056277A1
公开(公告)日：2012-03-08
申请号：US13013832
申请日：2011-01-26
申请人： Wei-Chieh Lin
发明人： Wei-Chieh Lin
IPC分类号： H01L29/78 , H01L23/495
CPC分类号： H01L23/49562 , H01L21/823418 , H01L21/823456 , H01L21/823487 , H01L23/3107 , H01L23/4952 , H01L23/49524 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/088 , H01L29/0649 , H01L29/1087 , H01L29/4175 , H01L29/41766 , H01L29/7813 , H01L29/7835 , H01L2224/0603 , H01L2224/06051 , H01L2224/37147 , H01L2224/40247 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/49175 , H01L2224/73221 , H01L2224/8385 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01079 , H01L2924/12032 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012
摘要： The present invention provides a semiconductor device including a semiconductor substrate having a first conductive type, at least one high-side transistor device and at least one low-side transistor device. The high-side transistor device includes a doped high-side base region having a second conductive type, a doped high-side source region having the first conductive type and a doped drain region having the first conductive type. The doped high-side base region is disposed within the semiconductor substrate, and the doped high-side source region and the doped drain region are disposed within the doped high-side base region. The doped high-side source region is electrically connected to the semiconductor substrate, and the semiconductor substrate is regarded as a drain of the low-side transistor device.
摘要翻译：本发明提供一种半导体器件，其包括具有第一导电类型的半导体衬底，至少一个高侧晶体管器件和至少一个低侧晶体管器件。高侧晶体管器件包括具有第二导电类型的掺杂高侧基极区域，具有第一导电类型的掺杂高侧源极区域和具有第一导电类型的掺杂漏极区域。掺杂的高侧基极区域设置在半导体衬底内，并且掺杂的高侧源极区域和掺杂漏极区域设置在掺杂的高侧基极区域内。掺杂的高侧源极区域与半导体衬底电连接，半导体衬底被认为是低侧晶体管器件的漏极。

24. 发明授权

US08049273B2 Semiconductor device for improving the peak induced voltage in switching converter 有权
标题翻译：用于提高开关转换器中峰值感应电压的半导体器件
公开(公告)号：US08049273B2
公开(公告)日：2011-11-01
申请号：US12371618
申请日：2009-02-15
申请人： Wei-Chieh Lin , Ho-Tai Chen , Li-Cheng Lin , Jen-Hao Yeh , Hsin-Yen Chiu , Hsin-Yu Hsu , Shih-Chieh Hung
发明人： Wei-Chieh Lin , Ho-Tai Chen , Li-Cheng Lin , Jen-Hao Yeh , Hsin-Yen Chiu , Hsin-Yu Hsu , Shih-Chieh Hung
IPC分类号： H01L26/66
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/42376 , H01L29/4238 , H01L29/456 , H01L29/4916
摘要： A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.
摘要翻译：功率半导体器件包括背面金属层，形成在背面金属层上的衬底，形成在衬底上的半导体层和前侧金属层。半导体层包括第一沟槽结构，其包括围绕具有多晶硅注入的第一沟槽形成的栅极氧化层，第二沟槽结构，包括围绕具有多晶硅注入的第二沟槽形成的栅极氧化层，形成的p基区在所述第一沟槽结构和所述第二沟槽结构之间形成有多个n +源极区，形成在所述p基区上以及所述第一沟槽结构和所述第二沟槽结构之间，形成在所述第一沟槽结构上的介电层，所述第二沟槽结构，以及多个n +源极区域。前半导体金属层形成在半导体层上并填充形成在p基区上的多个n +源极区之间的间隙。

25. 发明申请

US20100117142A1 Semiconductor Device for Improving the Peak Induced Voltage in Switching Converter 有权
标题翻译：用于提高开关转换器中的峰值感应电压的半导体器件
公开(公告)号：US20100117142A1
公开(公告)日：2010-05-13
申请号：US12371618
申请日：2009-02-15
申请人： Wei-Chieh Lin , Ho-Tai Chen , Li-Cheng Lin , Jen-Hao Yeh , Hsin-Yen Chiu , Hsin-Yu Hsu , Shih-Chieh Hung
发明人： Wei-Chieh Lin , Ho-Tai Chen , Li-Cheng Lin , Jen-Hao Yeh , Hsin-Yen Chiu , Hsin-Yu Hsu , Shih-Chieh Hung
IPC分类号： H01L29/772
CPC分类号： H01L29/7813 , H01L29/0696 , H01L29/1095 , H01L29/41741 , H01L29/41766 , H01L29/42376 , H01L29/4238 , H01L29/456 , H01L29/4916
摘要： A power semiconductor device includes a backside metal layer, a substrate formed on the backside metal layer, a semiconductor layer formed on the substrate, and a frontside metal layer. The semiconductor layer includes a first trench structure including a gate oxide layer formed around a first trench with poly-Si implant, a second trench structure including a gate oxide layer formed around a second trench with poly-Si implant, a p-base region formed between the first trench structure and the second trench structure, a plurality of n+ source region formed on the p-base region and between the first trench structure and the second trench structure, a dielectric layer formed on the first trench structure, the second trench structure, and the plurality of n+ source region. The frontside metal layer is formed on the semiconductor layer and filling gaps formed between the plurality of n+ source region on the p-base region.
摘要翻译：功率半导体器件包括背面金属层，形成在背面金属层上的衬底，形成在衬底上的半导体层和前侧金属层。半导体层包括第一沟槽结构，其包括围绕具有多晶硅注入的第一沟槽形成的栅极氧化层，第二沟槽结构，包括围绕具有多晶硅注入的第二沟槽形成的栅极氧化层，形成的p基区在所述第一沟槽结构和所述第二沟槽结构之间形成有多个n +源极区，形成在所述p基区上以及所述第一沟槽结构和所述第二沟槽结构之间，形成在所述第一沟槽结构上的介电层，所述第二沟槽结构，以及多个n +源极区域。前半导体金属层形成在半导体层上并填充形成在p基区上的多个n +源极区之间的间隙。

26. 发明授权

US07682903B1 Method of forming a power device 有权
标题翻译：形成电力设备的方法
公开(公告)号：US07682903B1
公开(公告)日：2010-03-23
申请号：US12334492
申请日：2008-12-14
申请人： Wei-Chieh Lin , Hsin-Yu Hsu , Hsin-Yen Chiu , Shih-Chieh Hung , Ho-Tai Chen , Jen-Hao Yeh , Li-Cheng Lin
发明人： Wei-Chieh Lin , Hsin-Yu Hsu , Hsin-Yen Chiu , Shih-Chieh Hung , Ho-Tai Chen , Jen-Hao Yeh , Li-Cheng Lin
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/4236 , H01L29/456 , H01L29/66734
摘要： A method of forming a power device includes providing a substrate, a semiconductor layer having at least a trench and being disposed on the substrate, a gate insulating layer covering the semiconductor layer, and a conductive material disposed in the trench, performing an ion implantation process to from a body layer, performing a tilted ion implantation process to from a heavy doped region, forming a first dielectric layer overall, performing a chemical mechanical polishing process until the body layer disposed under the heavy doped region is exposed to form source regions on the opposite sides of the trench, and forming a source trace directly covering the source regions disposed on the opposite sides of the trench.
摘要翻译：一种形成功率器件的方法包括提供衬底，至少具有沟槽并设置在衬底上的半导体层，覆盖半导体层的栅极绝缘层和设置在沟槽中的导电材料，执行离子注入工艺从体层进行倾斜的离子注入工艺，从重掺杂区域进行倾斜的离子注入工艺，整体形成第一介电层，进行化学机械抛光工艺，直到布置在重掺杂区域之下的体层露出，形成源区并且形成直接覆盖设置在沟槽的相对侧上的源极区域的源极迹线。

27. 发明授权

US08426914B2 Semiconductor device integrated with converter and package structure thereof 有权
标题翻译：集成转换器的半导体器件及其封装结构
公开(公告)号：US08426914B2
公开(公告)日：2013-04-23
申请号：US13013832
申请日：2011-01-26
申请人： Wei-Chieh Lin
发明人： Wei-Chieh Lin
IPC分类号： H01L29/00
CPC分类号： H01L23/49562 , H01L21/823418 , H01L21/823456 , H01L21/823487 , H01L23/3107 , H01L23/4952 , H01L23/49524 , H01L24/37 , H01L24/40 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L27/088 , H01L29/0649 , H01L29/1087 , H01L29/4175 , H01L29/41766 , H01L29/7813 , H01L29/7835 , H01L2224/0603 , H01L2224/06051 , H01L2224/37147 , H01L2224/40247 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/49175 , H01L2224/73221 , H01L2224/8385 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01079 , H01L2924/12032 , H01L2924/13091 , H01L2924/181 , H01L2924/30107 , H01L2924/00 , H01L2924/00012
摘要： The present invention provides a semiconductor device including a semiconductor substrate having a first conductive type, at least one high-side transistor device and at least one low-side transistor device. The high-side transistor device includes a doped high-side base region having a second conductive type, a doped high-side source region having the first conductive type and a doped drain region having the first conductive type. The doped high-side base region is disposed within the semiconductor substrate, and the doped high-side source region and the doped drain region are disposed within the doped high-side base region. The doped high-side source region is electrically connected to the semiconductor substrate, and the semiconductor substrate is regarded as a drain of the low-side transistor device.
摘要翻译：本发明提供一种半导体器件，其包括具有第一导电类型的半导体衬底，至少一个高侧晶体管器件和至少一个低侧晶体管器件。高侧晶体管器件包括具有第二导电类型的掺杂高侧基极区域，具有第一导电类型的掺杂高侧源极区域和具有第一导电类型的掺杂漏极区域。掺杂的高侧基极区域设置在半导体衬底内，并且掺杂的高侧源极区域和掺杂漏极区域设置在掺杂的高侧基极区域内。掺杂的高侧源极区域与半导体衬底电连接，半导体衬底被认为是低侧晶体管器件的漏极。

28. 发明申请

US20120146138A1 POWER DEVICE WITH LOW PARASITIC TRANSISTOR AND METHOD OF MAKING THE SAME 有权
标题翻译：具有低PARASITIC晶体管的功率器件及其制造方法
公开(公告)号：US20120146138A1
公开(公告)日：2012-06-14
申请号：US13070479
申请日：2011-03-24
申请人： Wei-Chieh Lin
发明人： Wei-Chieh Lin
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/0869 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/42372 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： The power device with low parasitic transistor comprises a recessed transistor and a heavily doped region at a side of a source region of the recessed transistor. The conductive type of the heavily doped region is different from that of the source region. In addition, a contact plug contacts the heavily doped region and connects the heavily doped region electrically. A source wire covers and contacts the source region and the contact plug to make the source region and the heavily doped region have the same electrical potential.
摘要翻译：具有低寄生晶体管的功率器件包括凹陷晶体管和位于凹陷晶体管的源极区一侧的重掺杂区域。重掺杂区域的导电类型与源极区域的导电类型不同。此外，接触插塞接触重掺杂区域并电连接重掺杂区域。源极线覆盖并接触源极区域和接触插塞以使源极区域和重掺杂区域具有相同的电势。

29. 发明申请

US20090114983A1 Power Transistor Capable of Decreasing Capacitance between Gate and Drain 审中-公开
标题翻译：功率晶体管能够降低栅极和漏极之间的电容
公开(公告)号：US20090114983A1
公开(公告)日：2009-05-07
申请号：US12142802
申请日：2008-06-20
申请人： Wei-Chieh Lin , Jen-Hao Yeh , Ming-Jang Lin
发明人： Wei-Chieh Lin , Jen-Hao Yeh , Ming-Jang Lin
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0661 , H01L29/1095 , H01L29/41741 , H01L29/41766
摘要： A power transistor capable of decreasing capacitance between a gate and a drain includes a backside mental layer, a substrate formed on the backside mental layer, a semiconductor layer formed on the substrate, and a frontside mental layer formed on the semiconductor layer. The semiconductor layer comprises a first trench structure comprising a gate oxide layer, a second trench structure comprising a p-well junction formed around a second trench, a p-body region formed outside the first trench structure and the second trench structure, a first n+ source region formed on the p-body region and beside a sidewall of the first trench structure, a second n+ source region formed on the p-body region and between another sidewall of the first trench structure and the second trench structure, and a dielectric layer formed on the first trench structure, the first n+ source region, and the second n+ source region.
摘要翻译：能够降低栅极和漏极之间的电容的功率晶体管包括背面的精神层，形成在背面的精神层上的衬底，形成在衬底上的半导体层以及形成在半导体层上的前侧心理层。半导体层包括包括栅极氧化物层的第一沟槽结构，包括围绕第二沟槽形成的p阱结的第二沟槽结构，形成在第一沟槽结构外部的p体区域和第二沟槽结构，第一n + 源区域形成在p体区域和第一沟槽结构的侧壁旁边，第二n +源极区域形成在p体区域上，在第一沟槽结构的另一个侧壁和第二沟槽结构之间，以及介电层形成在第一沟槽结构上，第一n +源极区域和第二n +源极区域。

30. 发明申请

US20090061584A1 Semiconductor Process for Trench Power MOSFET 审中-公开
标题翻译：沟槽功率MOSFET的半导体工艺
公开(公告)号：US20090061584A1
公开(公告)日：2009-03-05
申请号：US12030194
申请日：2008-02-12
申请人： Wei-Chieh Lin , Jen-Hao Yeh , Ming-Jang Lin , Hsin-Yen Chiu
发明人： Wei-Chieh Lin , Jen-Hao Yeh , Ming-Jang Lin , Hsin-Yen Chiu
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/1095 , H01L29/66727 , H01L29/66734
摘要： The present invention provides a semiconductor process for a trench power MOSFET. The semiconductor process includes providing a substrate, forming an EPI wafer on the surface, performing trench dry etching, performing HTP hard mask oxide deposition and channel self- align implant, performing boron (B) implant and completing the P-body region through a thermal process, performing arsenic (As) implant and completing the n+ source region through a thermal process, and depositing BPSG ILD, front side metal Al, and backside metal Ti/Ni/Ag.
摘要翻译：本发明提供了一种用于沟槽功率MOSFET的半导体工艺。半导体工艺包括提供衬底，在表面上形成EPI晶片，执行沟槽干蚀刻，执行HTP硬掩模氧化物沉积和通道自对准注入，执行硼（B）注入并通过热量完成P体区域处理，通过热处理完成砷（As）注入和完成n +源区，并沉积BPSG ILD，前侧金属Al和背面金属Ti / Ni / Ag。

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