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21. 发明授权

US06949464B1 Contact/via force fill techniques 失效
标题翻译：接触/通过力填充技术
公开(公告)号：US06949464B1
公开(公告)日：2005-09-27
申请号：US09506204
申请日：2000-02-17
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L21/768 , H01L21/44
CPC分类号： H01L21/76882
摘要： An improved semiconductor device fabrication method comprises insertion of a semiconductor wafer into a high-pressure heated chamber and deposition of a low melting-point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.
摘要翻译：改进的半导体器件制造方法包括将半导体晶片插入高压加热室中，并将低熔点铝材料沉积到接触孔中，或者通过覆盖在晶片的衬底上的绝缘层。将晶片加热到铝材料的熔点，并且加压室以迫使铝材料进入接触孔或通孔并消除其中存在的空隙。第二层材料，包括用作掺杂剂源的不同的金属或合金，沉积在沉积的铝材料层的外表面上，并允许其扩散到铝材料层中以形成均匀的铝合金在接触孔或通孔内。还公开了根据该方法制造的半导体器件结构。

22. 发明授权

US06897467B2 Controllable ovanic phase-change semiconductor memory device 失效
标题翻译：可控电流相变半导体存储器件
公开(公告)号：US06897467B2
公开(公告)日：2005-05-24
申请号：US10346994
申请日：2003-01-17
申请人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
发明人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
IPC分类号： H01L27/10 , H01L27/105 , H01L27/24 , H01L45/00 , H01L47/00
CPC分类号： H01L45/06 , G11C2213/52 , H01L27/2463 , H01L45/1233 , H01L45/1273 , H01L45/144 , H01L45/1675 , H01L45/1683
摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same, are disclosed. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.
摘要翻译：公开了一种在硫族化物存储器的电极之间具有减小的接触面积的双相相变半导体存储器件及其形成方法。这样的存储器件通过形成从下电极元件的下表面突出的尖端而形成。在下电极上施加绝缘材料，使得尖端的上表面露出。硫族化物材料和上电极都形成在尖端顶部，或者尖端被蚀刻到绝缘材料中，并且硫族化物材料和上电极沉积在凹部内。这允许使存储器单元变得更小并且允许最小化存储器单元的总体功率需求。

23. 发明授权

US06793736B2 Method of providing high flux of point of use activated reactive species for semiconductor processing 失效
标题翻译：提供高通量使用激活活性物质进行半导体加工的方法
公开(公告)号：US06793736B2
公开(公告)日：2004-09-21
申请号：US10392940
申请日：2003-03-20
申请人： Gurtej S. Sandhu , Trung T. Doan
发明人： Gurtej S. Sandhu , Trung T. Doan
IPC分类号： B08B702
CPC分类号： H01L21/67069
摘要： A method for providing a high flux of point of use activated reactive species for semiconductor processing wherein a workpiece is exposed to a gaseous atmosphere containing a transmission gas that is substantially nonattenuating to preselected wavelengths of electromagnetic radiation. A laminar flow of a gaseous constituent is also provided over a substantially planar surface of the workpiece wherein a beam of the electromagnetic radiation is directed into the gaseous atmosphere such that it converges in the laminar flow to provide maximum beam energy in close proximity to the surface of the workpiece, but spaced a finite distance therefrom. The gaseous constituent is dissociated by the beam producing an activated reactive species that reacts with the surface of the workpiece.
摘要翻译：一种用于提供用于半导体加工的高通量使用激活活性物质的方法，其中工件暴露于含有基本上不衰减到预选的电磁辐射波长的透射气体的气体气氛中。气体成分的层流还设置在工件的基本上平坦的表面上，其中电磁辐射的束被引导到气态气氛中，使得其在层流中会聚以提供最接近表面的最大束能的距离。气体组分由光束解离，产生与工件表面反应的活化反应物质。

24. 发明授权

US06750069B2 Minimally spaced MRAM structures 有权
标题翻译：最小间隔的MRAM结构
公开(公告)号：US06750069B2
公开(公告)日：2004-06-15
申请号：US10454479
申请日：2003-06-05
申请人： D. Mark Durcan , Trung T. Doan , Roger Lee , Dennis Keller , Ren Earl
发明人： D. Mark Durcan , Trung T. Doan , Roger Lee , Dennis Keller , Ren Earl
IPC分类号： H01L21336
CPC分类号： H01L27/222 , B82Y10/00
摘要： A method of forming minimally spaced apart MRAM structures is disclosed. A photolithography technique is employed to define patterns an integrated circuit, the width of which is further reduced by etching to allow formation of patterns used to etch digit line regions with optimum critical dimension between any of the two digit line regions. Subsequent pinned and sense layers of MRAM structures are formed over the minimally spaced digit regions.
摘要翻译：公开了形成最小间隔的MRAM结构的方法。使用光刻技术来定义集成电路的图案，其集成电路的宽度通过蚀刻进一步减小，以允许形成用于蚀刻具有两个数字线区域中的任一个之间的最佳临界尺寸的数字线区域的图案。在最小间隔的数字区域上形成随后的MRAM结构的固定和感测层。

25. 发明授权

US06620680B2 Method of forming a contact structure and a container capacitor structure 有权
公开(公告)号：US06620680B2
公开(公告)日：2003-09-16
申请号：US10080465
申请日：2002-02-22
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L218242
CPC分类号： H01L27/10888 , H01L27/10811 , H01L27/10852 , H01L28/91
摘要： Method for forming at least a portion of a top electrode of a container capacitor and at least a portion of a contact plug in one deposition are described. In one embodiment, the top electrode is formed interior to a bottom electrode of the container capacitor. In another embodiment, the top electrode is formed interior to, and exterior and below a portion of the bottom electrode of the container capacitor. The method of forming a top electrode of a container capacitor and a contact plug with a same deposition is particularly well-suited for high-density memory array formation.

26. 发明授权

US06521931B2 Self-aligned, magnetoresitive random-access memory (MRAM) structure utilizing a spacer containment scheme 有权
标题翻译：采用间隔物容纳方案的自对准磁致结构随机存取存储器（MRAM）结构
公开(公告)号：US06521931B2
公开(公告)日：2003-02-18
申请号：US10040447
申请日：2002-01-09
申请人： Gurtej Sandhu , Roger Lee , Dennis Keller , Trung T. Doan , Max F. Hineman , Ren Earl
发明人： Gurtej Sandhu , Roger Lee , Dennis Keller , Trung T. Doan , Max F. Hineman , Ren Earl
IPC分类号： H01L2976
CPC分类号： H01L27/228 , B82Y10/00 , B82Y25/00 , B82Y40/00 , H01F41/308 , H01L43/08 , H01L43/12
摘要： A method of fabricating a MRAM structure and the resulting structure. The MRAM structure of the invention has the pinned layer recessed within a trench with the upper magnetic layer positioned over it. The method of MRAM fabrication utilizes a spacer processing technique, whereby the upper magnetic layer of the MRAM stack structure is formed between the region defined by the spacers, thereby allowing for self-alignment of the upper magnetic layer over the underlying pinned magnetic layer.
摘要翻译：一种制造MRAM结构的方法及其结果。本发明的MRAM结构具有凹陷在沟槽内的钉扎层，上部磁性层位于其上。 MRAM制造的方法利用间隔物处理技术，由此MRAM层叠结构的上磁性层形成在由间隔物限定的区域之间，从而允许上磁性层在下面的被钉扎的磁性层上自对准。

27. 发明授权

US06423621B1 Controllable ovonic phase-change semiconductor memory device and methods of fabricating the same 有权
公开(公告)号：US06423621B1
公开(公告)日：2002-07-23
申请号：US09964145
申请日：2001-09-25
申请人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
发明人： Trung T. Doan , D. Mark Durcan , Brent D. Gilgen
IPC分类号： H01L2144
摘要： An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

28. 发明授权

US06395628B1 Contact/via force fill techniques 失效
标题翻译：接触/通过力填充技术
公开(公告)号：US06395628B1
公开(公告)日：2002-05-28
申请号：US09506206
申请日：2000-02-17
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L214763
CPC分类号： H01L21/76882
摘要： An improved semiconductor device structure comprises insertion of a semiconductor wafer into a high-pressure heated chamber and the deposition of a low-melting point aluminum material into a contact hole or via and over an insulating layer overlying a substrate of the wafer. The wafer is heated up to the melting point of the aluminum material and the chamber is pressurized to force the aluminum material into the contact holes or vias and eliminate voids present therein. A second layer of material, comprising a different metal or alloy, which is used as a dopant source, is deposited over an outer surface of the deposited aluminum material layer and allowed to diffuse into the aluminum material layer in order to form a homogenous aluminum alloy within the contact hole or via. A semiconductor device structure made according to the method is also disclosed.
摘要翻译：改进的半导体器件结构包括将半导体晶片插入高压加热室中，并且将低熔点铝材料沉积到接触孔中或通过覆盖晶片衬底的绝缘层上或之上沉积。将晶片加热至铝材料的熔点，并对该室进行加压以迫使铝材料进入接触孔或通孔并消除其中存在的空隙。第二层材料，包括用作掺杂剂源的不同的金属或合金，沉积在沉积的铝材料层的外表面上，并允许其扩散到铝材料层中以形成均匀的铝合金在接触孔或通孔内。还公开了根据该方法制造的半导体器件结构。

29. 发明授权

US06391735B1 Container capacitor structure 失效
标题翻译：集装箱电容器结构
公开(公告)号：US06391735B1
公开(公告)日：2002-05-21
申请号：US09653226
申请日：2000-08-31
申请人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
发明人： D. Mark Durcan , Trung T. Doan , Roger R. Lee , Fernando Gonzalez
IPC分类号： H01L2120
CPC分类号： H01L28/91 , H01L27/10811 , H01L27/10817 , H01L27/10852 , H01L27/10888 , H01L28/65 , Y10S257/905
摘要： Disclosed is a container capacitor structure and method of constructing it. An etch mask and etch are used to expose portions of an exterior surface of electrode (“bottom electrodes”) of the container capacitor structure. The etch provides a recess between proximal pairs of container capacitor structures which recess is available for forming additional capacitance. Accordingly, a capacitor dielectric and a top electrode are formed on and adjacent to, respectively, both an interior surface and portions of the exterior surface of the first electrode. Advantageously, surface area common to both the first electrode and second electrodes is increased over using only the interior surface, which provides additional capacitance without a decrease in spacing for clearing portions of the capacitor dielectric and the second electrode away from a contact hole location. Furthermore, such clearing of the capacitor dielectric and the second electrode portions may be done at an upper location of a substrate assembly in contrast to clearing at a bottom location of a contact via.
摘要翻译：公开了一种容器电容器结构及其构造方法。蚀刻掩模和蚀刻用于暴露容器电容器结构的电极（“底部电极”）的外部表面的部分。蚀刻在容器电容器结构的近端对之间提供凹部，该凹槽可用于形成额外的电容。因此，电容器电介质和顶电极分别形成在第一电极的外表面的内表面和部分上并相邻。有利地，仅使用内表面增加了第一电极和第二电极两者共同的表面积，这提供了额外的电容，而不会减小用于清除电容器电介质的部分和第二电极远离接触孔位置的间隔。此外，与在接触通孔的底部位置处的清除相反，电容器电介质和第二电极部分的这种清除可以在衬底组件的上部位置进行。

30. 发明授权

US06335225B1 High density direct connect LOC assembly 失效
公开(公告)号：US06335225B1
公开(公告)日：2002-01-01
申请号：US09026839
申请日：1998-02-20
申请人： Trung T. Doan
发明人： Trung T. Doan
IPC分类号： H01L2144
CPC分类号： H01L24/06 , H01L23/4951 , H01L23/522 , H01L23/525 , H01L24/05 , H01L24/48 , H01L24/72 , H01L2224/02379 , H01L2224/04042 , H01L2224/05554 , H01L2224/0556 , H01L2224/05599 , H01L2224/06136 , H01L2224/48091 , H01L2224/4826 , H01L2224/85399 , H01L2924/00014 , H01L2924/0002 , H01L2924/01005 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2224/45099 , H01L2924/00012 , H01L2224/05552
摘要： An apparatus and method for attaching a semiconductor die to a lead frame wherein the electric contact points of the semiconductor die are relocated to the periphery of the semiconductor die through a plurality of conductive traces. A plurality of leads extends from the lead frame over the conductive traces proximate the semiconductor die periphery and directly attaches to and makes electrical contact with the conductive traces in a LOC arrangement. Alternately, a connector may contact a portion of the conductive trace to make contact therewith.

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