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21. 发明授权

US09397233B2 High voltage deep trench capacitor 有权
标题翻译：高压深沟槽电容器
公开(公告)号：US09397233B2
公开(公告)日：2016-07-19
申请号：US12791996
申请日：2010-06-02
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L27/108 , H01L29/94 , H01L27/13 , H01L49/02 , H01L29/66
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

22. 发明授权

US07276419B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US07276419B2
公开(公告)日：2007-10-02
申请号：US11264068
申请日：2005-10-31
申请人： Vishnu Khemka , John M. Pigott , Ronghua Zhu , Amitava Bose , Randall C. Gray , Jeffrey J. Braun
发明人： Vishnu Khemka , John M. Pigott , Ronghua Zhu , Amitava Bose , Randall C. Gray , Jeffrey J. Braun
IPC分类号： H01L21/336
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device may include first, second, and third semiconductor layers. The first and third layers may have a first dopant type, and the second layer may have a second dopant type. A first region within the third semiconductor layer may have the second dopant type. A second region between the first region and the second semiconductor layer may have the first dopant type. A third region above the second region may have the first dopant type. A fourth semiconductor region adjacent to the third region may have a first concentration of the second dopant type. A source contact region may have a second concentration of the second dopant type adjacent to the third semiconductor region and adjacent to the fourth semiconductor region. The second concentration may be higher than the first concentration.
摘要翻译：半导体器件可以包括第一，第二和第三半导体层。第一和第三层可以具有第一掺杂剂类型，并且第二层可以具有第二掺杂剂类型。第三半导体层内的第一区域可以具有第二掺杂剂类型。第一区域和第二半导体层之间的第二区域可以具有第一掺杂剂类型。第二区域上方的第三区域可以具有第一掺杂剂类型。与第三区域相邻的第四半导体区域可以具有第二掺杂剂类型的第一浓度。源极接触区域可以具有与第三半导体区域相邻并且与第四半导体区域相邻的第二掺杂剂类型的第二浓度。第二浓度可能高于第一浓度。

23. 发明申请

US20070200184A1 Methods and apparatus for a stepped-drift MOSFET 有权
标题翻译：梯形漂移MOSFET的方法和装置
公开(公告)号：US20070200184A1
公开(公告)日：2007-08-30
申请号：US11361624
申请日：2006-02-24
申请人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Todd Roggenbauer
发明人： Ronghua Zhu , Amitava Bose , Vishnu Khemka , Todd Roggenbauer
IPC分类号： H01L29/76 , H01L21/332
CPC分类号： H01L29/7835 , H01L29/0653 , H01L29/1083 , H01L29/456 , H01L29/66659 , H01L29/66681 , H01L29/7816
摘要： A power metal-oxide-semiconductor field effect transistor (MOSFET) (100) incorporates a stepped drift region including a shallow trench insulator (STI) (112) partially overlapped by the gate (114) and which extends a portion of the distance to a drain region (122). A silicide block extends from and partially overlaps STI (112) and drain region (122). The STI (112) has a width that is approximately 50% to 75% of the drift region.
摘要翻译：功率金属氧化物半导体场效应晶体管（MOSFET）（100）包括阶梯状漂移区域，其包括与栅极（114）部分重叠的浅沟槽绝缘体（112），并将距离的一部分延伸到漏区（122）。硅化物块从STI（112）和漏极区（122）延伸并部分重叠。 STI（112）的宽度为漂移区域的大约50％至75％。

24. 发明申请

US20060273402A1 Semiconductor device and method of manufacture 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060273402A1
公开(公告)日：2006-12-07
申请号：US11144569
申请日：2005-06-02
申请人： Vishnu Khemka , Amitava Bose , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Ronghua Zhu
IPC分类号： H01L29/76
CPC分类号： H01L29/7393 , H01L29/0634 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor component and method of manufacture, including an insulated gate bipolar transistor (IGBT) (100, 200, 300, 400) that includes a semiconductor substrate (110, 210, 310, 410) having a first conductivity type and buried semiconductor region (115, 215, 315, 415) having a second conductivity type located above the semiconductor substrate. The IGBT further includes a first semiconductor region (120, 220, 320, 420) having the first conductivity type located above the buried semiconductor region, a second semiconductor region (130, 230, 330, 430) having the first conductivity type located above the first semiconductor region, a third semiconductor region (140, 240, 340, 440) having the second conductivity type located above the first semiconductor region, an emitter (150, 250, 350, 450) having the first conductivity type disposed in the third semiconductor region, and a collector (170, 270, 370, 470) having the first conductivity type disposed in the third semiconductor region. In a particular embodiment, the third semiconductor region and the buried semiconductor region deplete the first semiconductor region in response to a reverse bias applied between the second semiconductor region and the third semiconductor region.
摘要翻译：一种包括绝缘栅双极晶体管（IGBT）（100,200,300,400）的半导体元件和制造方法，包括具有第一导电类型和掩埋半导体区域的半导体衬底（110,210,310,410） 115,215,315,415），其具有位于半导体衬底上方的第二导电类型。 IGBT还包括具有位于掩埋半导体区域上方的第一导电类型的第一半导体区域（120,220,320,420），具有第一导电类型的第二半导体区域（130,230,330,430）位于第二半导体区域第一半导体区域，具有位于第一半导体区域上方的第二导电类型的第三半导体区域（140,240,340,440），具有设置在第三半导体区域中的第一导电类型的发射极（150,250,350,450）以及设置在第三半导体区域中的具有第一导电类型的集电极（170,270,370,470）。在特定实施例中，第三半导体区域和掩埋半导体区域响应于施加在第二半导体区域和第三半导体区域之间的反向偏压而耗尽第一半导体区域。

25. 发明申请

US20100230736A1 High Voltage Deep Trench Capacitor 有权
标题翻译：高压深沟槽电容器
公开(公告)号：US20100230736A1
公开(公告)日：2010-09-16
申请号：US12791996
申请日：2010-06-02
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L27/108
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

26. 发明申请

US20070224738A1 Semiconductor device with a multi-plate isolation structure 有权
标题翻译：具有多板隔离结构的半导体器件
公开(公告)号：US20070224738A1
公开(公告)日：2007-09-27
申请号：US11390918
申请日：2006-03-27
申请人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Todd Roggenbauer , Ronghua Zhu
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/823878 , H01L21/763 , H01L21/764 , H01L21/823481
摘要： A microelectronic assembly and a method for constructing a microelectronic assembly are provided. The microelectronic assembly may include a semiconductor substrate with an isolation trench (62) formed therein. The isolation trench (62) may have first and second opposing inner walls (74, 76) and a floor (78). First and second conductive plates (106) may be formed over the first and second opposing inner walls (74, 76) of the isolation trench (62) respectively such that there is a gap (90) between the first and second conductive plates (106). First and second semiconductor devices (114) may be formed in the semiconductor substrate on opposing sides of the isolation trench (62). The method may include forming a trench (62) in a semiconductor substrate, forming first and second conductive plates (106) within the trench, and forming first and second semiconductor devices (114) in the semiconductor substrate on opposing sides of the trench (62).
摘要翻译：提供微电子组件和构造微电子组件的方法。微电子组件可以包括其中形成有隔离沟槽（62）的半导体衬底。隔离沟槽（62）可以具有第一和第二相对的内壁（74,76）和底板（78）。第一和第二导电板（106）可以分别形成在隔离沟槽（62）的第一和第二相对的内壁（74,76）上，使得在第一和第二导电板（106）之间存在间隙（90））。可以在隔离沟槽（62）的相对侧上的半导体衬底中形成第一和第二半导体器件（114）。该方法可以包括在半导体衬底中形成沟槽（62），在沟槽内形成第一和第二导电板（106），并且在沟槽（62）的相对侧上的半导体衬底中形成第一和第二半导体器件（114））。

27. 发明申请

US20070096225A1 Semiconductor device and method for forming the same 有权
公开(公告)号：US20070096225A1
公开(公告)日：2007-05-03
申请号：US11264068
申请日：2005-10-31
申请人： Vishnu Khemka , John Pigott , Ronghua Zhu , Amitava Bose , Randall Gray , Jeffrey Braun
发明人： Vishnu Khemka , John Pigott , Ronghua Zhu , Amitava Bose , Randall Gray , Jeffrey Braun
IPC分类号： H01L29/76
CPC分类号： H01L29/0847 , H01L29/0653 , H01L29/1083 , H01L29/66659 , H01L29/7835
摘要： A semiconductor device may include first, second, and third semiconductor layers. The first and third layers may have a first dopant type, and the second layer may have a second dopant type. A first region within the third semiconductor layer may have the second dopant type. A second region between the first region and the second semiconductor layer may have the first dopant type. A third region above the second region may have the first dopant type. A fourth semiconductor region adjacent to the third region may have a first concentration of the second dopant type. A source contact region may have a second concentration of the second dopant type adjacent to the third semiconductor region and adjacent to the fourth semiconductor region. The second concentration may be higher than the first concentration.

28. 发明申请

US20070045767A1 Semiconductor devices employing poly-filled trenches 有权
标题翻译：采用多晶填充沟槽的半导体器件
公开(公告)号：US20070045767A1
公开(公告)日：2007-03-01
申请号：US11213069
申请日：2005-08-25
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose
IPC分类号： H01L29/00
CPC分类号： H01L29/0878 , H01L23/3677 , H01L29/0649 , H01L29/0653 , H01L29/0847 , H01L29/1083 , H01L29/1087 , H01L29/66659 , H01L29/66681 , H01L29/732 , H01L29/7816 , H01L29/7824 , H01L29/7835 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Structure and method are provided for semiconductor devices. The devices include trenches filled with highly doped polycrystalline semiconductor, extending from the surface into the body of the device for, among other things: (i) reducing substrate current injection, (ii) reducing ON-resistance and/or (iii) reducing thermal impedance to the substrate. For isolated LDMOS devices, the resistance between the lateral isolation wall (tied to the source) and the buried layer is reduced, thereby reducing substrate injection current. When placed in the drain of a lateral device or in the collector of a vertical device, the poly-filled trench effectively enlarges the drain or collector region, thereby lowering the ON-resistance. For devices formed on an oxide isolation layer, the poly-filled trench desirably penetrates this isolation layer thereby improving thermal conduction from the active regions to the substrate. The poly filled trenches are conveniently formed by etch and refill. Significant area savings are also achieved.
摘要翻译：为半导体器件提供了结构和方法。这些器件包括填充有高掺杂多晶半导体的沟槽，从表面延伸到器件的主体中，其中包括：（i）减少衬底电流注入，（ii）降低导通电阻和/或（iii）减少热对基片的阻抗。对于孤立的LDMOS器件，横向隔离壁（连接到源极）和掩埋层之间的电阻降低，从而降低衬底注入电流。当放置在垂直装置的横向装置或收集器的漏极中时，多晶硅填充沟槽有效地放大了漏极或集电极区域，从而降低了导通电阻。对于形成在氧化物隔离层上的器件，多晶填充沟槽期望地穿透该隔离层，从而改善从有源区到衬底的热传导。多孔填充沟槽通过蚀刻和再填充方便地形成。也实现了显着的面积节省。

29. 发明授权

US07732274B2 High voltage deep trench capacitor 失效
标题翻译：高压深沟槽电容器
公开(公告)号：US07732274B2
公开(公告)日：2010-06-08
申请号：US11752608
申请日：2007-05-23
申请人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
发明人： Ronghua Zhu , Vishnu Khemka , Amitava Bose , Todd C. Roggenbauer
IPC分类号： H01L21/8242
CPC分类号： H01L29/94 , H01L27/13 , H01L28/91 , H01L29/66181
摘要： A semiconductor process and apparatus provide a high voltage deep trench capacitor structure (10) that is integrated in an integrated circuit, alone or in alignment with a fringe capacitor (5). The deep trench capacitor structure is constructed from a first capacitor plate (4) that is formed from a doped n-type SOI semiconductor layer (e.g., 4a-c). The second capacitor plate (3) is formed from a doped p-type polysilicon layer (3a) that is tied to the underlying substrate (1).
摘要翻译：半导体工艺和装置提供集成在集成电路中的单独或与边缘电容器（5）对准的高电压深沟槽电容器结构（10）。深沟槽电容器结构由由掺杂的n型SOI半导体层（例如4a-c）形成的第一电容器板（4）构成。第二电容器板（3）由连接到下面的衬底（1）的掺杂p型多晶硅层（3a）形成。

30. 发明授权

US07608908B1 Robust deep trench isolation 失效
标题翻译：坚固的深沟隔离
公开(公告)号：US07608908B1
公开(公告)日：2009-10-27
申请号：US12125613
申请日：2008-05-22
申请人： Vishnu Khemka , Amitava Bose , Michael C. Butner , Bernhard H. Grote , Tahir A. Khan , Shifeng Shen , Ronghua Zhu
发明人： Vishnu Khemka , Amitava Bose , Michael C. Butner , Bernhard H. Grote , Tahir A. Khan , Shifeng Shen , Ronghua Zhu
IPC分类号： H01L29/00 , H01L29/167
CPC分类号： H01L21/76264
摘要： Higher voltage device isolation structures (40, 60, 70, 80, 90, 90′) are provided for semiconductor integrated circuits having strongly doped buried layers (24, 24″). One or more dielectric lined deep isolation trenches (27, 27′, 27″, 27′″) separates adjacent device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912). Electrical breakdown (BVdss) between the device regions (411, 412; 611, 612; 711, 712; 811, 812; 911, 912) and the oppositely doped substrate (22, 22″) is found to occur preferentially where the buried layer (24, 24″) intersects the dielectric sidewalls (273, 274; 273′, 274′; 273″, 274″) of the trench (27, 27′, 27″, 27′″). The breakdown voltage (BVdss) is increased by providing a more lightly doped region (42, 42″, 62, 72, 82) of the same conductivity type as the buried layer (24, 24″), underlying the buried layer (24, 24″) at the trench sidewalls (273, 274; 273′, 274′; 273″, 274″). The more lightly doped region's (42, 42″, 62, 72, 82) dopant concentration is desirably 1E4 to 2E2 times less than the buried layer (24, 24″) and it extends substantially entirely beneath the buried layer (24, 24″) or to a distance (724, 824) extending about 0.5 to 2.0 micro-meters from the trench sidewall (273, 274; 273′, 274′; 273″, 274″). In a preferred embodiment, the trench (27, 27′) is split into two portions (271, 272; 271′, 272′) with the semiconductor therein (475, 675, 775, 875) ohmically coupled to the substrate (22).
摘要翻译：为具有强掺杂掩埋层（24,24“）的半导体集成电路提供更高电压器件隔离结构（40,60,70,80,90,90'）。一个或多个电介质衬里的深隔离沟槽（27,27'，27“，27”'）分隔相邻的器件区域（411,412; 611,612; 711,712; 811,812; 911,912）。发现器件区域（411,412; 611,612; 711,712; 811,812; 911,912）和相对掺杂的衬底（22,22“）之间的电击穿（BVdss）优先发生在埋置层（24,24“）与沟槽（27,27'，27”，27“'）的电介质侧壁（273,274; 273'，274'; 273”，274“）相交。通过提供与掩埋层下面的掩埋层（24,24“）相同的导电类型的更轻掺杂区域（42,42”，62,72,82）来增加击穿电压（BVdss）（273,274; 273'，274'; 273“，”274“）上。掺杂浓度越高的掺杂区越好，比掩埋层（24,24“）要小1〜4埃，比埋入层（24，24”）大致全部下降，距离沟槽侧壁（273,274; 273'，274'; 273“，”274“）延伸约0.5至2.0微米的距离（724,824）。在优选实施例中，沟槽（27,27'）被分成两部分（271,272; 271'，272'），其中半导体在其中欧姆耦合到衬底（22），其中（475,675,775,875）。

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