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21. 发明授权

US06965603B1 Circuits for combining ATM and packet data on an optical fiber 有权
标题翻译：用于将ATM和分组数据组合在光纤上的电路
公开(公告)号：US06965603B1
公开(公告)日：2005-11-15
申请号：US09528802
申请日：2000-03-20
申请人： Bidyut Parruck , Joseph A. Nguyen , Chulanur Ramakrishnan
发明人： Bidyut Parruck , Joseph A. Nguyen , Chulanur Ramakrishnan
IPC分类号： H04L12/56
CPC分类号： H04L12/5601 , H04L2012/5605 , H04L2012/5652 , H04L2012/5665
摘要： An architecture for transmitting both ATM cells and data packets via a single optical fiber and for receiving ATM cells and data packets via a single optical fiber. The architecture includes both a transmission convergence device (TCD) circuit and a segmentation-and-reassembly (SAR) circuit and is implemented as integrated circuits, preferably as part of a router to eliminate the need for a SONET multiplexer.
摘要翻译：一种用于经由单个光纤传送ATM信元和数据包并经由单个光纤接收ATM信元和数据包的架构。该架构包括传输汇聚设备（TCD）电路和分段重组（SAR）电路，并且被实现为集成电路，优选地作为路由器的一部分，以消除对SONET多路复用器的需要。

22. 发明授权

US06751214B1 Methods and apparatus for dynamically allocating bandwidth between ATM cells and packets 有权
标题翻译：在ATM信元和数据包之间动态分配带宽的方法和装置
公开(公告)号：US06751214B1
公开(公告)日：2004-06-15
申请号：US09539478
申请日：2000-03-30
申请人： Bidyut Parruck , Joseph A. Nguyen , Chulanur Ramakrishnan
发明人： Bidyut Parruck , Joseph A. Nguyen , Chulanur Ramakrishnan
IPC分类号： H04J324
CPC分类号： H04L12/5602 , H04J3/1617 , H04J3/1682 , H04J2203/0069 , H04J2203/0089 , H04L12/5601 , H04L2012/5605 , H04L2012/5632 , H04L2012/5652 , H04L2012/5665 , H04L2012/5672
摘要： A method for dynamically allocating bandwidth among ATM cells and packets scheduled for output from an aggregation multiplexer of a transport-layer device configured to multiplex both ATM cells and packets onto the same channel of an optical fiber. The method includes local control and relative priority lookup of incoming ATM cells and packets to support output decision. When compared to currently employed methods, the required level of coordination with the receiving circuit for dynamic bandwidth allocation is substantially lower, thereby reducing operational complexity for network operators and latency for critical data when reallocating bandwidth.
摘要翻译：一种用于动态分配ATM信元之间的带宽和被调度从输出层传输层设备的聚合多路复用器输出的分组的方法，该传输层设备被配置为将ATM信元和分组复用到光纤的同一信道上。该方法包括本地控制和对ATM信元和数据包的相对优先级查询，以支持输出决策。与当前使用的方法相比，用于动态带宽分配的接收电路所需的协调水平显着降低，从而降低网络运营商的运营复杂性，并在重新分配带宽时降低关键数据的延迟。

23. 发明授权

US06198723B1 Asynchronous transfer mode traffic shapers 失效
标题翻译：异步传输模式流量整形器
公开(公告)号：US06198723B1
公开(公告)日：2001-03-06
申请号：US09060228
申请日：1998-04-14
申请人： Bidyut Parruck , Pramod B. Phadke , Sachin N. Pradhan , Akash Bansal , Kishalay Haldar
发明人： Bidyut Parruck , Pramod B. Phadke , Sachin N. Pradhan , Akash Bansal , Kishalay Haldar
IPC分类号： H04J316
CPC分类号： H04L12/5602 , H04L2012/5651 , H04L2012/5672 , H04L2012/5679 , H04L2012/568 , H04Q11/0478
摘要： The invention relates, in one embodiment, a computer-implemented method for shaping the output of cells on an output path of a data transmitting device. The data transmitting device is configured for switching the cells from a plurality of input paths to the output path to a network. In one embodiment the method includes sorting a plurality of queues, each queue including a plurality of cells associated with a communication device. The plurality of queues are arranged according to a weight and a data rate associated with each plurality of cells resulting in a plurality of sorted queues of queues. An aggregate output of cells from each sorted queue of queues is regulated based upon the data rates of the queues of the each sorted queue of queues. And, the output of the aggregate output of cells from each sorted queue of queues is regulated based upon the weights of the each sorted queue of queues, such that the scheduled output is coupled to the output path. The scheduled output conforms to a plurality of characteristics of the network, such that the network is efficiently used to carry the cells from the plurality of input paths to a plurality of communication devices. Thereby, apparatuses and methods of traffic shaping are disclosed herein.
摘要翻译：本发明在一个实施例中涉及一种计算机实现的方法，用于对数据发送设备的输出路径上的单元的输出进行整形。数据发送装置被配置为将小区从多个输入路径切换到到网络的输出路径。在一个实施例中，该方法包括对多个队列进行排序，每个队列包括与通信设备相关联的多个单元。多个队列根据权重和与每个多个小区相关联的数据速率被排列，导致多个排队的队列队列。基于队列的每个排序队列的队列的数据速率来调整来自队列的每个排序队列的单元的聚合输出。并且，基于队列的每个排序队列的权重来调整来自队列的每个排序队列的单元的聚合输出的输出，使得调度输出耦合到输出路径。调度输出符合网络的多个特性，使得网络被有效地用于将小区从多个输入路径传送到多个通信设备。因此，本文公开了流量整形的装置和方法。

24. 发明授权

US07342942B1 Multi-service segmentation and reassembly device that maintains only one reassembly context per active output port 有权
标题翻译：多业务分段和重组设备，每个活动输出端口只保留一个重组上下文
公开(公告)号：US07342942B1
公开(公告)日：2008-03-11
申请号：US09851565
申请日：2001-05-08
申请人： Bidyut Parruck , Chulanur Ramakrishnan
发明人： Bidyut Parruck , Chulanur Ramakrishnan
IPC分类号： H04L12/56
CPC分类号： H04L47/621 , H04L12/5601 , H04L12/5602 , H04L47/22 , H04L47/2441 , H04L47/35 , H04L47/50 , H04L49/90 , H04L49/9094 , H04L2012/5652 , H04L2012/5658 , H04L2012/5667 , H04L2012/5669
摘要： A multi-service segmentation and reassembly (MS-SAR) integrated circuit is disposed on a line card in a router or switch. The MS-SAR can operate in an ingress mode so that it receives packet and/or cell format data and forwards that data to either a packet-based or a cell-based switch fabric. The MS-SAR can also operate in an egress mode so that it receives data from either a packet-based or a cell-based switch fabric and outputs that data in packet and/or cell format. The MS-SAR has a data path through which many flows of different traffic types are processed simultaneously. Each flow is processed by functional blocks along the data path in accordance with one of several application types, the application type for a flow being predetermined by the host processor of the router or switch. Segmentation, reassembly and partitioning techniques are disclosed that reduce costs and facilitate high-speed operation.
摘要翻译：在路由器或交换机的线路卡上设置多业务分段和重组（MS-SAR）集成电路。 MS-SAR可以以入口模式操作，以便它接收分组和/或小区格式数据，并将该数据转发到基于分组或基于小区的交换结构。 MS-SAR还可以以出口模式操作，从而从基于分组或基于小区的交换结构接收数据，并以分组和/或小区格式输出该数据。 MS-SAR具有数据路径，同时处理不同流量类型的许多流。根据多个应用类型之一，沿着数据路径的功能块处理每个流程，流程的应用类型由路由器或交换机的主机处理器预先确定。公开了降低成本并促进高速运行的分段，重组和分区技术。

25. 发明授权

US07298738B1 Backpressuring using a serial bus interface and a status switch cell 有权
标题翻译：使用串行总线接口和状态开关单元进行反压
公开(公告)号：US07298738B1
公开(公告)日：2007-11-20
申请号：US09976206
申请日：2001-10-12
申请人： Bidyut Parruck , Chulanur Ramakrishnan
发明人： Bidyut Parruck , Chulanur Ramakrishnan
IPC分类号： H04L12/56
CPC分类号： H04L47/621 , H04L12/5601 , H04L12/5602 , H04L47/22 , H04L47/2441 , H04L47/35 , H04L47/50 , H04L49/90 , H04L49/9094 , H04L2012/5652 , H04L2012/5658 , H04L2012/5667 , H04L2012/5669
摘要： A multi-service segmentation and reassembly (MS-SAR) integrated circuit is disposed on a line card in a router or switch. The MS-SAR can operate in an ingress mode so that it receives packet and/or cell format data and forwards that data to either a packet-based or a cell-based switch fabric. The MS-SAR can also operate in an egress mode so that it receives data from either a packet-based or a cell-based switch fabric and outputs that data in packet and/or cell format. The MS-SAR has a data path through which many flows of different traffic types are processed simultaneously. Each flow is processed by functional blocks along the data path in accordance with one of several application types, the application type for a flow being predetermined by the host processor of the router or switch. Segmentation, reassembly and partitioning techniques are disclosed that reduce costs and facilitate high-speed operation.
摘要翻译：在路由器或交换机的线路卡上设置多业务分段和重组（MS-SAR）集成电路。 MS-SAR可以以入口模式操作，以便它接收分组和/或小区格式数据，并将该数据转发到基于分组或基于小区的交换结构。 MS-SAR还可以以出口模式操作，从而从基于分组或基于小区的交换结构接收数据，并以分组和/或小区格式输出该数据。 MS-SAR具有数据路径，同时处理不同流量类型的许多流。根据多个应用类型之一，沿着数据路径的功能块处理每个流程，流程的应用类型由路由器或交换机的主机处理器预先确定。公开了降低成本并促进高速运行的分段，重组和分区技术。

26. 发明授权

US07286566B1 Multi-service segmentation and reassembly device that maintains reduced number of segmentation contexts 有权
标题翻译：多业务分段和重组装置保持分割上下文数量的减少
公开(公告)号：US07286566B1
公开(公告)日：2007-10-23
申请号：US09976213
申请日：2001-10-12
申请人： Bidyut Parruck , Chulanur Ramakrishnan
发明人： Bidyut Parruck , Chulanur Ramakrishnan
IPC分类号： H04L12/54
CPC分类号： H04L49/602 , H04L49/30 , H04L2012/5605 , H04L2012/5652 , H04L2012/5667
摘要： A multi-service segmentation and reassembly (MS-SAR) integrated circuit is disposed on a line card in a router or switch. The MS-SAR can operate in an ingress mode so that it receives packet and/or cell format data and forwards that data to either a packet-based or a cell-based switch fabric. The MS-SAR can also operate in an egress mode so that it receives data from either a packet-based or a cell-based switch fabric and outputs that data in packet and/or cell format. The MS-SAR has a data path through which many flows of different traffic types are processed simultaneously. Each flow is processed by functional blocks along the data path in accordance with one of several application types, the application type for a flow being predetermined by the host processor of the router or switch. Segmentation, reassembly and partitioning techniques are disclosed that reduce costs and facilitate high-speed operation.
摘要翻译：在路由器或交换机的线路卡上设置多业务分段和重组（MS-SAR）集成电路。 MS-SAR可以以入口模式操作，以便它接收分组和/或小区格式数据，并将该数据转发到基于分组或基于小区的交换结构。 MS-SAR还可以以出口模式操作，从而从基于分组或基于小区的交换结构接收数据，并以分组和/或小区格式输出该数据。 MS-SAR具有数据路径，同时处理不同流量类型的许多流。根据多个应用类型之一，沿着数据路径的功能块处理每个流程，流程的应用类型由路由器或交换机的主机处理器预先确定。公开了降低成本并促进高速运行的分段，重组和分区技术。

27. 发明授权

US07142564B1 Multi-service segmentation and reassembly device with a single data path that handles both cell and packet traffic 有权
标题翻译：具有处理单元和分组流量的单个数据路径的多业务分段和重组设备
公开(公告)号：US07142564B1
公开(公告)日：2006-11-28
申请号：US09976522
申请日：2001-10-12
申请人： Bidyut Parruck , Chulanur Ramakrishnan
发明人： Bidyut Parruck , Chulanur Ramakrishnan
IPC分类号： H04L12/54
CPC分类号： H04L47/621 , H04L12/5601 , H04L12/5602 , H04L47/22 , H04L47/2441 , H04L47/35 , H04L47/50 , H04L49/90 , H04L49/9094 , H04L2012/5652 , H04L2012/5658 , H04L2012/5667 , H04L2012/5669
摘要： A multi-service segmentation and reassembly (MS-SAR) integrated circuit is disposed on a line card in a router or switch. The MS-SAR can operate in an ingress mode so that it receives packet and/or cell format data and forwards that data to either a packet-based or a cell-based switch fabric. The MS-SAR can also operate in an egress mode so that it receives data from either a packet-based or a cell-based switch fabric and outputs that data in packet and/or cell format. The MS-SAR has a data path through which many flows of different traffic types are processed simultaneously. Each flow is processed by functional blocks along the data path in accordance with one of several application types, the application type for a flow being predetermined by the host processor of the router or switch. Segmentation, reassembly and partitioning techniques are disclosed that reduce costs and facilitate high-speed operation.
摘要翻译：在路由器或交换机的线路卡上设置多业务分段和重组（MS-SAR）集成电路。 MS-SAR可以以入口模式操作，以便它接收分组和/或小区格式数据，并将该数据转发到基于分组或基于小区的交换结构。 MS-SAR还可以以出口模式操作，从而从基于分组或基于小区的交换结构接收数据，并以分组和/或小区格式输出该数据。 MS-SAR具有数据路径，同时处理不同流量类型的许多流。根据多个应用类型之一，沿着数据路径的功能块处理每个流程，流程的应用类型由路由器或交换机的主机处理器预先确定。公开了降低成本并促进高速运行的分段，重组和分区技术。

28. 发明授权

US06810039B1 PROCESSOR-BASED ARCHITECTURE FOR FACILITATING INTEGRATED DATA TRANSFER BETWEEN BOTH ATM AND PACKET TRAFFIC WITH A PACKET BUS OR PACKET LINK, INCLUDING BIDIRECTIONAL ATM-TO-PACKET FUNCTIONALLY FOR ATM TRAFFIC 有权
标题翻译：基于处理器的架构，用于利用分组总线或分组链路来促进两个ATM和分组交换之间的集成数据传输，其中包括用于ATM交通功能的双向ATM到分组
公开(公告)号：US06810039B1
公开(公告)日：2004-10-26
申请号：US09539476
申请日：2000-03-30
申请人： Bidyut Parruck , Joseph A. Nguyen , Chulanur Ramakrishnan
发明人： Bidyut Parruck , Joseph A. Nguyen , Chulanur Ramakrishnan
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04J3/1617 , H04L2012/5605 , H04L2012/5618 , H04L2012/5652 , H04L2012/5665
摘要： A processor-based architecture having a processor for facilitating transmission between an ATM port, a first packet port, and a second packet port. The processor-based architecture includes random access memory and a processor coupled to the random access memory and configured to receive ATM cells from the ATM port and first packets from the first packet port and for outputting second packets containing information from both the ATM cells and the first packets on the second packet port. The processor-based architecture includes segmentation-and-reassembly to facilitate bi-directional packet-to-ATM translation functionality. In one embodiment, the processor-based architecture is implemented on a single card and includes dynamic traffic management between ATM and packet traffic.
摘要翻译：一种基于处理器的架构，其具有用于促进ATM端口，第一分组端口和第二分组端口之间的传输的处理器。基于处理器的架构包括随机存取存储器和耦合到随机存取存储器的处理器，并且被配置为从ATM端口接收ATM信元和来自第一分组端口的第一分组，并且用于输出包含来自ATM信元和第二个数据包端口上的第一个数据包。基于处理器的架构包括分段和重组，以促进双向分组到ATM转换功能。在一个实施例中，基于处理器的架构在单个卡上实现，并且包括ATM和分组业务之间的动态业务管理。

29. 发明授权

US06229812B1 Scheduling techniques for data cells in a data switch 失效
公开(公告)号：US06229812B1
公开(公告)日：2001-05-08
申请号：US08872530
申请日：1997-06-11
申请人： Bidyut Parruck , Chetan V. Sanghvi , Vinay Kumar Bhasin , Makarand Dharmapurikar , Uday Govind Joshi
发明人： Bidyut Parruck , Chetan V. Sanghvi , Vinay Kumar Bhasin , Makarand Dharmapurikar , Uday Govind Joshi
IPC分类号： H04L1256
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1553 , H04L49/1576 , H04L2012/5635 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683
摘要： A computer-implemented method for scheduling cells output on an output path of a data switch. The data switch is configured for switching the cells from a plurality of input paths to the output path. The method includes providing a plurality of queues, each queue of the plurality of queues having an assigned weight, respective ones of the plurality of input paths being coupled to respective ones of the plurality of queues. The method further includes providing a plurality of queues of queues. The plurality of queues being coupled to the plurality of queues of queues with queues of the plurality of queues having a similar weight being coupled a same queue of queues of the plurality of queues of queues. There is further included providing a scheduler, the plurality of queues of queues being input into the scheduler, the scheduler being coupled to the output path.

30. 发明授权

US6069893A Asynchronous transfer mode switching architectures having connection buffers 失效
公开(公告)号：US6069893A
公开(公告)日：2000-05-30
申请号：US959056
申请日：1997-10-28
申请人： Bidyut Parruck , Chetan V. Sanghvi , Vinay Kumar Bhasin , Makarand Dharmapurikar , Uday Govind Joshi
发明人： Bidyut Parruck , Chetan V. Sanghvi , Vinay Kumar Bhasin , Makarand Dharmapurikar , Uday Govind Joshi
IPC分类号： G06T11/00 , H04L12/54 , H04L12/70 , H04L12/933 , H04L12/28 , H04L12/56
CPC分类号： H04L12/5601 , H04L49/106 , H04L49/1553 , H04L49/1576 , H04L2012/5635 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681 , H04L2012/5682 , H04L2012/5683
摘要： Improved methods and apparatus to facilitate switching Asynchronous Transfer Mode (ATM) cells through an ATM switching circuit are disclosed. The improved methods and apparatus facilitate the implementation of per virtual connection buffering, per virtual connection arbitration of ATM cells, and/or per virtual connection back-pressuring to improve switching efficiency and/or reduce the complexity and/or costs of the ATM switching circuit.

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